Infineon-Technologies-IRF9540NSTRLPBF
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PD – 96030
IRF9540NSPbF
IRF9540NLPbF
HEXFET
®
Power MOSFET
l
Advanced Process Technology
l
Ultra Low On-Resistance
l
150°C Operating Temperature
l
Fast Switching
l
Repetitive Avalanche Allowed up to Tjmax
l
Some Parameters are Different from
IRF9540NS/L
D
V
DSS
= -100V
R
DS(on)
= 117m
Ω
G
I
D
= -23A
S
l
P-Channel
l
Lead-Free
D
Description
D
Features of this design
are a 150°C junction
operating temperature, fast switching speed and
improve
d
r
epetitiv
e
a
valanch
e
r
atin
g
.
T
hes
e
f
ea-
tures combine to make this design an extremely
efficient and reliable device for use in
a wide
variety of other applications.
S
S
D
D
G
G
D
2
Pak
TO-262
IRF9540NLPbF
IRF9540NSPbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Parameter
Max.
Units
I
I
I
@ T
C
= 25°C
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ -10V
Continuous Drain Current, VGS @ -10V
Pulsed Drain Current
-23
A
D
D
-14
-92
3.1
110
DM
P
P
@T
A
= 25°C
@T
C
= 25°C
Maximum Power Dissipation
Maximum Power Dissipation
W
D
D
Linear Derating Factor
0.9
W/°C
V
V
Gate-to-Source Voltage
Single Pulse Avalanche Energy
± 20
GS
E
AS
I
AR
84
-14
11
mJ
A
Avalanche Current
Repetitive Avalanche Energy
E
AR
dv/dt
mJ
Peak Diode Recovery dv/dt
Operating Junction and
-13
V/ns
°C
T
T
-55 to
+ 150
J
Storage Temperature Range
STG
Soldering Temperature, for 10 seconds
300 (1.6mm from case )
Thermal Resistance
Parameter
Typ.
–––
Max.
1.1
Units
°C/W
R
θ
JC
Junction-to-Case
Junction-to-Ambient (PCB Mount, steady state)
R
θ
JA
–––
40
1
09/30/05
IRF9540NS/LPbF
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max.
Units
-100 –––
–––
Conditions
V
GS
= 0V, I
D
= -250µA
V
(BR)DSS
∆Β
V
DSS
/
∆
T
J
R
DS(on)
V
GS(th)
gfs
V
Breakdown Voltage Temp. Coefficient
––– -0.11 ––– V/°C
Reference to 25°C, I
D
= -1mA
m
Ω
V
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
–––
-2.0
5.6
–––
–––
–––
–––
117
-4.0
–––
-50
V
GS
= -10V, I
D
= -14A
V
DS
= V
GS
, I
D
= -250µA
V
DS
= -50V, I
D
= -14A
Forward Transconductance
S
I
DSS
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
µA V
DS
= -100V, V
GS
= 0V
V
DS
= -80V, V
GS
= 0V, T
J
= 125°C
nA V
GS
= -20V
V
GS
= 20V
––– -250
––– 100
––– -100
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Q
g
Q
gs
Q
gd
t
d(on)
t
r
73
13
38
13
64
40
45
4.5
110
20
nC I
D
= -14A
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Turn-On Delay Time
V
DS
= -80V
57
V
GS
= -10V
–––
–––
–––
–––
–––
ns
V
DD
= -50V
Rise Time
I
D
= -14A
t
d(off)
t
f
Turn-Off Delay Time
R
G
= 5.1
Ω
Fall Time
V
GS
= -10V
L
D
Internal Drain Inductance
nH Between
lead,
6mm (0.25in.)
from package
L
S
Internal Source Inductance
–––
7.5
–––
and center of die contact
C
iss
C
oss
C
rss
Input Capacitance
––– 1450 –––
pF V
GS
= 0V
V
DS
= -25V
Output Capacitance
–––
–––
430
230
–––
–––
Reverse Transfer Capacitance
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max.
Units
Conditions
I
S
Continuous Source Current
–––
–––
-23
MOSFET symbol
(Body Diode)
A
showing the
I
SM
Pulsed Source Current
(Body Diode)
–––
–––
-92
integral reverse
p-n junction diode.
V
SD
t
rr
T =
25°C, I
= -14A, V
= 0V
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
–––
–––
–––
–––
140
-1.6
210
V
J
S
GS
T =
25°C, I
= -14A, V
DD
= -25V
ns
J
F
Q
rr
t
on
890 1340
nC di/dt
= -100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Pulse width
≤
300µs; duty cycle
≤
2%.
Repetitive rating;
pulse width limited by
max. junction temperature. ( See fig. 11)
Starting T
J
= 25°C, L = 0.88mH
ꢀ
When mounted on 1″ square PCB (FR-4or G-10
Material). For
recommended footprint and soldering
techniques refer to application note #AN-994.
R
G
= 25
Ω
, I
AS
= -14A. (See Figure 12)
I
SD
≤
-14A, di/dt
≤
-620A/µs, V
DD
≤
V
(BR)DSS
,
T
J
≤
150°C.
2
IRF9540NS/LPbF
1000
100
10
1000
100
10
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
-4.5V
VGS
TOP
TOP
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
-4.5V
BOTTOM
BOTTOM
-4.5V
1
1
-4.5V
≤
60µs PULSE WIDTH
≤
60µs PULSE WIDTH
Tj = 150°C
Tj = 25°C
0.1
0.1
0.1
1
10
100
0.1
1
10
100
-V ,
Drain-to-Source Voltage (V)
-V ,
Drain-to-Source Voltage (V)
DS
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
100
10
1
2.0
I
= -14A
T
= 25°C
D
J
V
= -10V
GS
T
= 150°C
J
1.5
1.0
0.5
V
= -50V
DS
≤
60µs PULSE WIDTH
0.1
2
4
6
8
10 12 14
-60 -40 -20
T
0
20 40 60 80
100 120 140 160
, Junction Temperature (°C)
J
-V ,
Gate-to-Source Voltage (V)
GS
Fig 4.
Normalized On-Resistance
Fig 3.
Typical Transfer Characteristics
vs. Temperature
3
IRF9540NS/LPbF
10000
20
16
12
8
V
C
= 0V,
f = 1 MHZ
GS
I =
-14A
D
= C
+ C
, C
SHORTED
iss
gs
gd ds
V
V
V
= -80V
= -50V
= -20V
C
= C
DS
DS
DS
rss
gd
C
= C
+ C
oss
ds
gd
C
iss
1000
C
oss
C
rss
4
100
0
1
10
-V ,
Drain-to-Source Voltage (V)
100
0
20
40
60
80
100
120
Q , Total
Gate Charge (nC)
DS
G
Fig 5.
Typical Capacitance vs.
Fig 6.
Typical Gate Charge vs.
Drain-to-Source Voltage
Gate-to-Source Voltage
1000
100
10
100
10
1
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 150°C
J
100µsec
1msec
T
= 25°C
J
10msec
1
Tc = 25°C
Tj = 150°C
Single Pulse
V
= 0V
GS
0.1
0.1
1
10
100
1000
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
-V
DS
, Drain-toSource Voltage (V)
-V ,
Source-to-Drain Voltage (V)
SD
Fig 7.
Typical Source-Drain Diode
Fig 8.
Maximum Safe Operating Area
Forward Voltage
4
IRF9540NS/LPbF
R
D
V
DS
V
GS
24
20
16
12
8
D.U.T.
R
G
–
+
V
DD
-10V
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
Fig 10a.
Switching Time Test Circuit
t
t
r
t
t
f
d(on)
d(off)
V
GS
10%
4
0
25
50
75
100
125
150
90%
V
T
, Case Temperature (°C)
DS
C
Fig 9.
Maximum Drain Current vs.
Fig 10b.
Switching Time Waveforms
Case Temperature
10
1
0.1
D = 0.50
0.20
0.10
0.05
R
1
R
1
R
2
R
2
R
3
R
3
τ
i (sec)
Ri (°C/W)
τ
J
τ
J
τ
τ
C
0.1737838 0.0000610
0.4335992 0.0019590
0.4921007 0.0260060
1
τ
1
Ci=
τ
i
/
Ri
τ
τ
2
τ
2
3
τ
3
0.02
0.01
0.01
0.001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
IRF9540NS/LPbF
L
V
DS
350
300
250
200
150
100
50
I
D
D.U.T
R
G
V
DD
A
TOP
-6.7A
-9.6A
BOTTOM -14A
I
AS
DRIVER
-20V
0.01
t
Ω
p
15V
Fig 12a.
Unclamped Inductive Test Circuit
I
AS
0
25
50
75
100
125
150
Starting T
, Junction Temperature (°C)
J
Fig 13.
Maximum Avalanche Energy
vs. Drain Current
t
p
V
(BR)DSS
Fig 12b.
Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.
T
.
50K
Ω
Q
G
.2
µ
F
12V
.3
µ
F
-10V
–
V
+
DS
Q
Q
GD
GS
D.U.
T
.
V
GS
V
G
-3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 14b.
Gate Charge Test Circuit
Fig 14a.
Basic Gate Charge Waveform
6
IRF9540NS/LPbF
Peak Diode Recovery dv/dt Test Circuit
+
–
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
D.U.T
*
+
–
–
+
R
G
•
dv/dt controlled by R
G
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
+
–
V
DD
V
GS
*
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P
.
W.
Period
Period
D =
P.W.
V
[
=10V
] ***
GS
D.U.
T
. I
W
aveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
[
DD
]
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
[
]
SD
Ripple
≤
5%
***
V
GS
= 5.0V for Logic Level and 3V Drive Devices
Fig 15.
For P-Channel HEXFETS
7
IRF9540NS/LPbF
D
2
Pak Package Outline
Dimensions are shown in millimeters (inches)
D
2
Pak Part Marking Information
T
H
IS IS
A
N
I
RF530S
W
I
T
H
L
O
T CODE 8024
A
S
SE
M
B
LED
O
N WW 02, 2000
IN THE
A
S
SE
M
B
LY LINE “L”
P
A
R
T NU
M
B
ER
IN
T
ER
N
A
T
I
O
NAL
RE
C
T
IFIER
L
O
GO
F530S
D
A
T
E
C
ODE
YE
A
R 0 =
2
000
W
E
EK 02
A
S
SE
M
B
LY
L
O
T CODE
LINE L
OR
P
A
R
T
N
U
M
B
ER
IN
T
ER
N
A
T
I
O
N
A
L
RE
C
T
I
FIER
L
O
GO
F
5
30S
DA
T
E
C
ODE
P =
DE S I
G
N
A
T E S
L E AD – F R E E
PR
O
D
U
C
T (OP
T
I
O
NA
L
)
Y
E
A
R 0 =
2
000
A
S
SE
M
B
LY
L
O
T CODE
W
E
EK
0
2
A=
A
S
SE
M
B
LY
SITE
C
ODE
8
IRF9540NS/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
E
X
A
M
P
LE: THIS
IS
A
N
I
RL3103L
L
O
T CODE 1789
P
A
R
T NU
M
B
ER
IN
T
ER
N
A
T
I
O
NAL
RE
C
T
I
FIER
L
O
GO
A
S
SE
M
B
LED
O
N WW 19, 1997
IN
T
H
E
A
S
SE
M
B
LY LI
N
E “C”
D
A
T
E
C
ODE
Y
E
A
R 7 =
1997
W
E
EK
1
9
Note: “P” in
a
s
s
e
mb
l
y li
n
e
pos
i
tion indi
c
ates
“L ead
–
F r
e
e”
A
S
SE
M
B
LY
L
O
T CODE
LINE C
OR
P
A
R
T NU
M
B
ER
DA
T
E
C
ODE
IN
T
ER
N
A
T
I
O
NAL
RE
C
T
I
F
IER
L
O
GO
P =
D
E
SI
G
NA
T
ES LE
A
D
–
F
REE
PR
O
D
U
C
T (OP
T
I
O
NA
L
)
Y
E
A
R 7 =
1997
A
S
SE
M
B
LY
L
O
T CODE
W
E
EK
1
9
A=
A
S
SE
M
B
LY
SITE
C
ODE
9
IRF9540NS/LPbF
D
2
Pak
T
a
pe & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
TRL
11.60 (.457)
11.40 (.449)
1.85 (.073)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS
TO EIA-418.
2. CONTROLLING
DIMENSION: MILLIMETER.
3. DIMENSION
MEASURED @ HUB.
4. INCLUDES
FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
10
Note: For
the most current drawings please refer to the IR website at:
