Infineon-Technologies-IRFB3006GPBF
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PD – 96238
IRFB3006GPbF
HEXFET
®
Power MOSFET
Applications
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
D
V
DSS
R
DS(on)
typ.
60V
2.1m
2.5m
max.
l
Hard Switched and High Frequency Circuits
G
I
D
I
D
270A
(Silicon Limited)
195A
S
(Package Limited)
Benefits
l
Improved Gate,
Avalanche and Dynamic
dV/dt
Ruggedness
D
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
l
Halogen-Free
S
D
G
TO-220AB
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
D
@ T
C
= 25°C
I
DM
Parameter
Max.
270
Units
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Wire Bond Limited)
Pulsed Drain Current
190
A
195
1080
375
P
D
@T
C
= 25°C
W
Maximum Power Dissipation
2.5
Linear Derating Factor
W/°C
V
V
GS
± 20
Gate-to-Source Voltage
10
Peak Diode Recovery
dv/dt
T
J
V/ns
-55 to
+ 175
Operating Junction and
T
STG
Storage Temperature Range
°C
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
10lb in (1.1N m)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy
E
AS (Thermally limited)
320
mJ
A
Avalanche Current
I
AR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy
E
AR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.4
Units
R
θ
JC
Junction-to-Case
R
θ
CS
R
θ
JA
0.50
–––
–––
62
°C/W
Case-to-Sink, Flat Greased Surface
Junction-to-Ambient
1
06/29/09
IRFB3006GPbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
Parameter
Min. Typ. Max.
Units
60 –––
–––
––– 0.07 ––– V/°C
Reference to 25°C, I
D
= 5mA
Conditions
V
GS
= 0V, I
D
= 250µA
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
V
∆
V
(BR)DSS
/
∆
T
J
R
DS(on)
–––
2.0
2.1
2.5
4.0
20
V
GS
= 10V, I
D
= 170A
V
DS
= V
GS
, I
D
= 250µA
m
Ω
V
V
GS(th)
–––
I
DSS
Drain-to-Source Leakage Current
––– –––
µA V
DS
= 60V, V
GS
= 0V
V
DS
= 60V, V
GS
= 0V, T
J
= 125°C
nA V
GS
= 20V
––– ––– 250
––– ––– 100
––– ––– -100
I
GSS
R
G
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
V
GS
= -20V
–––
2.0
–––
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max.
Units
Conditions
V
DS
= 25V, I
D
= 170A
280 ––– –––
S
Q
g
––– 200 300
nC I
D
= 170A
V
DS
=30V
Q
gs
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Total Gate Charge Sync. (Q
g
– Q
gd
)
Turn-On Delay Time
–––
–––
37
60
–––
Q
gd
V
GS
= 10V
Q
sync
––– 140 –––
––– 16 –––
I
D
= 170A, V
DS
=0V, V
GS
= 10V
ns V
DD
= 39V
I
D
= 170A
R =
2.7
t
d(on)
t
r
Rise Time
––– 182 –––
––– 118 –––
––– 189 –––
––– 8970 –––
––– 1020 –––
––– 534 –––
––– 1480 –––
––– 1920 –––
t
d(off)
Turn-Off Delay Time
Ω
G
t
f
Fall Time
V
GS
= 10V
pF V
GS
= 0V
V
DS
= 50V
C
iss
Input Capacitance
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
ƒ = 1.0 MHz,
See Fig. 5
C
oss
eff. (ER)
C
oss
eff. (TR)
V
GS
= 0V, V
DS
= 0V to 48V
, See Fig. 11
V
GS
= 0V, V
DS
= 0V to 48V
Diode Characteristics
Symbol
Parameter
Min. Typ. Max.
Units
Conditions
I
S
Continuous Source Current
––– –––
A
MOSFET symbol
270
D
(Body Diode)
Pulsed Source Current
showing the
integral reverse
G
I
SM
––– –––
1080
A
S
(Body Diode)
p-n junction diode.
V
SD
t
rr
Diode Forward Voltage
––– –––
1.3
–––
–––
–––
–––
–––
V
T
J
= 25°C, I
S
= 170A, V
GS
= 0V
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
V
R
= 51V,
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
–––
–––
–––
44
48
63
77
2.4
ns
I
F
= 170A
di/dt = 100A/µs
Q
rr
nC
A
I
RRM
t
on
Reverse Recovery Current
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 195A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements.
(Refer to AN-1140)
Repetitive rating;
pulse width limited by max. junction
temperature.
I
SD
≤
170A, di/dt
≤
1360A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
ꢀ
Pulse width
≤
400µs; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.022mH
R
G
= 25
Ω
, I
AS
= 170A, V
GS
=10V. Part not recommended for use
above this value .
R
θ
is measured at T
J
approximately 90°C.
2
IRFB3006GPbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
6.0V
5.0V
4.5V
4.0V
3.5V
VGS
15V
TOP
TOP
10V
8.0V
6.0V
5.0V
4.5V
4.0V
3.5V
BOTTOM
BOTTOM
3.5V
60µs PULSE WIDTH
3.5V
1
≤
60µs PULSE WIDTH
≤
Tj = 175°C
Tj = 25°C
1
0.1
1
10
100
0.1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
2.5
2.0
1.5
1.0
0.5
1000
100
10
I
= 170A
= 10V
D
V
GS
T
= 175°C
J
T
= 25°C
J
V
= 25V
DS
60µs PULSE WIDTH
≤
1
2.0
3.0
4.0
5.0
6.0
7.0
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
V
, Gate-to-Source Voltage (V)
GS
T
, Junction Temperature (°C)
J
Fig 4.
Normalized On-Resistance vs. Temperature
Fig 3.
Typical Transfer Characteristics
16000
12000
8000
4000
0
16
V
C
= 0V,
f = 1 MHZ
GS
I =
170A
D
= C
+ C
, C
SHORTED
iss
gs
gd ds
V
V
= 48V
= 30V
DS
DS
C
= C
rss
gd
C
= C
+ C
12
8
oss
ds
gd
C
iss
4
C
oss
C
rss
0
0
40
80
120 160 200 240 280
1
10
100
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFB3006GPbF
1000
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
100
10
1
100µsec
LIMITED BY PACKAGE
1msec
T
J
= 25°C
10msec
DC
1
Tc = 25°C
Tj = 175°C
V
= 0V
GS
Single Pulse
0.1
0.1
0.0
0.4
0.8
1.2
1.6
2.0
0.1
1
10
100
V
, Drain-toSource Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
80
75
70
65
60
55
300
I
= 5mA
LIMITED BY PACKAGE
D
250
200
150
100
50
0
25
50
75
100
125
150
175
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
T
, Case Temperature (°C)
C
T
, Junction Temperature (°C)
J
Fig 9.
Maximum Drain Current vs.
Fig 10.
Drain-to-Source Breakdown Voltage
Case Temperature
1400
2.0
1.5
1.0
0.5
0.0
I
D
1200
1000
800
600
400
200
0
TOP
20A
27A
170A
BOTTOM
0
10
V
20
30
40
50
60
25
50
75
100
125
150
175
Drain-to-Source Voltage (V)
Starting T
, Junction Temperature (°C)
DS,
J
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy Vs. DrainCurrent
4
IRFB3006GPbF
1
0.1
D = 0.50
0.20
0.10
0.05
R
1
R
1
R
2
R
2
τι
0.01
(sec)
Ri (°C/W)
0.02
0.01
τ
J
τ
C
τ
J
τ
1
0.175365 0.000343
0.22547 0.006073
τ
2
τ
2
τ
1
Ci=
τ
i
/
Ri
0.001
0.0001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆
Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Τ
j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
400
300
200
100
0
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆
T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche =
t
av
·f
TOP
BOTTOM 1%
Duty Cycle
= 170A
Single Pulse
I
D
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
25
50
75
100
125
150
175
I
av
= 2
D
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Starting T
, Junction Temperature (°C)
J
Fig 15.
Maximum Avalanche Energy vs. Temperature
5
IRFB3006GPbF
4.0
3.5
3.0
2.5
2.0
1.5
1.0
20
16
12
8
I
I
I
= 1.0A
D
D
D
= 1.0mA
= 250µA
I
= 112A
F
V
= 51V
R
4
T
= 125°C
= 25°C
J
J
T
0
100
200
300
400
500
600
700
800
-75 -50 -25
0
J
25 50 75
100 125 150 175
, Temperature ( °C )
di /
dt – (A / µs)
T
f
Fig. 17
– Typical Recovery Current vs. di
f
/dt
Fig 16.
Threshold Voltage Vs. Temperature
20
700
600
500
400
300
16
12
8
I
= 170A
= 51V
I
= 112A
= 51V
200
100
0
F
F
V
V
T
R
4
0
R
T
= 125°C
= 25°C
= 125°C
= 25°C
J
J
T
T
J
J
100
200
300
400
500
600
700
800
100
200
300
400
500
600
700
800
di /
dt – (A / µs)
di /
dt – (A / µs)
f
f
Fig. 18
– Typical Recovery Current vs. di
f
/dt
Fig. 19
– Typical Stored Charge vs. di
f
/dt
700
600
500
400
300
200
100
0
I
= 170A
= 51V
F
V
T
R
= 125°C
= 25°C
J
T
J
100
200
300
400
500
600
700
800
di /
dt – (A / µs)
f
Fig. 20
– Typical Stored Charge vs. di
f
/dt
6
IRFB3006GPbF
Driver Gate Drive
P.W.
P
.
W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Current
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 21.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
V
2
GS
Ω
0.01
t
p
I
AS
Fig 22b.
Unclamped Inductive Waveforms
Fig 22a.
Unclamped Inductive Test Circuit
R
D
V
DS
V
DS
90%
V
GS
D.U.T.
R
G
+
V
DD
–
V
GS
10%
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a.
Switching Time Test Circuit
Fig 23b.
Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.
T
.
Vds
Vgs
50K
Ω
.2
µ
F
12V
.3
µ
F
+
V
DS
D.U.
T
.
–
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a.
Gate Charge Test Circuit
Fig 24b.
Gate Charge Waveform
7
IRFB3006GPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
TO-220AB packages are not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
8
