Infineon-Technologies-IRFB3206GPBF
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PD – 96210
IRFB3206GPbF
HEXFET
®
Power MOSFET
Applications
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
D
S
V
DSS
R
DS(on)
typ.
max.
60V
2.4m
3.0m
210A
l
Hard Switched and High Frequency Circuits
G
I
D
(Silicon Limited)
I
D
(Package Limited)
120A
Benefits
l
Improved Gate,
Avalanche and Dynamic
dV/dt
Ruggedness
D
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
S
D
G
l
Halogen-Free
TO-220AB
IRFB3206GPbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
Parameter
Max.
210
Units
A
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Wire Bond Limited)
Pulsed Drain Current
I
D
@ T
C
= 100°C
I
D
@ T
C
= 25°C
I
DM
150
120
840
P
D
@T
C
= 25°C
300
W
Maximum Power Dissipation
2.0
Linear Derating Factor
W/°C
V
V
GS
± 20
Gate-to-Source Voltage
5.0
Peak Diode Recovery
dv/dt
T
J
V/ns
-55 to
+ 175
Operating Junction and
T
STG
Storage Temperature Range
°C
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
10lbf in (1.1N m)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy
E
AS (Thermally limited)
170
mJ
A
Avalanche Current
I
AR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy
E
AR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.50
–––
62
Units
R
θ
JC
Junction-to-Case
R
θ
CS
R
θ
JA
0.50
–––
Case-to-Sink, Flat Greased Surface , TO-220
Junction-to-Ambient, TO-220
°C/W
1
1/06/09
IRFB3206GPbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
Parameter
Min. Typ. Max.
Units
60 –––
–––
––– 0.07 ––– V/°C
Reference to 25°C, I
D
= 5mA
Conditions
V
GS
= 0V, I
D
= 250µA
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
V
∆
V
(BR)DSS
/
∆
T
J
R
DS(on)
–––
2.0
2.4
3.0
4.0
20
V
GS
= 10V, I
D
= 75A
m
Ω
V
V
GS(th)
–––
V
DS
= V
GS
, I
D
= 150µA
I
DSS
Drain-to-Source Leakage Current
––– –––
µA V
DS
=60V, V
GS
= 0V
V
DS
= 48V, V
GS
= 0V, T
J
= 125°C
nA V
GS
= 20V
––– ––– 250
––– ––– 100
––– ––– -100
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
V
GS
= -20V
R
G
–––
0.7
–––
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max.
Units
Conditions
V
DS
= 50V, I
D
= 75A
nC I
D
= 75A
DS
=30V
V
GS
= 10V
I
D
= 75A, V
DS
=0V, V
GS
= 10V
ns V
DD
= 30V
I
D
= 75A
R =2.7
210 ––– –––
S
Q
g
––– 120 170
Q
gs
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Total Gate Charge Sync. (Q
g
– Q
gd
)
Turn-On Delay Time
–––
–––
–––
–––
–––
–––
–––
29
35
85
19
82
55
83
–––
V
Q
gd
Q
sync
–––
–––
–––
–––
–––
t
d(on)
t
r
Rise Time
t
d(off)
Turn-Off Delay Time
Ω
G
t
f
Fall Time
V
GS
= 10V
pF V
GS
= 0V
V
DS
= 50V
C
iss
Input Capacitance
––– 6540 –––
––– 720 –––
––– 360 –––
––– 1040 –––
––– 1230 –––
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
ƒ = 1.0MHz,
See Fig.5
C
oss
eff. (ER)
C
oss
eff. (TR)
V
GS
= 0V, V
DS
= 0V to 48V
, See
Fig.11
V
GS
= 0V, V
DS
= 0V to 48V
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
Diode Characteristics
Symbol
Parameter
Min. Typ. Max.
Units
Conditions
I
S
D
S
Continuous Source Current
––– –––
A
MOSFET symbol
210
(Body Diode)
Pulsed Source Current
showing the
integral reverse
G
I
SM
––– ––– 840
A
(Body Diode)
p-n junction diode.
V
SD
t
rr
Diode Forward Voltage
––– –––
1.3
50
V
T
J
= 25°C, I
S
= 75A, V
GS
= 0V
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
V
R
= 51V,
I
F
= 75A
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
–––
–––
–––
33
37
41
53
2.1
ns
56
di/dt = 100A/µs
Q
rr
62
nC
A
80
I
RRM
t
on
Reverse Recovery Current
Forward Turn-On Time
–––
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
I
SD
≤
75A, di/dt
≤
360A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
ꢀ
Pulse width
≤
400µs; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 120A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements.
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
Repetitive rating;
pulse width limited by max. junction
temperature.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.023mH
R
G
= 25
Ω
, I
AS
= 120A, V
GS
=10V. Part not recommended for use
R
θ
is measured at T
J
approximately 90°C
above this value.
2
IRFB3206GPbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
4.5V
60µs PULSE WIDTH
≤
60µs PULSE WIDTH
Tj = 25°C
≤
Tj = 175°C
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
100
10
2.5
2.0
1.5
1.0
0.5
I
= 75A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
J
1
V
= 25V
DS
≤
60µs PULSE WIDTH
0.1
2.0
3.0
V
4.0
5.0
6.0
7.0
8.0
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
, Gate-to-Source Voltage (V)
GS
T
, Junction Temperature (°C)
J
Fig 4.
Normalized On-Resistance vs. Temperature
Fig 3.
Typical Transfer Characteristics
20
12000
10000
8000
6000
4000
2000
0
V
C
= 0V,
f = 1 MHZ
I =
75A
D
GS
= C
+ C
, C
SHORTED
iss
gs
gd ds
V
= 48V
DS
C
= C
rss
gd
16
12
8
VDS= 30V
VDS= 12V
C
= C
+ C
ds
oss
gd
Ciss
4
Coss
Crss
0
0
40
80
120
160
200
1
10
100
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFB3206GPbF
1000
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
100
10
1
1msec
100µsec
T
= 25°C
J
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
DC
V
= 0V
GS
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
, Source-to-Drain Voltage (V)
0.1
0.1
0.1
1
10
100
V
, Drain-toSource Voltage (V)
V
DS
SD
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
240
200
160
120
80
80
75
70
65
60
55
I
= 5mA
D
Limited By Package
40
0
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
25
50
75
100
125
150
175
T
, Junction Temperature (°C)
T
, Case Temperature (°C)
J
C
Fig 9.
Maximum Drain Current vs.
Fig 10.
Drain-to-Source Breakdown Voltage
Case Temperature
2.0
1.5
1.0
0.5
0.0
800
600
400
200
0
I
D
TOP
21A
33A
BOTTOM
120A
0
10
V
20
30
40
50
60
25
50
75
100
125
150
175
Drain-to-Source Voltage (V)
Starting T
, Junction Temperature (°C)
DS,
J
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy Vs. DrainCurrent
4
IRFB3206GPbF
1
0.1
D = 0.50
0.20
0.10
0.05
R
1
R
1
R
2
R
2
R
3
R
3
τι
(sec)
Ri (°C/W)
0.02
0.01
τ
0.01
J
τ
J
τ
τ
C
τ
0.106416 0.0001
0.201878 0.001262
0.190923 0.011922
τ
1
τ
1
τ
2
τ
2
3
τ
3
Ci=
τ
i
/
Ri
Ci=
τ
i
/
Ri
SINGLE PULSE
( THERMAL RESPONSE )
0.001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆
Tj = 150°C and
Tstart =25°C (Single Pulse)
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Τ
j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
200
160
120
80
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
TOP
BOTTOM 1%
Duty Cycle
= 120A
Single Pulse
I
D
6. I
av
= Allowable avalanche current.
7.
∆
T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
40
t
av =
Average time in avalanche.
D = Duty cycle in avalanche =
t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
0
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
25
50
75
100
125
150
175
I
av
= 2
D
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Starting T
, Junction Temperature (°C)
J
Fig 15.
Maximum Avalanche Energy vs. Temperature
5
IRFB3206GPbF
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
18
16
14
12
10
8
I
I
I
= 1.0A
D
D
D
= 1.0mA
= 250µA
ID = 150µA
6
I
= 30A
F
4
V
= 51V
R
T
= 125°C
= 25°C
J
J
2
T
0
-75 -50 -25
0
J
25 50 75
100 125 150 175
, Temperature ( °C )
100 200 300 400 500 600 700 800 900
1000
T
di /
dt – (A / µs)
f
Fig. 17
– Typical Recovery Current vs. di
f
/dt
Fig 16.
Threshold Voltage Vs. Temperature
350
300
250
200
150
18
16
14
12
10
8
6
I
= 30A
= 51V
I
= 45A
= 51V
100
50
0
F
F
4
2
0
V
V
R
R
T
= 125°C
= 25°C
T
= 125°C
= 25°C
J
J
T
T
J
J
100 200 300 400 500 600 700 800 900
1000
100 200 300 400 500 600 700 800 900
1000
di /
dt – (A / µs)
f
di /
dt – (A / µs)
f
Fig. 18
– Typical Recovery Current vs. di
f
/dt
Fig. 19
– Typical Stored Charge vs. di
f
/dt
350
300
250
200
150
100
50
I
= 45A
F
V
= 51V
R
T
= 125°C
= 25°C
J
J
T
0
100 200 300 400 500 600 700 800 900
1000
di /
dt – (A / µs)
f
Fig. 20
– Typical Stored Charge vs. di
f
/dt
6
IRFB3206GPbF
Driver Gate Drive
P.W.
P
.
W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Current
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 21.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
V
2
GS
Ω
0.01
t
p
I
AS
Fig 22b.
Unclamped Inductive Waveforms
Fig 22a.
Unclamped Inductive Test Circuit
L
D
V
DS
V
DS
90%
+
–
V
DD
10%
V
GS
D.U.T
V
GS
Pulse Width < 1µs
Duty Factor < 0.1%
t
d(on)
t
d(off)
t
r
t
f
Fig 23a.
Switching Time Test Circuit
Fig 23b.
Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.
T
.
Vds
Vgs
50K
Ω
.2
µ
F
12V
.3
µ
F
+
V
DS
D.U.
T
.
–
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a.
Gate Charge Test Circuit
Fig 24b.
Gate Charge Waveform
7
IRFB3206GPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
TO-220AB packages are not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
8
