Infineon-Technologies-IRFB3207ZGPBF
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PD – 96201
IRFB3207ZGPbF
Applications
l
High Efficiency Synchronous Rectification in
HEXFET
®
Power MOSFET
SMPS
D
V
DSS
R
DS(on)
typ.
max.
I
D (Silicon Limited)
I
D (Package Limited)
75V
3.3m
4.1m
170A
120A
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
G
S
Benefits
D
l
Improved Gate,
Avalanche and Dynamic
dv/dt Ruggedness
l
Fully Characterized Capacitance and
Avalanche SOA
l
Enhanced body diode dV/dt and dI/dt
Capability
l
Lead-Free
l
Halogen-Free
S
D
G
TO-220AB
IRFB3207ZGPbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
Parameter
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Max.
170
Units
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
120
A
I
D
@ T
C
= 25°C
I
DM
Continuous Drain Current, V
GS
@ 10V (Wire Bond Limited)
Pulsed Drain Current
120
670
P
D
@T
C
= 25°C
W
300
Maximum Power Dissipation
Linear Derating Factor
2.0
W/°C
V
V
GS
± 20
Gate-to-Source Voltage
16
Peak Diode Recovery
dv/dt
T
J
V/ns
-55 to
+ 175
Operating Junction and
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
°C
300
10lbf in (1.1N m)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy
E
AS (Thermally limited)
170
mJ
A
Avalanche Current
I
AR
See Fig. 14, 15, 22a, 22b
Repetitive Avalanche Energy
E
AR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.50
–––
62
Units
R
θ
JC
Junction-to-Case
R
θ
CS
R
θ
JA
0.50
–––
°C/W
Case-to-Sink, Flat Greased Surface , TO-220
Junction-to-Ambient, TO-220
1
12/05/08
IRFB3207ZGPbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Min. Typ. Max.
Units
75 –––
–––
––– 0.091 –––
V/°C Reference
to 25°C, I
D
= 5mA
Conditions
V
GS
= 0V, I
D
= 250µA
V
∆
V
(BR)DSS
/
∆
T
J
R
DS(on)
–––
2.0
–––
3.3
–––
0.8
4.1
4.0
V
GS
= 10V, I
D
= 75A
m
Ω
V
V
GS(th)
V
DS
= V
GS
, I
D
= 150µA
R
G(int)
I
DSS
Internal Gate Resistance
Drain-to-Source Leakage Current
–––
20
Ω
––– –––
µA V
DS
= 75V, V
GS
= 0V
––– ––– 250
––– ––– 100
––– –––
-100
V
V
V
DS
= 75V, V
GS
= 0V, T
J
= 125°C
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
nA
GS
= 20V
GS
= -20V
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Min. Typ. Max.
Units
Conditions
V
DS
= 50V, I
D
= 75A
280 ––– –––
S
Q
g
Total Gate Charge
––– 120 170
I
D
= 75A
Q
gs
Q
gd
Q
sync
t
d(on)
t
r
Gate-to-Source Charge
–––
–––
–––
–––
–––
–––
–––
27
33
87
20
68
55
68
–––
–––
–––
–––
–––
–––
–––
V
DS
= 38V
nC
Gate-to-Drain (“Miller”) Charge
Total Gate Charge Sync. (Q
g
– Q
gd
)
V
GS
= 10V
I
D
= 75A, V
DS
=0V, V
GS
= 10V
V
DD
= 49V
Turn-On Delay Time
Rise Time
I
D
= 75A
ns
t
d(off)
t
f
Turn-Off Delay Time
R
G
= 2.7
Ω
V
GS
= 10V
Fall Time
C
iss
C
oss
C
rss
Input Capacitance
––– 6920 –––
––– 600 –––
––– 270 –––
––– 770 –––
––– 960 –––
V
GS
= 0V
Output Capacitance
V
DS
= 50V
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
ƒ = 1.0MHz
pF
C
oss
eff. (ER)
oss
eff. (TR)
V
GS
= 0V, V
DS
= 0V to 60V
GS
= 0V, V
DS
= 0V to 60V
C
V
Diode Characteristics
Symbol
Parameter
Continuous Source Current
Min. Typ. Max.
Units
Conditions
MOSFET symbol
D
S
I
S
––– –––
170
(Body Diode)
showing the
A
670
G
I
SM
Pulsed Source Current
(Body Diode)
integral reverse
––– –––
p-n junction diode.
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
––– –––
1.3
54
V
T
J
= 25°C, I
S
= 75A, V
GS
= 0V
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
V
R
= 64V,
–––
–––
–––
–––
–––
36
41
50
67
2.4
ns
I
F
= 75A
di/dt = 100A/µs
62
Q
rr
Reverse Recovery Charge
75
nC
100
–––
I
RRM
t
on
Reverse Recovery Current
Forward Turn-On Time
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 120A. Note that current
limitations arising from heating of the device leads may occur with
I
SD
≤
75A, di/dt
≤
1730A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
ꢀ
Pulse width
≤
400µs; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
some lead mounting arrangements.
Repetitive rating;
pulse width limited by max. junction
temperature.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.033mH
R
θ
is measured at T
J
approximately 90°C.
R
G
= 25
Ω
, I
AS
= 102A, V
GS
=10V. Part not recommended for use
above this value.
2
IRFB3207ZGPbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
4.5V
60µs PULSE WIDTH
≤
Tj = 175°C
60µs PULSE WIDTH
≤
Tj = 25°C
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
2.5
2.0
1.5
1.0
0.5
1000
100
10
I
= 75A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
J
1
V
= 25V
DS
≤
60µs PULSE WIDTH
0.1
2
3
4
5
6
7
-60 -40 -20
0 20
40 60 80
100120140160180
, Junction Temperature (°C)
T
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4.
Normalized On-Resistance vs. Temperature
Fig 3.
Typical Transfer Characteristics
12.0
100000
10000
1000
V
= 0V,
= C
f = 1 MHZ
GS
I
= 75A
D
C
C
C
+ C
, C
SHORTED
iss
gs
gd
ds
= C
10.0
8.0
6.0
4.0
2.0
0.0
rss
oss
gd
V
V
V
= 60V
= 38V
= 15V
DS
DS
DS
= C
+ C
ds
gd
C
iss
C
oss
C
rss
100
0
20
40
60
80
100 120 140
1
10
, Drain-to-Source Voltage (V)
100
Q ,
Total Gate Charge (nC)
V
G
DS
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFB3207ZGPbF
1000
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
100
10
1
100µsec
T
= 25°C
J
1msec
10msec
DC
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
0.1
0.1
0.0
0.5
1.0
1.5
2.0
2.5
1
10
, Drain-to-Source Voltage (V)
100
V
, Source-to-Drain Voltage (V)
V
DS
SD
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode Forward Voltage
180
100
95
90
85
80
75
70
Id = 5mA
Limited By Package
160
140
120
100
80
60
40
20
0
25
50
75
100
125
150
175
-60 -40 -20
0 20
40 60 80
100120140160180
T
, Case Temperature (°C)
T ,
Temperature ( °C )
J
C
Fig 10.
Drain-to-Source Breakdown Voltage
Fig 9.
Maximum Drain Current vs. Case Temperature
2.5
700
I
D
600
500
400
300
200
100
0
TOP
17A
30A
2.0
1.5
1.0
0.5
0.0
BOTTOM 102A
-10
0
10 20 30 40 50 60 70 80
Drain-to-Source Voltage (V)
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
J
V
DS,
Fig 12.
Maximum Avalanche Energy vs. DrainCurrent
Fig 11.
Typical C
OSS
Stored Energy
4
IRFB3207ZGPbF
1
D = 0.50
0.1
0.20
0.10
0.05
R
1
R
1
R
2
R
2
R
3
R
3
Ri (°C/W)
τ
i (sec)
τ
J
τ
J
τ
C
τ
0.1049 0.000099
0.2469 0.001345
0.1484 0.008469
τ
τ
1
τ
1
τ
2
τ
2
3
τ
3
0.02
0.01
0.01
0.001
Ci=
τ
i
/
Ri
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle =
Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
Tj = 150°C and
∆
0.01
Tstart =25°C (Single Pulse)
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
Tstart = 150°C.
j = 25°C and
∆Τ
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
200
180
160
140
120
100
80
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
TOP
BOTTOM 1.0%
Duty Cycle
= 102A
Single Pulse
I
D
6. I
av
= Allowable avalanche current.
7.
∆
T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
60
t
av =
Average time in avalanche.
D = Duty cycle in avalanche =
t
av
·f
40
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
20
0
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
25
50
75
100
125
150
175
I
av
= 2
D
T/ [1.3·BV·Z
th
]
Starting T
, Junction Temperature (°C)
E
AS (AR)
= P
D (ave)
·t
av
J
Fig 15.
Maximum Avalanche Energy vs. Temperature
5
IRFB3207ZGPbF
20
15
10
5
4.5
4.0
3.5
3.0
2.5
I =
30A
F
V
= 64V
R
T =
25°C
J
T =
125°C
J
I
I
I
I
= 150µA
= 250µA
= 1.0mA
= 1.0A
2.0
1.5
1.0
0.5
D
D
D
D
0
0
200
400
600
800
1000
-75 -50 -25
0
25 50 75
100 125 15
0
1
75 200
di /dt
(A/µs)
T ,
Temperature ( °C )
F
J
Fig. 17
– Typical Recovery Current vs. di
f
/dt
Fig 16.
Threshold Voltage vs. Temperature
20
340
I =
45A
I =
30A
F
F
V
= 64V
V
= 64V
R
R
T =
25°C
T =
25°C
J
J
15
10
5
260
180
100
20
T =
125°C
J
T =
125°C
J
0
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt
(A/µs)
di /dt
(A/µs)
F
F
Fig. 18
– Typical Recovery Current vs. di
f
/dt
Fig. 19
– Typical Stored Charge vs. di
f
/dt
340
I =
45A
F
V
= 64V
R
T =
25°C
J
260
180
100
20
T =
125°C
J
0
200
400
600
800
1000
di /dt
(A/µs)
F
Fig. 20
– Typical Stored Charge vs. di
f
/dt
6
IRFB3207ZGPbF
Driver Gate Drive
P.W.
P
.
W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Current
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 20.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
V
2
GS
Ω
0.01
t
p
I
AS
Fig 21b.
Unclamped Inductive Waveforms
Fig 21a.
Unclamped Inductive Test Circuit
L
D
V
DS
V
DS
90%
+
–
V
DD
10%
V
GS
D.U.T
V
GS
Pulse Width < 1µs
Duty Factor < 0.1%
t
d(on)
t
d(off)
t
r
t
f
Fig 22a.
Switching Time Test Circuit
Fig 22b.
Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
Vgs(th)
0
1K
Qgs1
Qgs2
Qgd
Qgodr
Fig 23a.
Gate Charge Test Circuit
Fig 23b.
Gate Charge Waveform
7
IRFB3207ZGPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
TO-220AB packages are not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
8
