Infineon-Technologies-IRFB42N20DPBF
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PD- 95470
SMPS MOSFET
IRFB42N20DPbF
HEXFET
®
Power MOSFET
Applications
l
High frequency DC-DC converters
l
Motor Control
V
DSS
200V
R
DS(on)
max
I
D
44A
0.055
Ω
l
Uninterrutible Power Supplies
l
Lead-Free
Benefits
l
Low Gate-to-Drain Charge to Reduce
Switching Losses
l
Fully Characterized Capacitance Including
Effective C
OSS
to Simplify Design, (See
App. Note AN1001)
l
Fully Characterized Avalanche Voltage
and Current
TO-220AB
Absolute Maximum Ratings
Parameter
Max.
44
31
Units
A
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
180
P
D
@T
A
= 25°C
P
D
@T
C
= 25°C
Power Dissipation
2.4
W
Power Dissipation
330
Linear Derating Factor
2.2
W/°C
V
V
GS
dv/dt
T
J
Gate-to-Source Voltage
± 30
Peak Diode Recovery dv/dt
Operating Junction and
2.5
V/ns
-55 to
+ 175
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torqe, 6-32 or
M3 screw
°C
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
Typ.
Max.
0.45
–––
62
Units
R
θ
JC
R
θ
CS
R
θ
JA
–––
0.50
–––
°C/W
Notes
through
ꢀ
are on
page 8
1
7/7/04
IRFB42N20DPbF
Static @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
200 –––
–––
––– 0.26
––– V/°C
Reference to 25°C, I
D
= 1mA
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
V
V
GS
= 0V, I
D
= 250µA
∆
V
(BR)DSS
/
∆
T
J
Breakdown Voltage Temp. Coefficient
R
DS(on)
V
GS(th)
Static Drain-to-Source On-Resistance
––– –––
0.055
Ω
V
V
GS
= 10V, I
D
= 26A
Gate Threshold Voltage
3.0
––– 5.5
V
DS
= V
GS
, I
D
= 250µA
––– ––– 25
––– –––
250
––– –––
100
––– –––
-100
V
DS
= 200V, V
GS
= 0V
I
DSS
Drain-to-Source Leakage Current
µA
V
DS
= 160V, V
GS
= 0V, T
J
= 150°C
V
GS
= 30V
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
I
GSS
nA
V
GS
= -30V
Dynamic @ T
J
= 25°C (unless otherwise specified)
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
g
fs
21
––– –––
S
V
DS
= 50V, I
D
= 26A
I
D
= 26A
Q
g
–––
–––
–––
–––
–––
–––
–––
91
24
43
140
36
Q
gs
Q
gd
t
d(on)
t
r
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Turn-On Delay Time
Rise Time
nC V
DS
= 160V
V
GS
= 10V,
65
18 –––
69 –––
29 –––
32 –––
V
DD
= 100V
I
D
= 26A
ns
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
R
G
= 1.8
Ω
V
GS
= 10V
V
GS
= 0V
C
iss
C
oss
C
rss
C
oss
C
oss
C
oss
eff.
Input Capacitance
––– 3430
–––
––– 530
–––
––– 100
–––
––– 5310
–––
––– 210
–––
––– 400
–––
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
V
DS
= 25V
pF
ƒ = 1.0MHz
V
GS
= 0V,
V
DS
= 1.0V,
ƒ = 1.0MHz
V
GS
= 0V,
V
DS
= 160V,
ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 160V
ꢀ
Avalanche Characteristics
Parameter
Single Pulse Avalanche Energy
Typ.
–––
–––
–––
Max.
510
26
Units
mJ
E
AS
I
AR
Avalanche Current
A
E
AR
Repetitive Avalanche Energy
33
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
D
S
I
S
Continuous Source Current
(Body Diode)
MOSFET symbol
44
––– –––
––– –––
showing the
A
G
I
SM
Pulsed Source Current
(Body Diode)
integral reverse
p-n junction diode.
180
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 1.3
––– 220 330
V
T
J
= 25°C, I
S
= 26A, V
GS
= 0V
ns
T
J
= 25°C, I
F
= 26A
Q
rr
t
on
––– 1860
2790 nC di/dt
= 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
2
IRFB42N20DPbF
1000
100
10
1000
100
10
VGS
15V
VGS
TOP
TOP
15V
10V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
8.0V
7.0V
6.5V
6.0V
5.5V
BOTTO
M
5
.0V
BOTTO
M
5
.0V
1
5.0V
0.1
5.0V
20µs PULSE WIDTH
°
20µs PULSE WIDTH
°
T =
175 C
J
T =
25 C
J
1
0.1
0.01
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
3.5
1000
44A
=
I
D
3.0
2.5
2.0
1.5
1.0
0.5
0.0
100
10
1
°
T =
175 C
J
°
T =
25 C
J
V
= 50V
DS
20µs PULSE WIDTH
V
=
1
0V
GS
0.1
5
6
7
8
9
10
11
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
°
V
, Gate-to-Source Voltage (V)
T ,
Junction Temperature (
C)
J
GS
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
3
IRFB42N20DPbF
20
16
12
8
100000
I
D
= 26A
V
C
= 0V,
f = 1 MHZ
GS
V
V
V
= 160V
= 100V
= 40V
= C
+ C
,
C
ds
SHORTED
DS
DS
DS
iss
gs
gd
C
= C
rss
gd
C
= C
+ C
oss
ds
gd
10000
1000
100
Ciss
Coss
Crss
4
FOR TEST CIRCUIT
SEE FIGURE 13
10
0
1
10
100
1000
0
20
40
60
80
100 120
140
Q ,
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 6.
Typical Gate Charge Vs.
Fig 5.
Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000
1000
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
100
10
1
100
10
1
°
T =
175 C
J
100µsec
1msec
°
T =
25 C
J
Tc = 25°C
10msec
Tj = 175°C
Single Pulse
V
= 0 V
GS
1.2
0.1
0.1
0.2
0.4
V
0.6
0.8
1.0
1.4
1
10
100
1000
,Source-to-Drain Voltage (V)
SD
V
, Drain-toSource Voltage (V)
DS
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
4
IRFB42N20DPbF
R
D
50
40
30
20
10
0
V
DS
V
GS
D.U.T.
R
G
+
V
DD
–
10V
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
Fig 10a.
Switching Time Test Circuit
V
DS
90%
25
50
75
100
125
150
175
°
T ,
Case Temperature
( C)
C
10%
V
GS
t
t
r
t
t
f
Fig 9.
Maximum Drain Current Vs.
d(on)
d(off)
Case Temperature
Fig 10b.
Switching Time Waveforms
1
D = 0.50
0.20
0.1
0.01
0.10
0.05
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
P
2
DM
t
1
t
2
Notes:
1. Duty factor D =
t /
t
1
2. Peak T
=
P
x Z
+ T
thJC C
J
DM
0.001
0.00001
0.0001
0.001
0.01
0.1
t ,
Rectangular Pulse Duration (sec)
1
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
IRFB42N20DPbF
1000
800
600
400
200
0
I
15V
D
TOP
11A
19A
BOTTOM 26A
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
2
V
0
G
V
S
Ω
0.01
t
p
Fig 12a.
Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
175
°
Starting T
, Junction Temperature
( C)
J
Fig 12c.
Maximum Avalanche Energy
Vs. Drain Current
I
AS
Fig 12b.
Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.
T
.
Q
G
50K
Ω
.2
µ
F
12V
10 V
.3
µ
F
Q
Q
GD
GS
+
V
DS
D.U.
T
.
–
V
GS
V
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 13a.
Basic Gate Charge Waveform
Fig 13b.
Gate Charge Test Circuit
6
IRFB42N20DPbF
Peak Diode Recovery dv/dt Test Circuit
+
–
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
D.U.T
+
–
–
+
R
G
•
dv/dt controlled by R
G
+
–
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
V
DD
Driver Gate Drive
P.W.
P
.
W.
Period
Period
D =
V
=10V
*
GS
D.U.
T
. I
W
aveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 14.
For N-Channel HEXFET
®
Power MOSFETs
7
IRFB42N20DPbF
TO-220AB Package Outline
10.54 (.415)
10.29 (.405)
– B –
3.78 (.149)
3.54 (.139)
2.87 (.113)
2.62 (.103)
4.69 (.185)
4.20 (.165)
1.32 (.052)
1.22 (.048)
– A –
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
LEAD ASSIGNMENTS
1.15 (.045)
MIN
HEXFET
IGBTs, CoPACK
2- DRAIN
3- SOURCE
1
2
3
1- GATE
1- GATE
2- COLLECTOR
3- EMITTER
4- COLLECTOR
4- DRAIN
14.09 (.555)
13.47 (.530)
4.06 (.160)
3.55 (.140)
0.93 (.037)
0.69 (.027)
0.55 (.022)
0.46 (.018)
3X
3X
1.40 (.055)
3X
1.15 (.045)
0.36 (.014)
M
B A M
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1
2
DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
CONTROLLING DIMENSION : INCH
3
4
OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
E XAM
P
LE:
T H
I
S
IS AN I
R
F1
0
10
LOT
C
O
D
E 1789
P
A
R
T NU
M
B
ER
A
S
S E
M
B
LE D
O
N WW 19, 1997
IN T HE
A
S
S
E
M
B
LY LINE
“
C”
INT E RN
A
T
I
ON
A
L
RE
C
T
IFIER
L
O
GO
Note:
“P” in assembly line
position indicates “Lead-Free”
DAT E
CODE
YE
A
R 7 =
1
997
W
E
E K
19
A
S
SE
M
B
LY
L
O
T CODE
L
I
NE C
Notes:
Repetitive rating;
pulse width limited by
I
SD
≤
26A, di/dt
≤
110A/µs, V
DD
≤
V
(BR)DSS
T
J
≤
175°C
Pulse width
≤
400µs; duty cycle
≤
2%.
,
max. junction temperature.
Starting T
J
= 25°C, L = 1.45mH
R
G
= 25
Ω
, I
AS
= 26A, V
GS
=10V
ꢀ
C
oss
eff. is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
8
Note: For
the most current drawings please refer to the IR website at:
