Infineon-Technologies-IRFB4410PBF
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PD – 96902C
IRFB4410
IRFS4410
IRFSL4410
HEXFET
®
Power MOSFET
Applications
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
D
S
V
DSS
R
DS(on)
typ.
max.
100V
8.0m
10m
96A
G
Benefits
I
D
l
Improved Gate,
Avalanche and Dynamic
dV/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
D
S
S
S
D
G
D
G
G
D
2
Pak
IRFS4410
TO-262
IRFSL4410
TO-220AB
IRFB4410
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
Parameter
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Max.
96
Units
A
68
380
250
1.6
P
D
@T
C
= 25°C
W
Maximum Power Dissipation
Linear Derating Factor
W/°C
V
V
GS
± 20
19
Gate-to-Source Voltage
Peak Diode Recovery
dv/dt
T
J
V/ns
°C
-55 to
+ 175
Operating Junction and
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
300
10lb in (1.1N m)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy
E
AS (Thermally limited)
220
mJ
A
Avalanche Current
I
AR
See Fig. 14, 15, 16a, 16b
Repetitive Avalanche Energy
E
AR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.61
–––
62
Units
R
θ
JC
Junction-to-Case
R
θ
CS
R
θ
JA
R
θ
JA
0.50
–––
°C/W
Case-to-Sink, Flat Greased Surface , TO-220
Junction-to-Ambient, TO-220
Junction-to-Ambient (PCB Mount) , D
2
Pak
–––
40
1
05/02/07
IRFB4410/IRFS4410/IRFSL4410
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
Parameter
Min. Typ. Max.
Units
100 ––– –––
––– 0.094 –––
V/°C Reference
to 25°C, I
D
= 1mA
Conditions
V
GS
= 0V, I
D
= 250µA
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
V
∆
V
(BR)DSS
/
∆
T
J
R
DS(on)
–––
2.0
8.0
10
4.0
20
V
GS
= 10V, I
D
= 58A
m
Ω
V
V
GS(th)
–––
V
DS
= V
GS
, I
D
= 150µA
I
DSS
Drain-to-Source Leakage Current
––– –––
µA
V
DS
= 100V, V
GS
= 0V
––– ––– 250
––– ––– 200
––– –––
-200
V
DS
= 100V, V
GS
= 0V, T
J
= 125°C
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Input Resistance
nA V
GS
= 20V
GS
= -20V
f = 1MHz, open drain
V
R
G
–––
1.5
–––
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Q
g
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max.
Units
Conditions
V
DS
= 50V, I
D
= 58A
nC I
D
= 58A
DS
= 80V
V
GS
= 10V
DD
= 65V
120 ––– –––
S
––– 120 180
Q
gs
Q
gd
t
d(on)
t
r
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Turn-On Delay Time
Rise Time
–––
–––
–––
–––
–––
–––
31
44
24
80
55
50
–––
–––
–––
–––
–––
–––
V
ns
V
I
D
= 58A
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
R
G
= 4.1
Ω
V
GS
= 10V
C
iss
C
oss
C
rss
Input Capacitance
––– 5150 –––
––– 360 –––
––– 190 –––
––– 420 –––
––– 500 –––
pF
V
GS
= 0V
Output Capacitance
Reverse Transfer Capacitance
V
DS
= 50V
ƒ = 1.0MHz
C
oss
eff. (ER)
V
GS
= 0V, V
DS
= 0V to 80V
, See Fig.11
GS
= 0V, V
DS
= 0V to 80V
, See Fig. 5
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
C
oss
eff. (TR)
V
Diode Characteristics
Symbol
Parameter
Min. Typ. Max.
Units
Conditions
MOSFET symbol
I
S
D
S
Continuous Source Current
––– –––
A
96
(Body Diode)
Pulsed Source Current
(Body Diode)
showing the
integral reverse
G
I
SM
––– ––– 380
A
p-n junction diode.
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
––– –––
1.3
56
77
92
V
T
J
= 25°C, I
S
= 58A, V
GS
= 0V
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
V
R
= 85V,
–––
–––
–––
38
51
61
ns
I
F
= 58A
di/dt = 100A/µs
Q
rr
Reverse Recovery Charge
nC
––– 110 170
––– 2.8 –––
I
RRM
t
on
Reverse Recovery Current
Forward Turn-On Time
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
temperature. Package limitation current is 75A.
Repetitive rating;
pulse width limited by max. junction
temperature.
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.14mH
R
G
= 25
Ω
, I
AS
= 58A, V
GS
=10V. Part not recommended for use
above this value.
When mounted on 1″ square PCB (FR-4 or G-10 Material).
For recommended
footprint and soldering techniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C.
I
SD
≤
58A, di/dt
≤
650A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
ꢀ
Pulse width
≤
400µs; duty cycle
≤
2%.
2
IRFB4410/IRFS4410/IRFSL4410
1000
100
10
1000
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
TOP
100
10
1
BOTTOM
BOTTOM
4.5V
1
4.5V
1
60µs PULSE WIDTH
≤
60µs PULSE WIDTH
≤
Tj = 175°C
Tj = 25°C
0.1
0.1
10
100
1000
0.1
1
10
100
1000
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
100
10
3.0
2.5
2.0
1.5
1.0
0.5
I
= 58A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
J
1
V
= 25V
DS
≤
60µs PULSE WIDTH
0.1
2
3
4
5
6
7
8
9
10
-60 -40 -20
T
0
20 40 60 80
100 120 140 160 180
, Junction Temperature (°C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4.
Normalized On-Resistance vs. Temperature
Fig 3.
Typical Transfer Characteristics
100000
10000
1000
12.0
V
= 0V,
= C
f = 1 MHZ
GS
I
= 58A
D
C
C
C
+ C
, C
SHORTED
iss
gs
gd
ds
= C
V
V
V
= 80V
= 50V
= 20V
10.0
8.0
6.0
4.0
2.0
0.0
rss
oss
gd
DS
DS
DS
= C
+ C
ds
gd
C
iss
C
oss
C
rss
100
1
10
, Drain-to-Source Voltage (V)
100
0
20
40
60
80
100
120
V
Q
Total Gate Charge (nC)
DS
G
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFB4410/IRFS4410/IRFSL4410
1000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
100µsec
1msec
100
T
= 175°C
J
10msec
DC
T
= 25°C
J
10
1
Tc = 25°C
Tj = 175°C
V
= 0V
GS
Single Pulse
1
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
, Source-to-Drain Voltage (V)
0
1
10
100
1000
V
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode Forward Voltage
130
125
120
115
110
105
100
100
90
80
70
60
50
40
30
20
10
0
Limited By Package
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
25
50
75
100
125
150
175
T
, Case Temperature (°C)
T ,
Temperature ( °C )
C
J
Fig 10.
Drain-to-Source Breakdown Voltage
Fig 9.
Maximum Drain Current vs. Case Temperature
2.0
900
I
D
800
700
600
500
400
300
200
100
0
TOP
6.7A
9.7A
BOTTOM 58A
1.5
1.0
0.5
0.0
0
20
V
40
60
80
100
120
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
J
Drain-to-Source Voltage (V)
DS,
Fig 12.
Maximum Avalanche Energy vs. DrainCurrent
Fig 11.
Typical C
OSS
Stored Energy
4
IRFB4410/IRFS4410/IRFSL4410
1
0.1
D = 0.50
0.20
0.10
0.05
R
1
R
1
R
2
R
2
Ri (°C/W)
τ
i (sec)
0.2736 0.000376
0.02
0.01
0.01
τ
J
τ
J
τ
τ
C
τ
1
τ
1
Ci=
τ
i
/
Ri
τ
2
τ
2
0.3376 0.004143
SINGLE PULSE
0.001
0.0001
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆
Tj = 150°C and
Tstart =25°C (Single Pulse)
Duty Cycle = Single Pulse
0.01
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆
Τ
j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
250
200
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as neither T
jmax
nor
Iav (max) is exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
TOP
BOTTOM 1%
Duty Cycle
= 58A
Single Pulse
I
D
6. I
av
= Allowable avalanche current.
7.
∆
T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche =
t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
0
25
50
75
100
125
150
175
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
Starting T
, Junction Temperature (°C)
I
av
= 2
D
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
J
Fig 15.
Maximum Avalanche Energy vs. Temperature
5
IRFB4410/IRFS4410/IRFSL4410
20
15
10
5
5.0
4.5
4.0
3.5
3.0
I
I
I
I
= 150µA
= 250µA
= 1.0mA
= 1.0A
D
D
D
D
2.5
2.0
1.5
1.0
I
= 19A
= 85V
F
V
R
T
= 25°C
_____
= 125°C ———-
J
T
J
0
-75 -50 -25
0
25 50 75
100 125 150 175 200
, Temperature ( °C )
100 200 300 400 500 600 700 800 900
1000
T
di /dt (A/µs)
f
J
Fig. 17
– Typical Recovery Current vs. di
f
/dt
Fig 16.
Threshold Voltage vs. Temperature
400
20
350
300
250
200
150
100
50
15
10
5
I
= 19A
= 85V
I
= 38A
= 85V
F
F
V
V
T
R
R
T
= 25°C
_____
= 125°C ———-
= 25°C
_____
= 125°C ———-
J
J
T
T
J
J
0
0
100 200 300 400 500 600 700 800 900
1000
100 200 300 400 500 600 700 800 900
1000
di /dt (A/µs)
f
di /dt (A/µs)
f
Fig. 18
– Typical Recovery Current vs. di
f
/dt
Fig. 19
– Typical Stored Charge vs. di
f
/dt
400
350
300
250
200
150
100
50
I
= 38A
= 85V
F
V
R
T
= 25°C
_____
= 125°C ———-
J
T
J
0
100 200 300 400 500 600 700 800 900
1000
di /dt (A/µs)
f
Fig. 20
– Typical Stored Charge vs. di
f
/dt
6
IRFB4410/IRFS4410/IRFSL4410
Driver Gate Drive
P
.
W.
Period
D.U.T
Period
D =
P.W.
+
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Current
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 20.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
V
2
GS
Ω
0.01
t
p
I
AS
Fig 21b.
Unclamped Inductive Waveforms
Fig 21a.
Unclamped Inductive Test Circuit
L
D
V
DS
V
DS
90%
+
–
V
DD
10%
V
GS
D.U.T
V
GS
Pulse Width < 1µs
Duty Factor < 0.1%
t
d(on)
t
d(off)
t
r
t
f
Fig 22a.
Switching Time Test Circuit
Fig 22b.
Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
Vgs(th)
0
1K
Qgs1
Qgs2
Qgd
Qgodr
Fig 23a.
Gate Charge Test Circuit
Fig 23b.
Gate Charge Waveform
7
IRFB4410/IRFS4410/IRFSL4410
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
TO-220AB packages are not recommended for Surface Mount Application.
8
IRFB4410/IRFS4410/IRFSL4410
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
9
IRFB4410/IRFS4410/IRFSL4410
D
2
Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D
2
Pak (TO-263AB) Part Marking Information
10
IRFB4410/IRFS4410/IRFSL4410
D
2
Pak (TO-263AB)
T
a
pe & Reel Information
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS
TO EIA-418.
2. CONTROLLING
DIMENSION: MILLIMETER.
3. DIMENSION
MEASURED @ HUB.
26.40 (1.039)
24.40 (.961)
4
3
4. INCLUDES
FLANGE DISTORTION @ OUTER EDGE.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
11
Note: For
the most current drawings please refer to the IR website at:
