Infineon-Technologies-IRFBA1404PPBF
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PD – 95903A
IRFBA1404PPbF
HEXFET
®
Power MOSFET
Typical Applications
Industrial Motor Drive
D
V
DSS
= 40V
Benefits
R
DS(on)
= 3.7m
Ω
l
l
l
l
l
l
l
l
Advanced Process Technology
Ultra Low On-Resistance
Increase Current Handling Capability
175°C Operating Temperature
Fast Switching
Dynamic dv/dt Rating
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
G
I
D
= 206A
S
Description
This Stripe Planar design of HEXFET
®
Power MOSFETs utilizes the latest
processing techniques to achieve extremely low on-resistance per silicon area.
Additional features of this MOSFET are a 175
o
C junction operating tempera-
ture, fast switching speed and improved ruggedness in single and repetitive
avalanche. The Super-220
TM
is a package that has been designed to have the
same mechanical outline and pinout as the industry standard TO-220 but can
house a considerably larger silicon die. The result is significantly increased
current handling capability over both the TO-220 and the much larger TO-247
Super
–
220
package. The combination of extremely low on-resistance silicon and the
TM
Super-220
package makes it ideal to reduce the component count in
multiparalled TO-220 applications, reduce system power dissipation, upgrade
existing designs or have TO-247 performance in a TO-220 outline.
These benefits make this design an extremely efficient and reliable device for
use in a wide variety of applications.
Absolute Maximum Ratings
Parameter
Max.
Units
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
206
145
A
650
P
D
@T
C
= 25°C
Power Dissipation
300
W
W/°C
V
Linear Derating Factor
2.0
V
GS
E
AS
I
AR
Gate-to-Source Voltage
± 20
480
Single Pulse Avalanche Energy
Avalanche Current
mJ
A
See Fig.12a, 12b, 14, 15
E
AR
dv/dt
T
J
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
mJ
V/ns
5.0
-40 to
+ 175
-55 to
+ 175
300 (1.6mm from case )
20
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Recommended clip force
°C
N
1
09/22/10
IRFBA1404PPbF
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
40 –––
–––
Conditions
V
GS
= 0V, I
D
= 250µA
V
(BR)DSS
Drain-to-Source Breakdown Voltage
V
∆
V
(BR)DSS
/
∆
T
J
Breakdown Voltage Temp. Coefficient
––– 0.036
––– V/°C
Reference to 25°C, I
D
= 1mA
R
DS(on)
V
GS(th)
g
fs
Static Drain-to-Source On-Resistance
––– ––– 3.7
m
Ω
V
GS
= 10V, I
D
= 95A
Gate Threshold Voltage
2.0
––– 4.0
V
V
DS
= 10V, I
D
= 250µA
V
DS
= 25V, I
D
= 60A
V
DS
= 40V, V
GS
= 0V
V
DS
= 32V, V
GS
= 0V, T
J
= 150°C
V
GS
= 20V
Forward Transconductance
106 –––
–––
––– ––– 20
––– –––
250
––– –––
200
––– –––
-200
––– 160
200
S
I
DSS
Drain-to-Source Leakage Current
µA
nA
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
I
GSS
V
GS
= -20V
Q
g
I
D
= 95A
Q
gs
Q
gd
t
d(on)
t
r
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Turn-On Delay Time
Rise Time
–––
–––
–––
35 –––
42 60
17 –––
nC
ns
V
DS
= 32V
V
GS
= 10V
V
DD
= 20V
––– 140
–––
I
D
= 95A
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
–––
–––
72 –––
26 –––
R
G
= 2.5
Ω
R
D
= 0.21
Ω
Between lead,
6mm (0.25in.)
D
S
L
D
L
S
Internal Drain Inductance
Internal Source Inductance
–––
–––
2.0 –––
nH
pF
G
from package
–––
5.0
and center of die contact
V
GS
= 0V
C
iss
Input Capacitance
––– 7360
–––
––– 1680
–––
––– 240
–––
––– 6630
–––
––– 1490
–––
––– 1540
–––
C
oss
Output Capacitance
V
DS
= 25V
C
rss
Reverse Transfer Capacitance
Output Capacitance
ƒ = 1.0MHz, See Fig. 5
C
oss
V
GS
= 0V,
V
DS
= 1.0V,
ƒ = 1.0MHz
V
GS
= 0V,
V
DS
= 32V,
ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 32V
C
oss
Output Capacitance
C
oss
eff.
Effective Output Capacitance
ꢀ
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
MOSFET symbol
D
I
S
––– –––
206
showing the
A
G
I
SM
Pulsed Source Current
(Body Diode)
integral reverse
––– –––
650
S
p-n junction diode.
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
––– –––
1.3
––– 71 110
––– 180 270
V
T
J
= 25°C, I
S
= 95A, V
GS
= 0V
ns
T
J
= 25°C, I
F
= 95A
Q
rr
t
on
nC di/dt
= 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Thermal Resistance
Parameter
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
Typ.
–––
0.5
Max.
0.50
–––
58
Units
R
θ
JC
R
θ
CS
R
θ
JA
°C/W
–––
2
IRFBA1404PPbF
1000
100
10
1000
100
10
VGS
15V
VGS
15V
TOP
TOP
10V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
BOTTOM 4.5V
4.5V
4.5V
20µs PULSE WIDTH
°
T =
175 C
J
20µs PULSE WIDTH
T =
25 C
J
°
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
2.5
159A
=
I
D
°
T =
25 C
J
°
2.0
1.5
1.0
0.5
0.0
T =
175 C
J
100
V
= 25V
DS
V
=
1
0V
GS
20µs PULSE WIDTH
10
4.0
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
°
5.0
6.0
7.0 8.0 9.0
T ,
Junction Temperature (
C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
3
IRFBA1404PPbF
20
16
12
8
12000
I
D
= 95A
V
= 0V,
f = 1MHz
C SHORTED
ds
GS
C
= C
+ C
iss
gs
gd ,
C
= C
V
= 32V
= 20V
rss
gd
DS
10000
8000
6000
4000
2000
0
C
= C
+ C
V
oss
ds
gd
DS
C
iss
C
oss
4
FOR TEST CIRCUIT
SEE FIGURE 13
C
rss
0
1
10
100
0
40
80
120
160
200
240
V
, Drain-to-Source Voltage (V)
Q ,
Total Gate Charge (nC)
DS
G
Fig 6.
Typical Gate Charge Vs.
Fig 5.
Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
10000
1000
100
10
1000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
°
T =
175 C
J
10us
100
10
1
100us
°
T =
25 C
J
1ms
10ms
°
T =
25 C
C
J
°
T =
175 C
V
= 0 V
Single Pulse
GS
2.0
1
1
10
100
0.4
0.8
1.2
1.6
2.4
V
, Drain-to-Source Voltage (V)
V
,Source-to-Drain Voltage (V)
DS
SD
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
4
IRFBA1404PPbF
R
D
240
180
120
60
V
DS
LIMITED BY PACKAGE
V
GS
D.U.T.
R
G
+
V
DD
–
10V
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
Fig 10a.
Switching Time Test Circuit
V
DS
90%
0
25
50
75
100
125
150
175
°
T ,
Case Temperature
( C)
C
10%
V
GS
Fig 9.
Maximum Drain Current Vs.
t
t
r
t
t
f
d(on)
d(off)
Case Temperature
Fig 10b.
Switching Time Waveforms
1
D = 0.50
0.20
0.1
0.01
0.10
0.05
SINGLE PULSE
0.02
0.01
(THERMAL RESPONSE)
P
2
DM
t
1
t
2
Notes:
1. Duty factor D =
t /
t
1
2. Peak T
=
P
x Z
+ T
thJC C
J
DM
0.001
0.00001
0.0001
0.001
0.01
0.1
t ,
Rectangular Pulse Duration (sec)
1
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
IRFBA1404PPbF
1000
800
600
400
200
0
15V
I
D
TOP
39A
67A
BOTTOM 95A
DRIVER
+
L
V
DS
D.U.T
R
G
V
DD
–
I
A
AS
20V
0.01
Ω
t
p
Fig 12a.
Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
175
°
Starting T
, Junction Temperature
( C)
J
I
AS
Fig 12c.
Maximum Avalanche Energy
Fig 12b.
Unclamped Inductive Waveforms
Vs. Drain Current
Q
G
10 V
50
48
46
44
42
40
Q
Q
GD
GS
V
G
Charge
Fig 13a.
Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.
T
.
50K
Ω
.2
µ
F
12V
.3
µ
F
+
V
DS
D.U.
T
.
–
0
20
I
40
60
80
100
V
GS
, Avalanche Current ( A)
3mA
AV
I
I
D
G
Current Sampling Resistors
Fig 12d.
Typical Drain-to-Source
Voltage
Vs. Avalanche Current
Fig 13b.
Gate Charge Test Circuit
6
IRFBA1404PPbF
1000
100
10
Duty Cycle = Single Pulse
0.01
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
Tj = 25°C due to
∆
avalanche losses
0.05
0.10
1
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current Vs.Pulsewidth
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
500
400
300
200
100
0
TOP
BOTTOM 10%
Duty Cycle
= 95A
Single Pulse
I
D
4. P
D (ave)
= Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆
T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as 25°C in Figure 15, 16).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche =
t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see figure 11)
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
J
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
Fig 15.
Maximum Avalanche Energy
I
av
= 2
D
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Vs. Temperature
7
IRFBA1404PPbF
Peak Diode Recovery dv/dt Test Circuit
+
–
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
D.U.T
+
–
–
+
R
G
•
dv/dt controlled by R
G
+
–
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
V
DD
Driver Gate Drive
P.W.
P
.
W.
Period
Period
D =
V
=10V
*
GS
D.U.
T
. I
W
aveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 16.
For N-Channel
HEXFET
®
Power MOSFETs
8
IRFBA1404PPbF
Super-220 ( TO-273AA ) Package Outline
9.00 [.
8.00 [.
11.00 [.433]
10.00 [.394]
B
A
5.00 [.196]
4.00 [.158]
0.25
1.50 [.059]
0.50 [.020]
13.50 [
12.50 [
4
15.00 [.590]
14.00 [.552]
1
2
3
4.00 [.157]
3.50 [.138]
14.50 [.570]
13.00 [.512]
1.00 [.039]
0.70 [.028]
4X
1.30 [.051]
0.90 [.036]
3X
3.00 [.118]
2.50 [.099]
2.55 [.100]
2X
0.25 [.010]
B A
MOSFET
IGBT
Notes:
Repetitive rating;
pulse width limited by
Pulse width
≤
400µs; duty cycle
≤
2%.
max. junction temperature.
ꢀ
C
oss
eff. is a fixed capacitance that gives the same charging time
Starting T
J
= 25°C, L = 0.11mH
R
G
= 25
Ω
, I
AS
= 95A.
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
. Refer to AN-1001
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 95A.
I
SD
≤
95A, di/dt
≤
150A/µs, V
DD
≤
V
(BR)DSS
T
J
≤
175°C
,
9
IRFBA1404PPbF
Super-220 (TO-273AA) Part Marking Information
EXAMPLE: THIS IS AN IRFBA22N50A WITH
ASSEMBLY LOT CODE 1789
ASSEMBLED ON WW 19, 1997
IN THE ASSEMBLY LINE “C”
PART NUMBER
INTERNATIONAL RECTIFIER
IRFBA22N50A
LOGO
719C
17
89
DATE CODE
YEAR 7 = 1997
WEEK 19
LINE C
ASSEMBLY LOT CODE
TOP
Note: “P” in assembly line position
indicates “Lead-Free”
Super-220
not recommended for surface mount application
Notes:
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial
market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
10
