Infineon-Technologies-IRFD9120PbF

IRFD9120, SiHFD9120  

Vishay Siliconix  

Power MOSFET  

FEATURES  

• Dynamic

 

dV/dt Rating  

PRODUCT SUMMARY  

V

DS

(V)  

– 100  

A

v

aila

b

le  

• Repetitive

 

Avalanche Rated  

R

V

GS

= – 10 V  

0.60  

RoHS*  

• For

 

Automatic Insertion  

• End

 

Stackable  

Q

g

(Max.) (nC)  

18  

3.0  

9.0  

COMPLIANT  

Q

Q

• P-Channel  

Configuration  

Single  

• 175

 

°C Operating Temperature  

• Fast

 

Switching  

S

• Lead

 

(Pb)-free Available  

HEXDIP  

DESCRIPTION  

G

Third generation Power MOSFETs from Vishay provide the  

designer with the best combination of fast switching,  

ruggedized device design, low on-resistance and  

cost-effectiveness.  

The 4 pin DIP package is a low cost machine-insertiable  

case style which can be stacked in multiple combinations on  

standard 0.1″ pin centers. The dual drain serves as a thermal  

link to the mounting surface for power dissipation levels up to  

1 W.  

S

G

D

D

P-Channel MOSFET  

ORDERING INFORMATION  

Package  

HEXDIP  

IRFD9120PbF  

SiHFD9120-E3  

IRFD9120  

Lead (Pb)-free  

SnPb  

SiHFD9120  

ABSOLUTE MAXIMUM RATINGS

T

C

= 25 °C, unless otherwise noted  

PARAMETER  

SYMBOL  

LIMIT  

– 100  

20  

UNIT  

Drain-Source Voltage  

Gate-Source Voltage  

V

DS  

V

V

GS  

T

C

= 25 °C  

T

C

=

1

0

0

°

C  

– 1.0  

Continuous Drain Current  

V

GS

at – 10 V  

I

D  

– 0.70  

– 8.0  

A

Pulsed Drain Current

a  

I

DM  

Linear Derating Factor  

0.0083  

140  

W/°C  

mJ  

A

Single Pulse Avalanche Energy

b  

Repetitive Avalanche Current

a  

Repetitive Avalanche Energy

a  

E

AS  

I

AR  

– 1.0  

E

AR  

0.13  

mJ  

W

Maximum Power Dissipation  

T

C

= 25 °C  

P

D  

1.3  

Peak Diode Recovery dV/dt

c  

dV/dt  

T

J

, T

stg  

– 5.5  

V/ns  

Operating Junction and Storage Temperature Range  

Soldering Recommendations (Peak Temperature)  

– 55 to + 175  

300

d  

°C  

for 10 s  

Notes  

a. Repetitive

 

rating; pulse width limited by maximum junction temperature (see fig. 11).  

b. V

DD

= 25 V, starting T

J

= 25 °C, L = 52 mH, R

G

= 25

Ω

, I

AS

= – 2.0 A (see fig. 12).  

c. I

SD

≤

– 6.8 A, dI/dt

≤

110 A/µs, V

DD

≤

V

DS

, T

J

≤

175 °C.  

d. 1.6

 

mm from case.  

* Pb containing terminations are not RoHS compliant, exemptions may apply  

Document Number: 91139  

S-81273-Rev. A, 16-Jun-08  

1

IRFD9120, SiHFD9120  

Vishay Siliconix  

THERMAL RESISTANCE RATINGS  

PARAMETER  

SYMBOL  

TYP.  

MAX.  

UNIT  

Maximum Junction-to-Ambient  

R

thJA  

–

120  

°C/W  

SPECIFICATIONS

T

J

= 25 °C, unless otherwise noted  

PARAMETER  

SYMBOL  

TEST CONDITIONS  

MIN.  

TYP.  

MAX.  

UNIT  

Static  

Drain-Source Breakdown Voltage  

V

DS  

Δ

V

DS

/T

J  

V

GS(th)  

I

GSS  

V

GS

= 0 V, I

D

= 250 µA  

– 100  

–

–

V

V/°C  

V

V

Reference to 25 °C, I

D

= – 1 mA  

V

DS

= V

GS

, I

D

= 250 µA  

–

– 0.10  

–

Gate-Source Threshold Voltage  

Gate-Source Leakage  

– 2.0  

–

–

–

–

–

–

– 4.0  

100  

– 100  

– 500  

0.60  

–

V

GS  

=

20 V  

–

nA  

V

DS

= – 100 V, V

GS

= 0 V  

–

Zero Gate Voltage Drain Current  

I

DSS  

µA  

V

–

–

Drain-Source On-State Resistance  

Forward Transconductance  

Dynamic  

R

DS(on)  

g

fs  

V

GS

= – 10 V  

V

DS

= – 50 V, I

D

= – 0.60 A

b  

I

D

= – 0.6 A

b  

Ω

0.71  

S

Input Capacitance  

Output Capacitance  

Reverse Transfer Capacitance  

Total Gate Charge  

Gate-Source Charge  

Gate-Drain Charge  

Turn-On Delay Time  

Rise Time  

C

iss  

C

oss  

C

rss  

Q

g  

–

–

–

–

–

–

–

–

–

–

390  

170  

45  

–

–

V

GS

= 0 V  

f = 1.0 MHz, see fig. 5  

V

–

–

pF  

nC  

18  

3.0  

9.0  

–

I

D

= – 6.8 A, V

DS

= – 80 V  

see fig. 6 and 13

b  

Q

gs  

Q

gd  

t

d(on)  

t

r  

V

–

–

9.6  

29  

21  

25  

–

V

ns  

Turn-Off Delay Time  

Fall Time  

t

d(off)  

t

f  

R

–

–

D

Between lead,  

Internal Drain Inductance  

L

D  

L

S  

–

–

4.0  

6.0  

–

–

6 mm (0.25″) from  

package and center of  

die contact  

nH  

G

Internal Source Inductance  

S

Drain-Source Body Diode Characteristics  

Continuous Source-Drain Diode Current  

MOSFET symbol  

showing the  

integral reverse  

p – n junction diode  

D

I

S  

–

–

–

–

– 1.0  

– 8.0  

A

G

Pulsed Diode Forward Current

a  

I

SM  

S

Body Diode Voltage  

V

SD  

t

rr  

T

J

= 25 °C, I

S

= – 1.0 A, V

GS

= 0 V

b  

–

–

–

–

– 6.3  

200  

V

Body Diode Reverse Recovery Time  

Body Diode Reverse Recovery Charge  

Forward Turn-On Time  

98  

ns  

µC  

T

J

= 25 °C, I

F

= – 6.8 A, dI/dt = 100 A/µs

b  

Q

rr  

t

on  

0.33  

0.66  

Intrinsic turn-on time is negligible (turn-on is dominated by L

S

and L

D

)  

Notes  

a. Repetitive

 

rating; pulse width limited by maximum junction temperature (see fig. 11).  

b. Pulse

 

width

≤

300 µs; duty cycle

≤

2 %.  

2

Document Number: 91139  

S-81273-Rev. A, 16-Jun-08  

IRFD9120, SiHFD9120  

Vishay Siliconix  

TYPICAL CHARACTERISTICS

 

25 °C, unless otherwise noted  

Fig. 1 – Typical Output Characteristics, T

C

= 25 °C  

Fig. 3 – Typical Transfer Characteristics  

Fig. 4 – Normalized On-Resistance vs. Temperature  

Fig. 2 – Typical Output Characteristics, T

C

= 175 °C  

Document Number: 91139  

S-81273-Rev. A, 16-Jun-08  

3

IRFD9120, SiHFD9120  

Vishay Siliconix  

Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage  

Fig. 7 – Typical Source-Drain Diode Forward Voltage  

Fig. 8 – Maximum Safe Operating Area  

Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage  

4

Document Number: 91139  

S-81273-Rev. A, 16-Jun-08  

IRFD9120, SiHFD9120  

Vishay Siliconix  

R

D  

V

DS  

V

GS  

D.U.T.  

R

G  

–

+

V

DD  

– 10

V  

P

u

lse

w

idth

≤

1

µ

s  

D

u

ty factor

≤

0.1

%  

Fig. 10a – Switching Time Test Circuit  

t

d(on)

t

r  

t

d(off)

t

f  

V

GS  

10

%  

90

%  

V

DS  

Fig. 9 – Maximum Drain Current vs. Case Temperature  

Fig. 10b – Switching Time Waveforms  

Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to-Case  

Document Number: 91139  

S-81273-Rev. A, 16-Jun-08  

5

IRFD9120, SiHFD9120  

Vishay Siliconix  

L

I

AS  

V

DS  

V

ary t

p

to o

b

tain  

req

u

ired I

AS  

V

DS  

D.U.T.  

I

AS  

R

G  

–

V

+

DD  

V

DD  

t

p  

– 10

V

 

0.01

Ω  

t

p  

V

DS  

Fig. 12a – Unclamped Inductive Test Circuit  

Fig. 12b – Unclamped Inductive Waveforms  

Fig. 12c – Maximum Avalanche Energy vs. Drain Current  

C

u

rrent reg

u

lator  

Same type as D.U.T.  

50 k

Ω

 

Q

G  

12

V

 

0.2

µ

F  

0.3

µ

F  

– 10

V  

–

Q

GS  

Q

GD  

V

+

DS  

D.U.T.  

V

G  

V

GS  

– 3 mA  

Charge  

I

G  

I

D  

C

u

rrent sampling resistors  

Fig. 13b – Gate Charge Test Circuit  

Fig. 13a – Basic Gate Charge Waveform  

6

Document Number: 91139  

S-81273-Rev. A, 16-Jun-08  

IRFD9120, SiHFD9120  

Vishay Siliconix  

Peak Diode Recovery dV/dt Test Circuit  

D.U.T.  

+

Circ

u

it layo

u

t considerations  

•

Lo

w

stray ind

u

ctance  

•

Gro

u

nd plane  

•

Lo

w

leakage ind

u

ctance  

c

u

rrent transformer  

–

+

–

+

–

R

G  

+

–

•

d

V

/dt controlled

b

y R

G  

•

I

SD

controlled

b

y d

u

ty factor “D”  

•

D.U.T. – de

v

ice

u

nder test  

V

DD  

Compliment

N

-Channel of D.U.

T

. for dri

v

er  

Dri

v

er gate dri

v

e  

P.

W

.  

Period  

Period  

D =  

P.

W

.  

V

= – 10

V

*  

GS  

D.U.T. I

 

w

a

v

eform  

SD  

Re

v

erse  

reco

v

ery  

c

u

rrent  

Body diode for

w

ard  

c

u

rrent  

dI/dt  

D.U.T.

V w

a

v

eform  

DS  

Diode reco

v

ery  

d

V

/dt  

V

DD  

Re-applied  

v

oltage  

Body diode for

w

ard drop  

Ripple

≤

5

%  

Ind

u

ctor c

u

rrent  

I

SD  

*

V

GS

= – 5

V

for logic le

v

el and

 

– 3

V

dri

v

e de

v

ices  

Fig. 14 – For P-Channel  

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon  

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and  

Document Number: 91139  

S-81273-Rev. A, 16-Jun-08  

7

Legal Disclaimer Notice  

Vishay  

Disclaimer  

All product specifications and data are subject to change without notice.  

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf  

(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein  

or in any other disclosure relating to any product.  

Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any  

information provided herein to the maximum extent permitted by law. The product specifications do not expand or  

otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed  

therein, which apply to these products.  

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this  

document or by any conduct of Vishay.  

The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless  

otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such  

applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting  

from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding  

products designed for such applications.  

Product names and markings noted herein may be trademarks of their respective owners.  

Document Number: 91000  

Revision: 18-Jul-08  

1