Infineon-Technologies-IRFH4251DTRPBF

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Infineon-Technologies-IRFH4251DTRPBF
Fast
IR
FET™  
IRFH4251DPbF  
HEXFET

®

Power MOSFET  
Q1  
25  
Q2  
25  
V

DSS  

V
R

DS(on)

max  
(@V

GS

= 4.5V)  
4.60  
10
 
1.10  
44  
m
  
nC  
Qg

(typical)  

I

D  

45
 
45
  
A
(@T

C

= 25°C)  
Applications  
Control and Synchronous MOSFETs for synchronous buck  
converters  
DUAL PQFN 5X6 mm  
Benefits  
Features  
Control and synchronous MOSFETs in one package  
Increased power density  
Lower switching losses  
Lower conduction losses  
Lower Switching Losses  
Environmentally friendlier  
Increased reliability  
Low charge control MOSFET (10nC typical)  
results in  
Low R

DSON

synchronous MOSFET (<1.10m
)  
Intrinsic Schottky Diode with Low Forward Voltage on Q2  
RoHS Compliant, Halogen-Free  
MSL1, Industrial Qualification  
Base part number  
Package Type  
Standard Pack  
Orderable Part Number  
IRFH4251DTRPbF  
Form  
Quantity  
4000  
IRFH4251DPbF  
Dual PQFN 5mm x 6mm  
Tape and Reel  
Absolute Maximum Ratings  
Parameter  
Gate-to-Source Voltage  
Continuous Drain Current, V

GS

@ 4.5V  
Continuous Drain Current, V

GS

@ 4.5V  
Q1 Max.  
Q2 Max.  
Units  
V

GS  

± 20  
V
A
I

D

@ T

C

= 25°C  
64
  
51
  
188
  
151
  
I

D

@ T

C

= 70°C  
I

D

@ T

C

= 25°C  
Continuous Drain Current, V

GS

@ 4.5V  
(Source Bonding Technology Limited)  
45
  
45
  
I

DM  

Pulsed Drain Current  
Power Dissipation  
Power Dissipation  
120  
31  
750
  
63  
P

D

@T

C

= 25°C  
P

D

@T

C

= 70°C  
W
20  
40  
Linear Derating Factor  
0.25  
0.50  
W/°C  
°C  
T

J  

Operating Junction and  
Storage Temperature Range  
-55 to
 
+ 150  
T

STG  

Thermal Resistance  
Parameter  
Q1 Max.  
Q2 Max.  
Units  
Junction-to-Case
  
4.0  
20  
34  
24  
2.0  
12  
35  
22  
R

JC

(Bottom)  
R

JC

(Top)  
R

JA  

°C/W  
Junction-to-Case
  
Junction-to-Ambient
  
Junction-to-Ambient
  
R

JA

(<10s)  
Notes
through
are on page 12  
1
© 2014 International Rectifier  
May 20, 2014  

IRFH4251DPbF  
Static @ T

J

= 25°C (unless otherwise specified)  
Parameter  
Min. Typ. Max.
 
Units  
Conditions  
V

GS

= 0V, I

D

= 250µA  
V

GS

= 0V, I

D

= 1.0mA  
BV

DSS  

Drain-to-Source Breakdown Voltage  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
25  
25  
––– –––  
––– –––  
V
Breakdown Voltage Temp. Coefficient  
–––  
–––  
22  
20  
––– mV/°C
 
Reference to 25°C, I

D

= 1.0mA  
BV

DSS

/
T

J  

–––  
Reference to 25°C, I

D

= 10mA  
V

GS

= 10V, I

D

= 30A
  
––– 2.50
 
3.20  
––– 0.60
 
0.85  
––– 3.70
 
4.60  
––– 0.85
 
1.10  
R

DS(on)  

Static Drain-to-Source On-Resistance  
V

GS

= 10V, I

D

= 30A
  
m
  
V

GS

= 4.5V, I

D

= 30A
  

GS

= 4.5V, I

D

= 30A
  
V
V

GS(th)  

Gate Threshold Voltage  
1.1  
1.1  
1.6  
1.6  
2.1  
2.1  
V
Q1: V

DS

= V

GS

, I

D

= 35µA  
Q2: V

DS

= V

GS

, I

D

= 150µA  
Gate Threshold Voltage Coefficient  
Drain-to-Source Leakage Current  
––– -5.7 –––
 
mV/°C Q1: V

DS

= V

GS

, I

D

= 35µA  
V

GS(th)

/
T

J  

I

DSS  

I

GSS  

gfs  
––– -10 –––  
––– ––– 1.0  
––– ––– 250  
Q2: V

DS

= V

GS

, I

D

= 150µA  
µA V

DS

= 20V, V

GS

= 0V  
V

DS

= 20V, V

GS

= 0V  
Gate-to-Source Forward Leakage  
Gate-to-Source Reverse Leakage  
Forward Transconductance  
Q1/Q2 ––– ––– 100  
Q1/Q2 ––– ––– -100  
nA V

GS

= 20V  
V
V
V

GS

= -20V  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
131 ––– –––  
161 ––– –––  
S

DS

= 10V, I

D

= 30A  

DS

= 10V, I

D

= 30A  
Q

g  

Total Gate Charge  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
10  
44  
15  
66  
Q1  
Q

gs1  

Q

gs2  

Q

gd  

Pre-Vth Gate-to-Source Charge  
Post-Vth Gate-to-Source Charge  
Gate-to-Drain Charge  
Gate Charge Overdrive  
Switch Charge (Q

gs2

+ Q

gd

)  
Output Charge  
2.5 –––  
11 –––  
V

DS

= 13V  

GS

= 4.5V, I

D

= 30A  
V
1.6 –––  
4.2 –––  
3.8 –––  
nC  
Q2  
V

DS

= 13V  

GS

= 4.5V, I

D

= 30A  
15  
–––  
V
Q

godr  

Q

sw  

Q

oss  

R

G  

2.1 –––  
––– 13.8 –––  
––– 5.4 –––  
––– 19.2 –––  
–––  
–––  
–––  
10  
44  
–––  
–––  
nC V

DS

= 16V, V

GS

= 0V  
Gate Resistance  
2.4 –––  
  
––– 0.85 –––  
t

d(on)  

t

r  

t

d(off)  

t

f  

Turn-On Delay Time  
Rise Time  
–––  
–––  
–––  
10  
24  
61  
–––  
–––  
–––  
Q1  
V

DS

= 13V V

GS

= 4.5V  
I

D

= 30A, Rg = 1.8
  
ns  
––– 105 –––  
Q2  
Turn-Off Delay Time  
Fall Time  
–––  
–––  
–––  
–––  
13  
35  
15  
60  
–––  
–––  
–––  
–––  
V

DS

= 13V V

GS

= 4.5V  
I

D

= 30A, Rg = 1.8
  
C

iss  

Input Capacitance  
––– 1314 –––  
––– 5845 –––  
––– 365 –––  
––– 1703 –––  
V

GS

= 0V  
pF  
V

DS

= 13V  
C

oss  

C

rss  

Output Capacitance  
Reverse Transfer Capacitance  
ƒ = 1.0MHz  
–––  
92  
–––  
––– 408 –––  
2
© 2014 International Rectifier  
May 20, 2014  

IRFH4251DPbF  
Avalanche Characteristics  
Parameter  
Typ.  
–––  
–––  
Q1 Max.  
61  
Q2 Max.  
1292  
60  
Units  
mJ  
E

AS  

I

AR  

Single Pulse Avalanche Energy
  
Avalanche Current
  
30  
A
Diode Characteristics  
Parameter  
Min. Typ.
 
Max. Units  
Conditions  
I

S  

Continuous Source Current  
(Body Diode)  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
––– –––
 
45
  
––– –––
 
45
  
––– ––– 120  
––– –––
 
750
  
––– ––– 1.0  
––– –––
 
0.75  
A
A
V
MOSFET symbol  
showing the  
integral reverse  
p-n junction diode.  
I

SM  

V

SD  

t

rr  

Pulsed Source Current  
(Body Diode)  
Diode Forward Voltage  
T

J

= 25°C, I

S

= 30A, V

GS

= 0V
  
T

J

= 25°C, I

S

= 30A, V

GS

= 0V
  
Reverse Recovery Time  
Reverse Recovery Charge  
–––  
–––  
–––  
–––  
16  
36  
13  
67  
–––  
–––  
ns Q1
 
T

J

= 25°C, I

F

= 30A  

DD

= 13V, di/dt = 235A/µs
  
V
Q

rr  

––– nC
 
Q2 T

J

= 25°C, I

F

= 30A  
–––  

DD

= 13V, di/dt = 190A/µs
  
V
3
© 2014 International Rectifier  
May 20, 2014  

IRFH4251DPbF  
Q2 – Synchronous FET  
Q1 – Control FET  
1000  
100  
10  
1000  
100  
10  
VGS  
10V  
VGS  
10V  
TOP  
TOP  
5.0V  
4.5V  
3.5V  
3.1V  
2.9V  
2.7V  
2.5V  
5.0V  
4.5V  
3.5V  
3.0V  
2.7V  
2.5V  
2.3V  
BOTTOM  
BOTTOM  
1
1
2.3V  
0.1  
0.01  
60µs PULSE WIDTH  
Tj = 25°C  
60µs PULSE WIDTH  
Tj = 25°C  
2.5V  
0.1  
0.1  
1
10  
100  
0.1  
1
10  
, Drain-to-Source Voltage (V)  
DS  
100  
V
, Drain-to-Source Voltage (V)  
V
DS  
Fig 2.
 
Typical Output Characteristics  
Fig 1.
 
Typical Output Characteristics  
1000  
100  
10  
1000  
VGS  
10V  
VGS  
10V  
TOP  
TOP  
5.0V  
4.5V  
3.5V  
3.0V  
2.7V  
2.5V  
2.3V  
5.0V  
4.5V  
3.5V  
3.1V  
2.9V  
2.7V  
2.5V  
100  
10  
1
BOTTOM  
BOTTOM  
2.3V  
2.5V  
60µs PULSE WIDTH  
60µs PULSE WIDTH  
Tj = 150°C  
Tj = 150°C  
1
0.1  
1
10  
100  
0.1  
1
10  
100  
V
, Drain-to-Source Voltage (V)  
DS  
V
, Drain-to-Source Voltage (V)  
DS  
Fig 3.
 
Typical Output Characteristics  
Fig 4.
 
Typical Output Characteristics  
1000  
1000  
100  
10  
100  
10  
1
T
= 150°C  
J
T
= 150°C  
J
T
= 25°C  
J
T
= 25°C  
J
1
V
= 15V  
V
= 15V  
DS  
60µs PULSE WIDTH  
DS  
60µs PULSE WIDTH  
0.1  
0.1  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
V
, Gate-to-Source Voltage (V)  
GS  
V
, Gate-to-Source Voltage (V)  
GS  
Fig 6.
 
Typical Transfer Characteristics  
Fig 5.
 
Typical Transfer Characteristics  
4
© 2014 International Rectifier  
May 20, 2014  

IRFH4251DPbF  
Q2 – Synchronous FET  
Q1 – Control FET  
100000  
10000  
1000  
100  
100000  
10000  
1000  
V
= 0V,  
= C  
f = 1 MHZ  
V
= 0V,  
= C  
f = 1 MHZ  
+ C
 
, C  
GS  
GS  
C
C
C
+ C
 
, C  
SHORTED  
C
C
C
SHORTED  
iss  
gs  
gd  
ds  
iss  
gs  
gd  
ds  
= C  
= C  
rss  
oss  
gd  
= C
 
+ C  
rss  
oss  
gd  
= C
 
+ C  
ds  
gd  
ds  
gd  
C
iss  
C
C
iss  
oss  
C
oss  
C
rss  
C
rss  
10  
100  
1
10  
, Drain-to-Source Voltage (V)  
100  
1
10  
, Drain-to-Source Voltage (V)  
100  
V
V
DS  
DS  
Fig 7.
 
Typical Capacitance vs. Drain-to-Source Voltage  
Fig 8.
 
Typical Capacitance vs. Drain-to-Source Voltage  
14.0  
14.0  
I =
 
30A  
D
I =
 
30A  
D
12.0  
12.0  
V
V
= 20V  
= 13V  
DS  
DS  
V
V
= 20V  
= 13V  
DS  
DS  
10.0  
8.0  
6.0  
4.0  
2.0  
0.0  
10.0  
8.0  
6.0  
4.0  
2.0  
0.0  
0
5
10  
15  
20  
25  
30  
0
20  
40  
60  
80  
100  
120  
Q , Total
 
Gate Charge (nC)  
Q , Total
 
Gate Charge (nC)  
G
G
Fig 10.
 
Typical Gate Charge vs. Gate-to-Source Voltage  
Fig 9.
 
Typical Gate Charge vs. Gate-to-Source Voltage  
10000  
1000  
OPERATION IN THIS AREA  
OPERATION IN THIS AREA  
LIMITED BY R  
(on)  
LIMITED BY R  
(on)  
DS  
DS  
1000  
100  
10  
100  
10  
100µsec  
100µsec  
1msec  
Limited by package  
Limited by package  
1msec  
1
1
10msec  
10msec  
DC  
0.1  
0.01  
Tc = 25°C  
Tj = 150°C  
Single Pulse  
Tc = 25°C  
Tj = 150°C  
Single Pulse  
0.1  
0.01  
DC  
0.1  
1
10  
100  
0.1  
1
10  
100  
V
, Drain-to-Source Voltage (V)  
V
, Drain-to-Source Voltage (V)  
DS  
DS  
Fig 11.
 
Maximum Safe Operating Area  
Fig 12.
 
Maximum Safe Operating Area  
5
© 2014 International Rectifier  
May 20, 2014  

IRFH4251DPbF  
Q2 – Synchronous FET  
Q1 – Control FET  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
I
= 30A  
I
= 30A  
D
D
V
= 4.5V  
V
= 4.5V  
GS  
GS  
-60 -40 -20  
0
20 40 60 80
 
100 120 140 160  
-60 -40 -20  
0
20 40 60 80
 
100 120 140 160  
T
J
, Junction Temperature (°C)  
T
J
, Junction Temperature (°C)  
Fig 14.
 
Normalized On-Resistance vs. Temperature  
1000  
Fig 13.
 
Normalized On-Resistance vs. Temperature  
1000  
T
= 150°C  
J
100  
100  
10  
T
= 150°C  
J
T
= 25°C  
J
10  
T
= 25°C  
= 0V  
J
V
V
= 0V  
GS  
GS  
1.0  
1.0  
0.4  
0.5  
V
0.6  
0.7  
0.8  
0.9  
1.0  
0.2  
0.4  
0.6  
0.8  
1.0  
, Source-to-Drain Voltage (V)  
V
, Source-to-Drain Voltage (V)  
SD  
SD  
Fig 15.
 
Typical Source-Drain Diode Forward Voltage  
Fig 16.
 
Typical Source-Drain Diode Forward Voltage  
2.0  
10  
I
= 30A  
I
= 30A  
D
D
8
6
4
2
0
1.5  
1.0  
0.5  
0.0  
T
= 125°C  
J
T
= 125°C  
J
T
= 25°C  
J
T
= 25°C  
J
2
4
6
8
10 12 14 16 18 20  
2
4
6
8
10 12 14 16 18 20  
V
Gate -to -Source Voltage
 
(V)  
V
Gate -to -Source Voltage
 
(V)  
GS,  
GS,  
Fig 17.
 
Typical On-Resistance vs. Gate Voltage  
Fig 18.
 
Typical On-Resistance vs. Gate Voltage  
6
© 2014 International Rectifier  

IRFH4251DPbF  
Q2 – Synchronous FET  
Q1 – Control FET  
70  
60  
50  
40  
30  
20  
10  
0
200  
160  
120  
80  
Limited By Package  
Limited By Package  
40  
0
25  
50  
T
75  
100  
125  
150  
25  
50  
T
75  
100  
125  
150  
, Case Temperature (°C)  
, Case Temperature (°C)  
C
C
Fig 20.
 
Maximum Drain Current vs. Case Temperature  
Fig 19.
 
Maximum Drain Current vs. Case Temperature  
2.5  
2.2  
2.0  
1.8  
2.0  
1.5  
I
= 150µA  
D
1.6  
1.4  
1.2  
1.0  
I
= 35µA  
D
1.0  
0.5  
0.0  
-75 -50 -25  
0
25 50 75
 
100 125 150  
-75 -50 -25  
0
25 50 75
 
100 125 150  
T
, Temperature ( °C )  
T
, Temperature ( °C )  
J
J
Fig 21.
 
Threshold Voltage vs. Temperature  
Fig 22.
 
Threshold Voltage vs. Temperature  
250  
6000  
I
I
D
D
TOP  
7.7A  
12A  
TOP  
11A  
25A  
5000  
4000  
3000  
2000  
1000  
0
200  
150  
100  
50  
BOTTOM 30A  
BOTTOM 60A  
0
25  
50  
75  
100  
125  
150  
25  
50  
75  
100  
125  
150  
Starting T
 
, Junction Temperature (°C)  
Starting T
 
, Junction Temperature (°C)  
J
J
Fig 23.
 
Maximum Avalanche Energy vs. Drain Current  
Fig 24.
 
Maximum Avalanche Energy vs. Drain Current  
7
© 2014 International Rectifier  

IRFH4251DPbF  
100  
10  
1
Allowed avalanche Current vs avalanche  
pulsewidth, tav, assuming
Tj = 125°C and  
Tstart =25°C (Single Pulse)  
Allowed avalanche Current vs avalanche  
pulsewidth, tav, assuming

j = 25°C and  
Tstart = 125°C.  
0.1  
1.0E-06  
1.0E-05  
1.0E-04  
1.0E-03  
1.0E-02  
1.0E-01  
tav (sec)  
Fig 25.
 
Max Avalanche Current vs. Pulse Width (Q1)  
100  
10  
1
Allowed avalanche Current vs avalanche  
pulsewidth, tav, assuming
Tj = 125°C and  
Tstart =25°C (Single Pulse)  
Allowed avalanche Current vs avalanche  
pulsewidth, tav, assuming

j = 25°C and  
Tstart = 125°C.  
0.1  
1.0E-06  
1.0E-05  
1.0E-04  
1.0E-03  
tav (sec)  
1.0E-02  
1.0E-01  
1.0E+00  
Fig 26.
 
Max Avalanche Current vs. Pulse Width (Q2)  
10  
1
D = 0.50  
0.20  
0.10  
0.05  
0.1  
0.02  
0.01  
0.01  
SINGLE PULSE  
( THERMAL RESPONSE )  
Notes:  
1. Duty Factor D = t1/t2  
2. Peak Tj = P dm x Zthjc + Tc  
0.001  
1E-006  
1E-005  
0.0001  
0.001  
0.01  
0.1  
1
10  
t
, Rectangular Pulse Duration (sec)  
1
Fig 27.
 
Maximum Effective Transient Thermal Impedance, Junction-to-Case (Q1)  
© 2014 International Rectifier
 

8
May 20, 2014  

IRFH4251DPbF  
10  
1
D = 0.50  
0.20  
0.10  
0.05  
0.1  
0.02  
0.01  
0.01  
0.001  
0.0001  
SINGLE PULSE  
( THERMAL RESPONSE )  
Notes:  
1. Duty Factor D = t1/t2  
2. Peak Tj = P dm x Zthjc + Tc  
1E-006  
1E-005  
0.0001  
0.001  
0.01  
0.1  
1
10  
t
, Rectangular Pulse Duration (sec)  
1
Fig 28.
 
Maximum Effective Transient Thermal Impedance, Junction-to-Case (Q2)  
9
© 2014 International Rectifier  
May 20, 2014  

IRFH4251DPbF  
Fig 29.
Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET

®

Power MOSFETs  
V
(BR)DSS  
t
p
15V  
DRIVER  
+
L
V
DS  
D.U.T  
AS  
R
G
V
DD  
–
I
A
20V  
I
0.01  
t
p
AS  
Fig 30a.
 
Unclamped Inductive Test Circuit  
Fig 30b.
 
Unclamped Inductive Waveforms  
Fig 31a.
 
Switching Time Test Circuit  
Fig 31b.
 
Switching Time Waveforms  
Id  
Vds  
Vgs  
VDD  
Vgs(th)  
Qgs1  
Qgs2  
Qgd  
Qgodr  
Fig 32a.
Gate Charge Test Circuit  
Fig 32b.
Gate Charge Waveform  
10  
© 2014 International Rectifier  
May 20, 2014  

IRFH4251DPbF  
Dual PQFN 5×6 Outline “H” Package Details  
C
D
4
A
INDEX AREA  
(D/2xE/2)  
D2  
PIN#1 ID  
B
L1  
A1  
R0.30  
7x L2  
8x b  
8x K  
0.48  
D1  
1.15  
TOP VIEW  
SIDE VIEW  
D
i
m
ens
i
on Table  
V :
V
ery Th
i
n  
1.08  
0.94  
NOTE  
BOTTOM VIEW  
M
I
N
I
M
UM NOM
I
N
AL
 
MAX
I
M
UM  
A
A1  
b
0.80  
0.00  
0.30  
0
.
9
0  
0
.
0
2  
0.40  
1.00  
0
.
0
5  
0
.
5
0  
6
D
E
e
D1  
E1  
D2  
E2  
K
6
.
0
0 BSC  
5.00 BSC  
1.27 BSC  
2
.
5
7  
4
.
56  
0
.
9
3  
2
.
4
2  
4
.
4
1  
0.78  
4
.
01  
0.20  
1.67  
2
.
6
7  
4
.
66  
1.03  
4
.
26  
—  
4
.
16  
—  
L1  
L2  
1.77  
0
.
5
0  
1.87  
0
.
6
0  
0
.
4
0  
For more information on board mounting, including footprint and stencil recommendation, please refer to  
For more information on package inspection techniques, please refer to application note AN-1154:  
PQFN 5×6 Outline “H” Part Marking  
INTERNATIONAL  
RECTIFIER LOGO  
DATE CODE  
PART NUMBER  
XXXX  
(“4 or 5 digits”)  
ASSEMBLY  
SITE CODE  
(Per SCOP 200-002)  
MARKING CODE  
XYWWX  
XXXXX  
(Per Marking Spec)  
PIN 1  
IDENTIFIER  
LOT CODE  
(Eng Mode – Min last 4 digits of EATI#)  
(Prod Mode – 4 digits of SPN code)  
Note: For the most current drawing please refer to IR website at

11  
© 2014 International Rectifier  
May 20, 2014  
 

IRFH4251DPbF  
Dual PQFN 5×6 Outline Tape and Reel  
Note: For the most current drawing please refer to IR website at

Qualification Information

†  

Industrial  
Qualification level  
(per JEDEC JESD47F

††

guidelines )  
MSL1  
DUAL PQFN 5mm x 6mm  
Moisture Sensitivity Level  
RoHS Compliant  
(per JEDEC J-STD-020D

††)  

Yes  
†
††  
Qualification standards can be found at International Rectifier’s web site

Applicable version of JEDEC standard at the time of product release.  
Notes:  
Repetitive rating;
 
pulse width limited by max. junction temperature.  
Starting T

J

= 25°C,  
Q1: L = 0.14mH, R

G

= 50
, I

AS

= 30A;  
Q2: L = 0.72mH, R

G

= 50
, I

AS

= 60A.  
Pulse width
≤
400µs; duty cycle
≤
2%.  
R

is measured at T

J

approximately 90°C.  
When mounted on 1 inch square
 
PCB (FR-4). Please refer to AN-994 for more details:  
Calculated continuous current based on maximum allowable junction temperature.  
Current is limited to Q1 = 45A & Q2 = 45A by source bonding technology.  
Pulsed drain current is limited to 180A by source bonding technology.  
12  
© 2014 International Rectifier  
May 20, 2014  
 

IRFH4251DPbF  
Revision History  
Date  
Comments  

Updated the schematic drawing, on page 1.  

Updated the Features and Benefits table, on page 1.  

Updated Vsd for Q2 from 1.0V to 0.75V, on page 3.  

Added Tape and Reel drawing, on page 12.  
05/28/2013  
06/10/2013  
08/15/2013  
01/16/2014  
5/20/2014  

Updated the MSL level from MSL3 to MSL2, on pages 1 & 12.  

Added “Fast
IR
FET™” above the part number, on page 1.  

Added part marking drawing, on page 11.  

Update the MSL level from MSL2 to MSL1, on page 1 & 12.  

Updated fig. 25 to show the max avalanche plateau at 45A, on page 8.  

Corrected fig. 26 to cap the curves at package limitation current of 45A, on page 8.  
IR WORLD HEADQUARTERS:
101 N. Sepulveda Blvd., El Segundo, California 90245, USA  
To contact International Rectifier, please visit

13  
© 2014 International Rectifier  
May 20, 2014