Infineon-Technologies-IRFH7446TRPBF
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Strong
IR
FET
IRFH7446PbF
HEXFET
®
Power MOSFET
Applications
l
Brushed Motor drive applications
l
BLDC Motor drive applications
l
PWM Inverterized topologies
l
Battery powered circuits
l
Half-bridge and full-bridge topologies
l
Synchronous rectifier applications
l
Resonant mode power supplies
l
OR-ing and redundant power switches
l
DC/DC and AC/DC converters
V
DSS
R
DS(on)
typ.
max.
40V
2.5m
Ω
3.3m
Ω
117A
I
D (Silicon Limited)
I
D
85A
(Package Limited)
Benefits
l
Improved Gate,
Avalanche and Dynamic
dV/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
RoHS Compliant containing no Lead, no Bromide,
and no Halogen
PQFN 5X6 mm
Base Part Number
Package Type
Standard Pack
Form
Tape and Reel
Tape and Reel
Orderable part number
Note
Quantity
4000
IRFH7446PBF
PQFN 5mm x 6mm
PQFN 5mm x 6mm
IRFH7446TRPBF
IRFH7446TR2PBF
400
EOL notice #259
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
125
100
75
50
25
0
I
= 50A
D
Limited By Package
T
= 125°C
J
T
= 25°C
J
4
6
8
10
12 14 16
18 20
25
50
T
75
100
125
150
, Case Temperature (°C)
C
V
Gate -to -Source Voltage
(V)
GS,
Fig 2.
Maximum Drain Current vs. Case Temperature
Fig 1.
Typical On-Resistance vs. Gate Voltage
1
A
ugust 28, 2015
IRFH7446PbF
Absolute Maximum Ratings
Symbol
Parameter
Max.
Units
117
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
D
@ T
C
= 25°C
I
DM
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Package Limited)
Pulsed Drain Current
74
85
A
468
Maximum Power Dissipation
78
P
D
@T
C
= 25°C
W
Linear Derating Factor
0.63
W/°C
V
Gate-to-Source Voltage
± 20
V
GS
T
J
Operating Junction and
-55 to
+ 150
°C
Storage Temperature Range
T
STG
Avalanche Characteristics
Single Pulse Avalanche Energy
Single Pulse Avalanche Energy
Avalanche Current
E
AS (Thermally limited)
78
152
mJ
E
AS (Thermally limited)
I
AR
See Fig. 14, 15, 22a, 22b
A
Repetitive Avalanche Energy
E
AR
mJ
Thermal Resistance
Symbol
Parameter
Junction-to-Case
Typ.
–––
–––
–––
–––
Max.
1.6
Units
R
θ
JC
(Bottom)
R
θ
JC
(Top)
Junction-to-Case
31
35
23
°C/W
Junction-to-Ambient
Junction-to-Ambient
R
θ
JA
R
θ
JA
(<10s)
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
Parameter
Min. Typ.
Max.
40 –––
–––
––– 0.032 –––
Units
V
Conditions
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
V
GS
= 0V, I
D
= 250µA
Reference to 25°C, I
D
= 1.0mA
V
GS
= 10V, I
D
= 50A
V
/ T
∆
V/°C
∆
(BR)DSS
J
m
R
DS(on)
–––
–––
2.2
2.5
3.8
3.3
–––
3.9
Ω
m
V
GS
= 6.0V, I
D
= 50A
V
DS
= V
GS
, I
D
= 100µA
V
DS
= 40V, V
GS
= 0V
Ω
V
GS(th)
I
DSS
Gate Threshold Voltage
–––
–––
–––
–––
–––
1.5
V
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
1.0
µA
150
100
-100
–––
V
DS
= 40V, V
GS
= 0V, T
J
= 125°C
GS
= 20V
V
GS
= -20V
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
nA
V
R
G
Ω
Notes:
Calculated continuous current based on maximum allowable
junction temperature. Current is limited to 85A by source bond
technology. Note that current limitations arising from heating of
ꢀ
Pulse width
≤
400µs; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
the device leads may occur with some lead mounting
arrangements
.
(Refe
r
t
o
A
N-1140)
.
Repetitive rating;
pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.062mH
R
G
= 50
Ω
, I
AS
= 50A, V
GS
=10V.
When mounted on 1 inch square 2 oz copper pad on 1.5 x 1.5 in. board of
FR-4 material.
R
θ
is measured at T
J
approximately 90°C.
Limited by T
Jmax
, starting T
J
= 25°C, L = 1mH,
R
G
= 50
Ω
, I
AS
= 18A,V
GS
=10V
I
SD
≤
50A, di/dt
≤
1123A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
150°C.
A
ugust 28, 2015
2
IRFH7446PbF
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ.
Max.
Units
S
Conditions
gfs
Q
g
159
–––
–––
–––
–––
–––
–––
–––
–––
–––
65
16
23
42
11
37
33
26
–––
98
V
DS
= 10V, I
D
= 50A
nC
I
D
= 50A
Q
gs
Q
gd
Q
sync
t
d(on)
t
r
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Total Gate Charge Sync. (Q
g
– Q
gd
)
Turn-On Delay Time
–––
–––
–––
–––
–––
–––
–––
V
DS
=20V
V
GS
= 10V
I
D
= 50A, V
DS
= 20V, V
GS
= 10V
V
DD
= 20V
ns
Rise Time
I
D
= 30A
t
d(off)
t
f
Turn-Off Delay Time
R =
2.7
Ω
G
Fall Time
V
GS
= 10V
V
GS
= 0V
V
DS
= 25V
C
iss
C
oss
C
rss
Input Capacitance
––– 3174 –––
pF
Output Capacitance
–––
–––
–––
–––
479
332
637
656
–––
–––
–––
–––
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
ƒ = 1.0 MHz
C
oss
eff. (ER)
oss
eff. (TR)
V
GS
= 0V, V
DS
= 0V to 32V
V
GS
= 0V, V
DS
= 0V to 32V
C
Diode Characteristics
Symbol
Parameter
Min. Typ.
Max.
Units
Conditions
85
I
S
Continuous Source Current
–––
–––
A
MOSFET symbol
D
S
(Body Diode)
showing the
G
I
SM
Pulsed Source Current
–––
–––
468
A
integral reverse
(Body Diode)
p-n junction diode.
V
SD
dv/dt
t
rr
Diode Forward Voltage
Peak Diode Recovery
–––
–––
–––
–––
–––
–––
–––
0.9
2.6
16
1.3
–––
–––
–––
–––
–––
–––
V
T
J
= 25°C, I
S
= 50A, V
GS
= 0V
T
J
= 150°C, I
S
= 50A, V
DS
= 40V
V/ns
ns
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
V
R
= 34V,
18
I
F
= 50A
di/dt = 100A/µs
Q
rr
5.0
6.9
0.50
nC
A
I
RRM
3
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© 2015 International Rectifier
IRFH7446PbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
4.5V
60µs PULSE WIDTH
Tj = 150°C
≤
60µs PULSE WIDTH
Tj = 25°C
≤
1
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 3.
Typical Output Characteristics
Fig 4.
Typical Output Characteristics
1000
100
10
1.8
I
= 50A
D
V
= 10V
GS
1.6
1.4
1.2
1.0
0.8
0.6
T
= 150°C
J
T
= 25°C
J
V
= 10V
DS
≤
60µs PULSE WIDTH
1.0
3
4
5
6
7
8
-60 -40 -20
0
20 40 60 80
100 12
0
1
40 160
T
J
, Junction Temperature (°C)
V
, Gate-to-Source Voltage (V)
GS
Fig 6.
Normalized On-Resistance vs. Temperature
Fig 5.
Typical Transfer Characteristics
100000
10000
1000
14.0
V
= 0V,
= C
f = 1 MHZ
GS
I =
50A
D
C
C
C
+ C
, C
SHORTED
ds
iss
gs
gd
12.0
= C
rss
oss
gd
= C
+ C
V
V
= 32V
= 20V
DS
DS
ds
gd
10.0
8.0
6.0
4.0
2.0
0.0
C
iss
C
oss
rss
C
100
1
10
, Drain-to-Source Voltage (V)
100
0
10 20 30 40 50 60 70 80 90
V
Q , Total
Gate Charge (nC)
G
DS
Fig 7.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 8.
Typical Gate Charge vs. Gate-to-Source Voltage
A
ugust 28, 2015
4
IRFH7446PbF
1000
100
10
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
100µsec
T
= 150°C
J
1msec
T
= 25°C
J
10msec
DC
1
Tc = 25°C
Tj = 150°C
Single Pulse
V
= 0V
GS
0.1
1.0
0.1
1
10
100
0.0
0.4
0.8
1.2
1.6
2.0
V
, Drain-to-Source Voltage (V)
DS
V
, Source-to-Drain Voltage (V)
SD
Fig 10.
Maximum Safe Operating Area
Fig 9.
Typical Source-Drain Diode
Forward Voltage
0.50
50
48
46
44
42
40
Id = 1.0mA
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-5
0
5
10 15 20 25 30 35 40 45
Drain-to-Source Voltage (V)
-60 -40 -20
0
20 40 60 80
100 12
0
1
40 160
, Temperature ( °C )
T
J
V
DS,
Fig 11.
Drain-to-Source Breakdown Voltage
Fig 12.
Typical C
OSS
Stored Energy
140
120
100
80
V
V
V
V
V
= 5.0V
GS
= 6.0V
= 7.0V
= 8.0V
=10V
GS
GS
GS
GS
60
40
20
0
0
100
200
300
400
500
I ,
Drain Current (A)
D
Fig 13.
Typical On-Resistance vs. Drain Current
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© 2015 International Rectifier
5
IRFH7446PbF
10
1
D = 0.50
0.20
0.10
0.05
0.1
0.02
0.01
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 14.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆
Tj = 125°C and
Tstart =25°C (Single Pulse)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Τ
j = 25°C and
Tstart = 125°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15.
Typical Avalanche Current vs.Pulsewidth
80
70
60
50
40
30
20
10
0
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆
T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche =
t
av
·f
TOP
BOTTOM 1.0%
Duty Cycle
= 50A
Single Pulse
I
D
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
I
av
= 2
D
T/ [1.3·BV·Z
th
]
25
50
75
100
125
150
E
AS (AR)
= P
D (ave)
·t
av
Starting T
, Junction Temperature (°C)
J
Fig 16.
Maximum Avalanche Energy vs. Temperature
A
ugust 28, 2015
6
IRFH7446PbF
4.5
4.0
3.5
3.0
2.5
2.0
1.5
7
6
5
4
3
2
1
0
I =
30A
F
V
= 34V
R
T =
25°C
J
T =
125°C
J
I
I
I
= 100µA
= 1.0mA
= 1.0A
D
D
D
0
200
400
600
800
1000
-75 -50 -25
0
25 50 75
100 125 150
T ,
Temperature ( °C )
di /dt
(A/µs)
F
J
Fig. 18
– Typical Recovery Current vs. di
f
/dt
Fig 17.
Threshold Voltage vs. Temperature
7
100
I =
50A
F
I =
30A
F
6
5
4
3
2
1
0
V
= 34V
V
= 34V
R
R
80
60
40
20
0
T =
25°C
T =
25°C
J
J
T =
125°C
J
T =
125°C
J
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt
(A/µs)
di /dt
(A/µs)
F
F
Fig. 19
– Typical Recovery Current vs. di
f
/dt
Fig. 20
– Typical Stored Charge vs. di
f
/dt
100
I =
50A
F
V
= 34V
R
80
60
40
20
0
T =
25°C
J
T =
125°C
J
0
200
400
600
800
1000
di /dt
(A/µs)
F
Fig. 21
– Typical Stored Charge vs. di
f
/dt
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© 2015 International Rectifier
7
IRFH7446PbF
Driver Gate Drive
P.W.
P
.
W.
Period
D.U.T
Period
D =
+
–
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Current
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 22.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
V
G
S
Ω
0.01
t
p
I
AS
Fig 22b.
Unclamped Inductive Waveforms
Fig 22a.
Unclamped Inductive Test Circuit
R
D
V
DS
V
DS
90%
V
GS
D.U.T.
R
G
+
V
DD
–
V
GS
10%
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a.
Switching Time Test Circuit
Fig 23b.
Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.
T
.
Vds
Vgs
50K
Ω
.2
µ
F
12V
.3
µ
F
+
V
DS
D.U.
T
.
–
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a.
Gate Charge Test Circuit
Fig 24b.
Gate Charge Waveform
A
ugust 28, 2015
8
IRFH7446PbF
PQFN 5×6 Outline “E” Package Details
PQFN 5×6 Outline “G” Package Details
For more information on board mounting, including footprint and stencil recommendation, please refer to
9
www.irf.com
© 2015 International Rectifier
IRFH7446PbF
PQFN 5×6 Part Marking
INTERNATIONAL
RECTIFIER LOGO
DATE CODE
PART NUMBER
XXXX
XYWWX
XXXXX
(“4 or 5 digits”)
ASSEMBLY
SITE CODE
(Per SCOP 200-002)
MARKING CODE
(Per Marking Spec)
PIN 1
IDENTIFIER
LOT CODE
(Eng Mode – Min last 4 digits of EATI#)
(Prod Mode – 4 digits of SPN code)
PQFN 5×6 Tape and Reel
REEL DIMENSIONS
TAPE DIMENSIONS
CODE
Ao
DES CR
I
P
T
I
O
N
Dim
e
ns
i
o
n des
i
g
n to accommodate the component
w
i
d
t
h
Dim
e
ns
i
o
n des
i
g
n to accommodate the component
l
e
nght
Dim
e
ns
i
o
n des
i
g
n
t
o
a
ccommodate the component th
i
c
k
n
ess
O
v
e
r
a
l
l
w
i
d
t
h of the carr
i
e
r
t
ape
Bo
Ko
W
P
1
Pitch between s
ucces s
i
ve
c
av
i
t
y
c
ente
r
s
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
N
o
t
e:
A
ll
d
i
m
ens
i
o
n
are nom
i
n
al
Package
Ty
p
e
R
e
el
Di
a
me
t
e
r
(
I
n
ch)
Q
T
Y
R
e
el
Wi
d
t
h
W1
Ao
Bo
Ko
P1
W
Pin 1
(mm)
(mm)
(
m
m)
(mm)
(
m
m)
Quadrant
(mm)
5 X
6 PQFN
13
4000
12.4
6.300
5.300
1.20
8.00
12
Q1
A
ugust 28, 2015
10
IRFH7446PbF
Qualification information
†
I
n
du
s
t
rial
(per JE
DE C
JE S D47F
guide
l
i
n
es)
††
Qualification le
v
el
MS L1
Moisture Sensiti
v
i
ty Le
v
e
l
RoHS compliant
PQFN 5mm x 6mm
(p
e
r JE
D
E C
J-S
T
D-020D
††
)
Yes
Qualification standards can be found at International Rectifiers web site:
http://www.irf.com/product-info/reliability/
Applicable
version of JEDEC standard at the time of product release.
Revision History
Date
Comment
1/17/2014
Updated ordering information to reflect the End-Of-Life (EOL) of the mini-reel option (EOL notice #259).
Updated E
AS (L =1mH)
= 152mJ on page 2
•
•
•
•
2/19/2015
Updated note 10
“Limited by T
, starting T
= 25°C, L = 1mH, R
= 50
, I
AS
= 18A, V
GS
=10V”. on
page 2
Ω
J G
Jmax
Updated package outline for “option E” and
added package outline for “option G” on page 9.
6/2/2015
•
Updated “IFX” logo on page 1 & 11.
•
Updated tape and reel on page 10.
Corrected package outline for “option E”
on page 9.
Corrected Fig 10 – SOA Curve with Package Limitation = 85A instead of 50A on PW = DC Curve – page 5.
Notes: Number 1 – Corrected from “Current is limited to 71A —” to “Current is limited to 85A —–” – page 2
7/7/2015
8/19/2015
8/28/2015
•
•
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11
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