Infineon-Technologies-IRFI4110GPBF
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IRFI4110GPbF
HEXFET
®
Power MOSFET
Applications
V
DSS
R
DS(on)
typ.
R
DS(on)
max.
I
D
100V
3.7m
4.5m
72A
High Efficiency Synchronous Rectification in SMPS
Uninterruptible Power Supply
High Speed Power Switching
Hard Switched and High Frequency Circuits
Benefits
Improved Gate,
Avalanche and Dynamic dV/dt Ruggedness
Fully Characterized Capacitance and Avalanche SOA
Enhanced body diode dV/dt and dI/dt Capability
Lead-Free
S
D
G
TO-220 Full-Pak
Halogen-Free
G
D
S
Gate
Drain
Source
Standard Pack
Quantity
50
Base Part Number
Package Type
Orderable Part Number
Form
IRFI4110GPbF
TO-220 Full-Pak
Tube
IRFI4110GPbF
Absolute Maximum Ratings
Symbol
Parameter
Max.
Units
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V
72
A
I
D
@ T
C
= 100°C
I
DM
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
51
290
61
P
D
@T
C
= 25°C
Maximum Power Dissipation
Linear Derating Factor
W
W/°C
0.41
V
GS
dv/dt
T
J
Gate-to-Source Voltage
Peak Diode Recovery dv/dt
Operating Junction and
V
V/ns
± 20
27
-55 to
+ 175
T
STG
Storage Temperature Range
°C
Soldering Temperature, for 10 seconds (1.6mm from case)
Mounting torque, 6-32 or M3 screw
300
10 lbf•in (1.1N•m)
Avalanche Characteristics
E
AS
I
AR
Single Pulse Avalanche Energy (Thermally Limited)
mJ
A
71
43
Avalanche Current
E
AR
Repetitive Avalanche Energy
mJ
6.1
Thermal Resistance
Symbol
R
JC
R
JA
Parameter
Typ.
–––
–––
Max.
2.46
65
Units
Junction-to-Case
°C/W
Junction-to-Ambient (PCB Mount)
1
2017-04-27
IRFI4110GPbF
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max.
Units
100 ––– –––
––– 0.11 –––
Conditions
V
(BR)DSS
V
(BR)DSS
/
T
J
R
DS(on)
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
V
V
GS
= 0V, I
D
= 250µA
V/°C Reference
to 25°C, I
D
= 5mA
–––
2.0
––– –––
––– –––
––– –––
3.7
4.5
V
GS
= 10V, I
D
= 43A
m
V
V
GS(th)
–––
4.0
20
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 100 V, V
GS
= 0V
V
DS
= 100V,V
GS
= 0V,T
J
=125°C
GS
= 20V
V
GS
= -20V
I
DSS
I
GSS
Drain-to-Source Leakage Current
µA
nA
250
100
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
V
––– ––– -100
Dynamic @ T
J
= 25°C (unless otherwise specified)
gfs
Q
g
Forward Trans conductance
Total Gate Charge
260 –––
–––
––– 190
290
S
V
DS
= 50V, I
D
= 43A
I
D
= 43A
Q
gs
Q
gd
R
G
t
d(on)
t
r
Gate-to-Source Charge
Gate-to-Drain Charge
Internal Gate Resistance
Turn-On Delay Time
Rise Time
–––
–––
–––
–––
–––
–––
–––
40 ––– nC
V
DS
= 50V
V
GS
= 10V
49 –––
1.3 –––
24 –––
58 –––
81 –––
71 –––
V
DD
= 65V
I
D
= 43A
R
G
= 2.6
ns
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
V
GS
= 10V
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
––– 9540
–––
––– 680
–––
––– 300
–––
V
GS
= 0V
V
DS
= 50V
ƒ = 1.0MHz
pF
C
oss eff. (ER)
Effective Output Capacitance (Energy Related)
––– 760
–––
V
GS
=0V,V
DS
= 0V to 80V
V
GS
= 0V, V
DS
= 0V to 80V
C
oss eff. (TR)
Effective Output Capacitance (Time Related)
––– 1120
–––
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max.
Units
Conditions
MOSFET symbol
showing the
integral reverse
p-n junction diode.
Continuous Source Current
(Body Diode)
I
S
––– –––
72
A
Pulsed Source Current
(Body Diode)
I
SM
––– –––
––– –––
290
V
SD
t
rr
Diode Forward Voltage
1.3
75
V
T
J
= 25°C,I
S
= 43A,V
GS
= 0V
–––
–––
50
60
T
J
= 25°C
Reverse Recovery Time
ns
90
T
J
= 125°C
V
R
= 85V
––– 100
––– 140
150
210
T
J
= 25°C
I
F
= 43A
Q
rr
Reverse Recovery Charge
nC
T
J
= 125°C
di/dt= 100A/µs
I
RRM
t
on
Reverse Recovery Current
Forward Turn-On Time
–––
3.5
–––
A
T
J
= 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Notes:
Repetitive rating;
pulse width limited by max. junction temperature. (See fig. 11)
Limited by T
Jmax
, starting
T
J
= 25°C, L = 0.077mH, R
G
= 50
, I
AS
= 43A, V
GS
=10V. Part not recommended for use above this value.
I
SD
43A, di/dt
1600A/µs, V
DD
V
(BR)DSS
, T
J
175°C.
Pulse width
400µs; duty cycle
2%.
C
oss eff.
(TR) is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss eff.
(ER) is a fixed capacitance that gives the same energy as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
When mounted on 1″ square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to application
note #AN-994.
R
is measured at T
J
approximately 90°C.
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2017-04-27
IRFI4110GPbF
1000
100
10
1000
100
10
VGS
15V
10V
5.5V
5.0V
4.7V
4.5V
4.2V
4.0V
VGS
15V
10V
5.5V
5.0V
4.7V
4.5V
4.2V
4.0V
60µs PULSE WIDTH
Tj = 175°C
60µs PULSE WIDTH
Tj = 25°C
TOP
TOP
BOTTOM
BOTTOM
4.0V
4.0V
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig. 2
Typical Output Characteristics
Fig. 1
Typical Output Characteristics
1000
100
10
3.0
2.5
2.0
1.5
1.0
0.5
V
= 25V
DS
60µs PULSE WIDTH
I
= 72A
= 10V
D
V
GS
T
= 175°C
J
T
= 25°C
J
1.0
2
3
4
5
6
-60 -40 -20
0 20
40 60 80
10
0
1
2
0
1
4
0
1
6
0
1
80
, Junction Temperature (°C)
V
, Gate-to-Source Voltage (V)
GS
T
J
Fig. 3
Typical Transfer Characteristics
Fig. 4
Normalized On-Resistance vs. Temperature
12.0
100000
10000
1000
V
C
= 0V,
f = 1 MHZ
I =
43A
D
GS
= C
+ C
, C
SHORTED
iss
gs gd
ds
10.0
V
V
= 80V
= 50V
C
= C
gd
DS
DS
rss
C
= C
+ C
oss
ds
gd
8.0
6.0
4.0
2.0
0.0
C
iss
C
C
oss
rss
100
0
40
80
120
160
200
240
1
10
, Drain-to-Source Voltage (V)
100
Q
, Total
Gate Charge (nC)
G
V
DS
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
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IRFI4110GPbF
10000
1000
100
10
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
100µsec
1msec
10msec
T
= 25°C
J
DC
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
GS
= 0V
0.1
1.0
0
1
10
100
1000
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
, Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
V
DS
SD
Fig. 7.
Typical Source-to-Drain Diode Forward Voltage
Fig 8.
Maximum Safe Operating Area
125
80
Id = 5mA
70
60
50
40
30
20
10
0
120
115
110
105
100
95
90
-60 -40 -20
0
T
20 40 60 80
10
0
1
2
0
1
4
0
1
6
0
1
80
, Temperature ( °C )
25
50
75
100
125
150
175
J
T
, Case Temperature (°C)
C
Fig. 9.
Maximum Drain Current vs. Case Temperature
Fig 10.
Drain-to-Source Breakdown Voltage
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
300
I
D
TOP
17A
22A
BOTTOM 43A
250
200
150
100
50
0
-20
0
20
40
60
80
100 120
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
V
Drain-to-Source Voltage (V)
J
DS,
Fig. 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy vs. Drain Current
2017-04-27
4
IRFI4110GPbF
10
1
D = 0.50
0.20
Ri (°C/W)
i (sec)
0.000005
0.000067
0.003980
0.228341
3.049000
0.10
0.05
0.0371
0.1159
0.2585
0.9745
1.0740
0.1
0.02
0.01
SINGLE PULSE
( THERMAL RESPONSE )
0.01
0.001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t
, Rectangular Pulse Duration (sec)
1
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
Tstart =25°C (Single Pulse)
Tj = 150°C and
100
0.01
10
1
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
Tstart = 150°C.
j = 25°C and
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
tav (sec)
1.0E-02
1.0E-01
1.0E+00
Fig 14.
Single Avalanche Event: Pulse Current vs. Pulse Width
80
70
60
50
40
30
20
10
0
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.infineon.com)
1.Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
T = Allowable rise in junction temperature, not to exceed T
jmax
(assumed as 25°C in Figure 14, 15).
t
av
= Average time in avalanche.
D = Duty cycle in avalanche =
tav ·f
TOP
BOTTOM 1.0%
Duty Cycle
= 43A
Single Pulse
I
D
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
I
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
T/ Z
thJC
av
= 2
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)· av
25
50
75
100
125
150
175
t
Starting T
, Junction Temperature (°C)
J
Fig 15.
Maximum Avalanche Energy vs. Temperature
5
2017-04-27
IRFI4110GPbF
4.0
3.5
3.0
2.5
2.0
1.5
1.0
25
20
15
10
5
I
= 29A
F
V
= 85V
R
T =
25°C
J
T =
125°C
J
I
I
I
= 250µA
= 1.0mA
= 1.0A
D
D
D
0
-75 -50 -25
0
25 50 75
100 125 150 175 200
, Temperature ( °C )
0
200
400
600
800
1000
T
di /dt
(A/µs)
J
F
Fig 16.
Threshold Voltage vs. Temperature
Fig 17.
Typical Recovery Current vs. dif/dt
30
1400
I
= 43A
F
I
= 29A
= 85V
F
V
= 85V
R
1200
1000
800
600
400
200
0
V
25
20
15
10
5
R
T =
25°C
J
T =
125°C
J
T =
25°C
J
T =
125°C
J
0
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt
(A/µs)
di /dt
(A/µs)
F
F
Fig 18.
Typical Recovery Current vs. dif/dt
Fig 19.
Typical Stored Charge vs. dif/dt
1600
I
= 43A
= 85V
F
1400
1200
1000
800
600
400
200
0
V
R
T =
25°C
J
T =
125°C
J
0
200
400
600
800
1000
di /dt
(A/µs)
F
Fig 20.
Typical Stored Charge vs. dif/dt
6
2017-04-27
IRFI4110GPbF
Fig 21.
Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
20V
t
0.01
I
AS
p
Fig 22a.
Unclamped Inductive Test Circuit
Fig 22b.
Unclamped Inductive Waveforms
Fig 23a.
Switching Time Test Circuit
Fig 23b.
Switching Time Waveforms
Id
Vds
Vgs
Vgs(th)
Qgs1
Qgs2
Qgd
Qgodr
Fig 24a.
Gate Charge Test Circuit
Fig 24b.
Gate Charge Waveform
7
2017-04-27
IRFI4110GPbF
TO-220 Full-Pak Package Outline
(Dimensions are shown in millimeters (inches))
TO-220 Full-Pak Part Marking Information
TO-220AB Full-Pak
packages are not recommended for Surface Mount Application.
8
2017-04-27
IRFI4110GPbF
Qualification Information
Qualification Level
Industrial
(per JEDEC JESD47F)
†
TO-220 Full-Pak
N/A
Yes
Moisture Sensitivity Level
RoHS Compliant
†
Applicable version of JEDEC standard at the time of product release.
Revision History
Date
Comments
Changed datasheet with Infineon logo – all pages.
Corrected Package Outline on page 8.
Corrected fig 19 & 20 –Y axis title from “A” to “nC” on page 6.
Added disclaimer on last page.
04/27/2017
Trademarks of Infineon Technologies AG
µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™,
CoolSiC™, DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™,
GaNpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™,
OPTIGA™, OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID
FLASH™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™
Trademarks updated November 2015
Other Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
Edition 2016-04-19
Published by
Infineon Technologies AG
81726 Munich, Germany
For further information on the product, technology,
delivery terms and conditions and prices please
contact your nearest Infineon Technologies o
ff
ice
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Bescha
ff
enheitsgarantie”) .
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
Please note that this product is not qualified
according to the AEC Q100 or AEC Q101 documents
of the Automotive Electronics Council.
© 2016 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about this
document?
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Due to technical requirements products may
In addition, any information given in this
contain dangerous substances. For information on
document
is subject to customer’s compliance
the types in question please contact your nearest
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obligations stated in this document and
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ff
ice.
any applicable legal requirements, norms and
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Except as otherwise explicitly approved by Infineon
any use of the product of Infineon Technologies in
Technologies in a written document signed by
customer’s applications.
Document reference
ifx1
authorized
representatives
of
Infineon
Technologies,
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may
not be used in any applications where a
failure of the product or any consequences of the
use thereof can reasonably be expected to result in
personal injury.
The data contained in this document is exclusively
intended for technically trained sta
ff
. It is the
responsibility
of
customer’s
technical
departments
to evaluate the suitability of the
product for the intended application and the
completeness of the product information given in
this document with respect to such application.
9
2017-04-27
