Infineon-Technologies-IRFI7536GPBF
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IRFI7536GPbF
HEXFET
®
Power MOSFET
Applications
V
DSS
R
DS(on)
typ.
R
DS(on)
max.
I
D
60V
High Efficiency Synchronous Rectification in SMPS
Uninterruptible Power Supply
High Speed Power Switching
2.7m
3.4m
86A
Hard Switched and High Frequency Circuits
Benefits
Improved Gate,
Avalanche and Dynamic dV/dt Ruggedness
Fully Characterized Capacitance and Avalanche SOA
Enhanced body diode dV/dt and dI/dt Capability
Lead-Free
S
D
G
TO-220 Full-Pak
G
D
S
Gate
Drain
Source
Standard Pack
Quantity
50
Base Part Number
Package Type
Orderable Part Number
Form
IRFI7536GPbF
TO-220 Full-Pak
Tube
IRFI7536GPbF
Absolute Maximum Ratings
Symbol
Parameter
Max.
Units
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V
86
A
I
D
@ T
C
= 100°C
I
DM
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
73
820
75
P
D
@T
C
= 25°C
Maximum Power Dissipation
Linear Derating Factor
W
W/°C
V
0.5
V
GS
T
J
Gate-to-Source Voltage
Operating Junction and
Storage Temperature Range
± 20
-55 to
+ 175
T
STG
°C
Soldering Temperature, for 10 seconds (1.6mm from case)
Mounting torque, 6-32 or M3 screw
300
10 lbf•in (1.1N•m)
Avalanche Characteristics
E
AS
I
AR
Single Pulse Avalanche Energy (Thermally Limited)
738
mJ
A
Avalanche Current
See Fig. 14, 15, 22a, 22b
E
AR
Repetitive Avalanche Energy
mJ
Thermal Resistance
Symbol
R
JC
R
JA
Parameter
Typ.
–––
–––
Max.
2.87
65
Units
Junction-to-Case
°C/W
Junction-to-Ambient (PCB Mount)
1
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IRFI7536PbF
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max.
Units
Conditions
V
(BR)DSS
V
(BR)DSS
/
T
J
R
DS(on)
V
GS(th)
gfs
R
G
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Trans conductance
Internal Gate Resistance
60
–––
–––
2.0
88
–––
29
–––
V
V
GS
= 0V, I
D
= 250µA
––– mV/°C
Reference to 25°C, I
D
= 1mA
2.7
–––
–––
3.4
4.0
–––
V
GS
= 10V, I
D
= 75A
V
DS
= V
GS
, I
D
= 150µA
V
DS
= 25V, I
D
= 75A
m
V
S
––– 0.79 –––
––– –––
––– –––
––– –––
20
250
100
V
DS
= 60 V, V
GS
= 0V
V
DS
= 60V,V
GS
= 0V,T
J
=125°C
GS
= 20V
V
GS
= -20V
I
DSS
I
GSS
Drain-to-Source Leakage Current
µA
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
V
nA
––– ––– -100
Dynamic @ T
J
= 25°C (unless otherwise specified)
Q
g
Total Gate Charge
––– 130
195
I
D
= 75A
V
DS
= 30V
Q
gs
Q
gd
Q
sync
t
d(on)
t
r
Gate-to-Source Charge
Gate-to-Drain Charge
Total Gate Charge Sync. (Qg – Qgd)
Turn-On Delay Time
Rise Time
–––
–––
–––
–––
–––
–––
–––
31 –––
42 –––
88 –––
22 –––
77 –––
55 –––
64 –––
nC
ns
V
GS
= 10V
V
DD
= 39V
I
D
= 75A
R
G
= 2.7
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
V
GS
= 10V
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
––– 6600
–––
––– 720
–––
––– 400
–––
V
GS
= 0V
V
DS
= 48V
ƒ = 1.0MHz, See Fig. 5
pF
C
oss eff. (ER)
Effective Output Capacitance (Energy Related)
––– 1080
–––
V
GS
=0V,V
DS
= 0V to 48V See Fig.11
V
GS
= 0V, V
DS
= 0V to 48V
C
oss eff. (TR)
Effective Output Capacitance (Time Related)
––– 1400
–––
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max.
Units
Conditions
MOSFET symbol
showing the
integral reverse
p-n junction diode.
Continuous Source Current
(Body Diode)
I
S
––– –––
86
A
Pulsed Source Current
(Body Diode)
I
SM
––– –––
––– –––
820
1.3
V
SD
Diode Forward Voltage
V
T
J
= 25°C,I
S
= 75A,V
GS
= 0V
dv/dt
Peak Diode Recovery dv/dt
–––
–––
3.3
43
––– V/ns
T
J
= 25°C, I
S
= 75A, V
DS
= 60V
–––
T
J
= 25°C
V
R
= 51V
t
rr
Reverse Recovery Time
ns
53
58
65
–––
–––
–––
T
J
= 125°C
T
J
= 25°C
T
J
= 125°C
I
F
=75A
–––
–––
–––
Q
rr
Reverse Recovery Charge
Reverse Recovery Current
nC
di/dt= 100A/µs
I
RRM
2.4
–––
A
T
J
= 25°C
Notes:
Repetitive rating;
pulse width limited by max. junction temperature. (See fig. 11)
Limited by T
Jmax
, starting
T
J
= 25°C, L = 0.26mH, R
G
= 50
, I
AS
= 75A, V
GS
=10V. Part not recommended for use above this value.
I
SD
75A, di/dt
890A/µs, V
DD
V
(BR)DSS
, T
J
175°C.
Pulse width
400µs; duty cycle
2%.
C
oss eff.
(TR) is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss eff.
(ER) is a fixed capacitance that gives the same energy as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
R
is measured at T
J
approximately 90°C.
R
JC
value shown is at time zero.
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IRFI7536PbF
1000
100
10
1000
100
10
VGS
15V
12V
VGS
15V
12V
TOP
TOP
10V
10V
6.0V
5.0V
4.75V
4.50V
4.25V
6.0V
5.0V
4.75V
4.50V
4.25V
BOTTOM
BOTTOM
4.25V
4.25V
60µs PULSE WIDTH
Tj = 175°C
60µs PULSE WIDTH
Tj = 25°C
1
1
0.01
0.1
1
10
100
0.01
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig. 2
Typical Output Characteristics
Fig. 1
Typical Output Characteristics
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
1000
100
10
I
= 75A
= 10V
D
V
GS
T
= 175°C
J
T
= 25°C
= 25V
J
V
DS
60µs PULSE WIDTH
1.0
2
3
4
5
6
7
-60 -40 -20
T
0
20 40 60 80
10
0
1
2
0
1
4
0
1
6
0
1
80
, Junction Temperature (°C)
V
, Gate-to-Source Voltage (V)
J
GS
Fig. 3
Typical Transfer Characteristics
Fig. 4
Normalized On-Resistance vs. Temperature
100000
10000
1000
14.0
V
= 0V,
= C
f = 1 MHZ
GS
I
= 75A
C
C
C
+ C
, C
SHORTED
D
iss
gs
gd
ds
12.0
10.0
8.0
= C
rss
oss
gd
= C
+ C
V
V
V
= 48V
= 30V
= 12V
DS
DS
DS
ds
gd
C
iss
C
oss
6.0
C
rss
4.0
2.0
100
0.0
1
10
, Drain-to-Source Voltage (V)
100
0
20 40 60 80
100 120 140 160 180
V
Q , Total
Gate Charge (nC)
G
DS
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
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IRFI7536PbF
1000
100
10
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
100µsec
T
= 175°C
J
1msec
10msec
DC
T
= 25°C
J
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
2.5
GS
1.0
0.1
0.0
0.5
1.0
1.5
2.0
3.0
0.1
1
10
100
V
, Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig. 7.
Typical Source-to-Drain Diode Forward Voltage
Fig 8.
Maximum Safe Operating Area
100
72
70
68
66
64
62
60
I
= 1.0mA
D
80
60
40
20
0
-60 -40 -20
0
20 40 60 80
10
0
1
2
0
1
4
0
1
6
0
1
80
, Temperature ( °C )
25
50
75
100
125
150
175
T
J
T
, Case Temperature (°C)
C
Fig. 9.
Maximum Drain Current vs. Case Temperature
Fig 10.
Drain-to-Source Breakdown Voltage
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
3000
I
D
TOP
8.6A
12A
BOTTOM 75A
2500
2000
1500
1000
500
0
0
10
20
30
40
50
60
70
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
V
Drain-to-Source Voltage (V)
J
DS,
Fig. 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy vs. Drain Current
2017-04-27
4
IRFI7536PbF
10
1
D = 0.50
0.20
0.10
0.05
0.1
0.02
0.01
0.01
0.001
0.0001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t
, Rectangular Pulse Duration (sec)
1
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
Tj = 150°C and
Tstart =25°C (Single Pulse)
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
tav (sec)
1.0E-02
1.0E-01
1.0E+00
Fig 14.
Single Avalanche Event: Pulse Current vs. Pulse Width
800
700
600
500
400
300
200
100
0
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.infineon.com)
1.Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
T = Allowable rise in junction temperature, not to exceed T
jmax
(assumed as 25°C in Figure 14, 15).
t
av
= Average time in avalanche.
D = Duty cycle in avalanche =
tav ·f
TOP
BOTTOM 1.0%
Duty Cycle
= 75A
Single Pulse
I
D
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
I
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
T/ Z
thJC
av
= 2
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)· av
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
t
J
Fig 15.
Maximum Avalanche Energy vs. Temperature
5
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IRFI7536PbF
16
14
12
10
8
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
I
= 30A
F
V
= 51V
R
T =
25°C
J
T =
125°C
J
I
I
I
= 150µA
= 1.0mA
= 1.0A
D
D
D
6
4
2
0
200
400
600
800
1000
-75
-25
25
75
125
175
di /dt
(A/µs)
T
J
, Temperature ( °C )
F
Fig 16.
Threshold Voltage vs. Temperature
Fig 17.
Typical Recovery Current vs. dif/dt
500
16
I
= 30A
= 51V
I
= 45A
F
F
V
14
12
10
8
V
= 51V
R
R
400
300
200
100
0
T =
25°C
J
T =
125°C
J
T =
25°C
J
T =
125°C
J
6
4
2
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt
(A/µs)
di /dt
(A/µs)
F
F
Fig 18.
Typical Recovery Current vs. dif/dt
Fig 19.
Typical Stored Charge vs. dif/dt
500
I
= 45A
F
V
= 51V
R
400
300
200
100
0
T =
25°C
J
T =
125°C
J
0
200
400
600
800
1000
di /dt
(A/µs)
F
Fig 20.
Typical Stored Charge vs. dif/dt
6
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IRFI7536PbF
Fig 21.
Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
20V
t
0.01
I
AS
p
Fig 22a.
Unclamped Inductive Test Circuit
Fig 22b.
Unclamped Inductive Waveforms
Fig 23a.
Switching Time Test Circuit
Fig 23b.
Switching Time Waveforms
Id
Vds
Vgs
Vgs(th)
Qgs1
Qgs2
Qgd
Qgodr
Fig 24a.
Gate Charge Test Circuit
Fig 24b.
Gate Charge Waveform
7
2017-04-27
IRFI7536PbF
TO-220 Full-Pak Package Outline
(Dimensions are shown in millimeters (inches))
TO-220 Full-Pak Part Marking Information
TO-220AB Full-Pak
packages are not recommended for Surface Mount Application.
8
2017-04-27
IRFI7536PbF
Qualification Information
Qualification Level
Industrial
(per JEDEC JESD47F)
†
TO-220 Full-Pak
N/A
Yes
Moisture Sensitivity Level
RoHS Compliant
†
Applicable version of JEDEC standard at the time of product release.
Revision History
Date
Comments
Changed datasheet with Infineon logo – all pages.
Corrected Package Outline on page 8.
Corrected Qual level from “TSOP-6” to “TO-220 Full-Pak” on page 9.
Added disclaimer on last page.
04/27/2017
Trademarks of Infineon Technologies AG
µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™,
CoolSiC™, DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™,
GaNpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™,
OPTIGA™, OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID
FLASH™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™
Trademarks updated November 2015
Other Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
Edition 2016-04-19
Published by
Infineon Technologies AG
81726 Munich, Germany
For further information on the product, technology,
delivery terms and conditions and prices please
contact your nearest Infineon Technologies o
ff
ice
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Bescha
ff
enheitsgarantie”) .
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
Please note that this product is not qualified
according to the AEC Q100 or AEC Q101 documents
of the Automotive Electronics Council.
© 2016 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about this
document?
WARNINGS
Due to technical requirements products may
In addition, any information given in this
contain dangerous substances. For information on
document
is subject to customer’s compliance
the types in question please contact your nearest
with its
obligations stated in this document and
Infineon Technologies o
ff
ice.
any applicable legal requirements, norms and
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ifx1
standards concerning customer’s products and
Except as otherwise explicitly approved by Infineon
any use of the product of Infineon Technologies in
Technologies in
a written document signed by
customer’s applications.
authorized
representatives
of
Infineon
Technologies,
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The data contained in this document is exclusively
may
not be used in any applications where
a
intended for technically trained sta
ff
. It is the
failure of the product or any consequences of the
use thereof can reasonably be expected to result in
personal injury.
responsibility
of
customer’s
technical
departments
to evaluate the suitability of the
product for the intended application and the
completeness of the product information given in
this document with respect to such application.
9
2017-04-27
