Infineon-Technologies-IRFP4310ZPBF
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PD –
97123A
IRFP4310ZPbF
HEXFET
®
Power MOSFET
Applications
D
V
DSS
R
DS(on)
typ.
100V
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
4.8m
6.0m
:
:
max.
G
I
D
I
D
134A
c
(Silicon Limited)
120A
S
(Package Limited)
Benefits
l
Improved Gate,
Avalanche and Dynamic
dV/dt
D
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
S
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
D
G
TO-247AC
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
D
@ T
C
= 25°C
I
DM
Parameter
Max.
134
c
95
Units
A
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Wire Bond Limited)
Pulsed Drain Current
d
120
560
P
D
@T
C
= 25°C
280
Maximum Power Dissipation
W
1.9
Linear Derating Factor
W/°C
V
V
GS
± 20
Gate-to-Source Voltage
18
Peak Diode Recovery
f
dv/dt
T
J
V/ns
°C
-55 to
+ 175
Operating Junction and
T
STG
Storage Temperature Range
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
10lb
x
in (1.1N
x
m)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy
e
E
AS (Thermally limited)
130
mJ
A
Avalanche Current
ꢀd
I
AR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy
g
E
AR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.54
–––
40
Units
R
θ
JC
R
θ
CS
R
θ
JA
Junction-to-Case
j
Case-to-Sink, Flat Greased Surface
0.24
–––
°C/W
Junction-to-Ambient
j
1
3/8/08
IRFP4310ZPbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
Parameter
Min. Typ. Max.
Units
100 ––– –––
––– 0.11 ––– V/°C
Reference to 25°C, I
D
= 5mA
d
Conditions
V
GS
= 0V, I
D
= 250
μ
A
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
V
Δ
V
(BR)DSS
/
Δ
T
J
R
DS(on)
–––
2.0
4.8
6.0
4.0
20
V
GS
= 10V, I
D
= 75A
g
V
DS
= V
GS
, I
D
= 150
μ
A
m
Ω
V
V
GS(th)
–––
I
DSS
Drain-to-Source Leakage Current
––– –––
μ
A V
DS
= 100V, V
GS
= 0V
V
DS
= 80V, V
GS
= 0V, T
J
= 125°C
nA V
GS
= 20V
––– ––– 250
––– ––– 100
––– ––– -100
I
GSS
R
G
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
V
GS
= -20V
–––
0.7
–––
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max.
Units
Conditions
V
DS
= 50V, I
D
= 75A
150 ––– –––
S
Q
g
––– 120 170
nC I
D
= 75A
V
DS
=50V
Q
gs
Gate-to-Source Charge
–––
–––
–––
–––
–––
–––
–––
29
35
85
20
60
55
57
–––
Q
gd
Gate-to-Drain (“Miller”) Charge
Total Gate Charge Sync. (Q
g
– Q
gd
)
Turn-On Delay Time
V
GS
= 10V
g
I
D
= 75A, V
DS
=0V, V
GS
= 10V
ns V
DD
= 65V
Q
sync
–––
–––
–––
–––
–––
t
d(on)
t
r
Rise Time
I
D
= 75A
t
d(off)
Turn-Off Delay Time
R
G
= 2.7
Ω
V
GS
= 10V
g
t
f
Fall Time
C
iss
Input Capacitance
––– 6860 –––
––– 490 –––
––– 220 –––
––– 570 –––
––– 920 –––
pF V
GS
= 0V
C
oss
Output Capacitance
V
DS
= 50V
C
rss
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
h
ƒ = 1.0MHz,
See Fig. 5
C
oss
eff. (ER)
C
oss
eff. (TR)
V
GS
= 0V, V
DS
= 0V to 80V
i
, See Fig. 11
V
GS
= 0V, V
DS
= 0V to 80V
h
Diode Characteristics
Symbol
Parameter
Min. Typ. Max.
Units
Conditions
I
S
Continuous Source Current
––– –––
A
MOSFET symbol
134
c
D
(Body Diode)
showing the
I
SM
Pulsed Source Current
––– ––– 560
A
integral reverse
G
(Body Diode)
ꢀ
d
p-n junction diode.
S
V
SD
t
rr
Diode Forward Voltage
––– –––
1.3
V
T
J
= 25°C, I
S
= 75A, V
GS
= 0V
g
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
V
R
= 85V,
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
–––
–––
–––
40
49
58
89
2.5
ns
I
F
= 75A
di/dt = 100A/
μ
s
g
Q
rr
nC
A
I
RRM
t
on
Reverse Recovery Current
Forward Turn-On Time
–––
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
ꢁ
Pulse width
≤
400
μ
s; duty cycle
≤
2%.
temperature. Bond wire current limit is 120A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
Repetitive rating;
pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.047mH
C
oss
while V
DS
is rising from 0 to 80% V
DSS
R
θ
is measured at T
J
approximately 90°C
.
R
G
= 25
Ω
, I
AS
= 75A, V
GS
=10V. Part not recommended for use
above the Eas value and test conditions.
I
SD
≤
75A, di/dt
≤
600A/
μ
s, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
2
IRFP4310ZPbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
4.5V
≤
60
μ
s PULSE WIDTH
Tj = 25°C
≤
60
μ
s PULSE WIDTH
Tj = 175°C
1
0.1
1
10
100
0.1
1
10
, Drain-to-Source Voltage (V)
DS
100
V
, Drain-to-Source Voltage (V)
V
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
2.5
2.0
1.5
1.0
0.5
1000
100
10
I
= 75A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
= 50V
J
1
V
DS
≤
60
μ
s PULSE WIDTH
0.1
2.0
3.0
V
4.0
5.0
6.0
7.0
8.0
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
, Gate-to-Source Voltage (V)
GS
T
, Junction Temperature (°C)
J
Fig 4.
Normalized On-Resistance vs. Temperature
Fig 3.
Typical Transfer Characteristics
12000
10000
8000
6000
4000
2000
0
20
V
C
= 0V,
f = 1 MHZ
I =
75A
D
GS
= C
+ C
, C
SHORTED
iss
gs
gd ds
V
= 80V
DS
C
= C
rss
gd
16
12
8
VDS= 50V
VDS= 20V
C
= C
+ C
oss
ds
gd
Ciss
4
Coss
Crss
0
0
40
80
120
160
200
1
10
100
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFP4310ZPbF
1000
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
100
10
1
1msec
100
μ
sec
T
= 25°C
J
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
DC
0.1
0.1
0.1
1
10
100
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
, Source-to-Drain Voltage (V)
V
, Drain-toSource Voltage (V)
V
DS
SD
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
130
120
110
100
90
140
120
100
80
I
= 5mA
LIMITED BY PACKAGE
D
60
40
20
0
25
50
75
100
125
150
175
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
T ,
Case Temperature (°C)
C
T
, Junction Temperature (°C)
J
Fig 9.
Maximum Drain Current vs.
Fig 10.
Drain-to-Source Breakdown Voltage
Case Temperature
3.0
2.5
2.0
1.5
1.0
0.5
0.0
600
I
D
TOP
11A
19A
75A
500
400
300
200
100
0
BOTTOM
0
20
40
60
80
100
25
50
75
100
125
150
175
V
Drain-to-Source Voltage (V)
Starting T
, Junction Temperature (°C)
J
DS,
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy Vs. DrainCurrent
4
IRFP4310ZPbF
1
D = 0.50
0.20
0.10
0.1
R
1
R
2
R
3
R
4
τι
(sec)
Ri (°C/W)
R
1
R
2
R
3
R
4
0.05
τ
J
0.01688 0.000007
τ
C
τ
J
τ
0.02
0.01
0.143482 0.000117
0.288653 0.001817
0.091153 0.011735
τ
1
τ
2
τ
1
τ
3
τ
4
τ
3
τ
4
τ
2
0.01
Ci=
τ
i
/
Ri
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
Δ
Tj = 150°C and
Tstart =25°C (Single Pulse)
Duty Cycle = Single Pulse
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
ΔΤ
j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
140
120
100
80
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
TOP
BOTTOM 1%
Duty Cycle
= 75A
Single Pulse
I
D
60
6. I
av
= Allowable avalanche current.
7.
Δ
T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14).
40
t
av =
Average time in avalanche.
D = Duty cycle in avalanche =
t
av
·f
20
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
0
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
25
50
75
100
125
150
175
I
av
= 2
D
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Starting T
, Junction Temperature (°C)
J
Fig 15.
Maximum Avalanche Energy vs. Temperature
5
IRFP4310ZPbF
4.5
4.0
3.5
3.0
2.5
2.0
1.5
24
20
16
12
8
I
I
I
= 1.0A
D
D
D
= 1.0mA
= 250
μ
A
ID = 150
μ
A
I
= 30A
= 85V
F
V
R
4
T
= 125°C
= 25°C
J
T
J
1.0
0
-75 -50 -25
0
25 50 75
100 125 150 175
, Temperature ( °C )
100 200 300 400 500 600 700 800 900
1000
T
di /
dt – (A /
μ
s)
J
f
Fig. 17
– Typical Recovery Current vs. di
f
/dt
Fig 16.
Threshold Voltage Vs. Temperature
600
500
400
300
200
24
20
16
12
8
I
= 30A
= 85V
I
= 45A
= 85V
F
F
V
T
V
T
R
R
100
0
4
0
= 125°C
= 25°C
= 125°C
= 25°C
J
J
T
T
J
J
100 200 300 400 500 600 700 800 900
1000
100 200 300 400 500 600 700 800 900
1000
di /
dt – (A /
μ
s)
di /
dt – (A /
μ
s)
f
f
Fig. 18
– Typical Recovery Current vs. di
f
/dt
Fig. 19
– Typical Stored Charge vs. di
f
/dt
600
500
400
300
200
100
0
I
= 45A
F
V
= 85V
R
T
= 125°C
= 25°C
J
J
T
100 200 300 400 500 600 700 800 900
1000
di /
dt – (A /
μ
s)
f
Fig. 20
– Typical Stored Charge vs. di
f
/dt
6
IRFP4310ZPbF
Driver Gate Drive
P.W.
P
.
W.
Period
Period
D =
D.U.T
+
V
***
=10V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
*
V
DD
**
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Curent
I
SD
Ripple
≤
5%
*
Use P-Channel Driver for P-Channel Measurements
**
Reverse Polarity for P-Channel
***
V
GS
= 5V for Logic Level Devices
Fig 21.
Diode Reverse Recovery Test Circuit
for HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
V
20
GS
0.01
Ω
t
p
I
AS
Fig 22b.
Unclamped Inductive Waveforms
Fig 22a.
Unclamped Inductive Test Circuit
R
D
V
DS
V
DS
90%
V
GS
D.U.T.
R
G
+
V
DD
–
10%
V
GS
10V
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
t
d(on)
t
d(off)
t
r
t
f
Fig 23a.
Switching Time Test Circuit
Fig 23b.
Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
0
Vgs(th)
20K
Qgs1
Qgs2
Qgodr
Qgd
Fig 24a.
Gate Charge Test Circuit
Fig 24b.
Gate Charge Waveform
7
IRFP4310ZPbF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
TO-247AC Part Marking Information
EX
A
M
P
LE: THIS
IS
A
N
I
RFPE30
W
I
T
H
A
S
SE
M
B
LY
P
A
R
T
N
U
M
B
ER
IN
T
ER
N
A
T
I
O
NAL
RE
C
T
I
FIER
L
O
GO
L
O
T CODE 5657
IRFPE30
135H
57
A
S
SE
M
B
LED
O
N WW
3
5, 2001
IN
T
H
E
A
S
SE
M
B
LY LI
N
E “H”
56
DA
T
E
C
ODE
YE
A
R 1 =
2
001
W
E
EK
3
5
A
S
SE
M
B
LY
L
O
T CODE
Note: “P” in a
s
s
e
mb
l
y lin
e
p
o
s
i
tion
indicates “
L
e
ad
–
F
r
e
e”
LINE H
TO-247AC packages are not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
8
