Infineon-Technologies-IRFP4368PBF
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PD – 97322
IRFP4368PbF
Applications
l
High Efficiency Synchronous Rectification in
HEXFET
®
Power MOSFET
SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
D
S
V
DSS
R
DS(on)
typ.
max.
I
D (Silicon Limited)
75V
1.46m
Ω
1.85m
Ω
G
350A
c
I
D (Package Limited)
195A
Benefits
l
Improved Gate,
Avalanche and Dynamic
dv/dt Ruggedness
l
Fully Characterized Capacitance and
Avalanche SOA
D
l
Enhanced body diode dV/dt and dI/dt
Capability
S
D
G
TO-247AC
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
Parameter
Max.
350
c
250
c
195
Units
I
D
@ T
C
= 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
I
D
@ T
C
= 100°C
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
A
I
D
@ T
C
= 25°C
I
DM
Continuous Drain Current, V
GS
@ 10V (Wire Bond Limited)
Pulsed Drain Current
d
1280
520
P
D
@T
C
= 25°C
W
Maximum Power Dissipation
Linear Derating Factor
3.4
W/°C
V
V
GS
20
Gate-to-Source Voltage
13
Peak Diode Recovery
f
dv/dt
T
J
V/ns
°C
-55 to
+ 175
Operating Junction and
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
300
10lb
x
in (1.1N
x
m)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy
e
E
AS (Thermally limited)
430
mJ
A
Avalanche Current
ꢀd
I
AR
See Fig. 14, 15, 22a, 22b
Repetitive Avalanche Energy
g
E
AR
mJ
Thermal Resistance
Symbol
Parameter
Junction-to-Case
k
Typ.
–––
Max.
0.29
–––
40
Units
R
θ
JC
R
θ
CS
R
θ
JA
0.24
–––
°C/W
Case-to-Sink, Flat Greased Surface
Junction-to-Ambient
jk
1
06/02/08
IRFP4368PbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Min. Typ. Max.
Units
75 –––
–––
––– 0.077 –––
V/°C Reference
to 25°C, I
D
= 5mA
d
Conditions
V
GS
= 0V, I
D
= 250µA
V
∆
V
(BR)DSS
/
∆
T
J
R
DS(on)
––– 1.46 1.85
V
GS
= 10V, I
D
= 195A
g
m
Ω
V
V
GS(th)
2.0
–––
4.0
20
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 75V, V
GS
= 0V
V
DS
= 75V, V
GS
= 0V, T
J
= 125°C
V
GS
= 20V
V
I
DSS
Drain-to-Source Leakage Current
––– –––
µA
––– ––– 250
––– ––– 100
––– –––
-100
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
nA
GS
= -20V
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max.
Units
Conditions
V
DS
= 50V, I
D
= 195A
650 ––– –––
S
Q
g
––– 380 570
nC I
D
= 195A
V
DS
= 38V
Q
gs
Q
gd
Q
sync
Gate-to-Source Charge
–––
79
–––
Gate-to-Drain (“Miller”) Charge
Total Gate Charge Sync. (Q
g
– Q
gd
)
––– 105 –––
––– 275 –––
V
GS
= 10V
g
I
D
= 195A, V
DS
=0V, V
GS
= 10V
R
G(int)
t
d(on)
–––
Ω
Internal Gate Resistance
Turn-On Delay Time
Rise Time
0.80 –––
43 –––
–––
ns V
DD
= 49V
I
D
= 195A
R
G
= 2.7
Ω
V
GS
= 10V
g
t
r
––– 220 –––
––– 170 –––
––– 260 –––
––– 19230 –––
––– 1670 –––
––– 770 –––
––– 1700 –––
––– 1410 –––
t
d(off)
Turn-Off Delay Time
Fall Time
t
f
C
iss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
pF
V
GS
= 0V
C
oss
V
DS
= 50V
C
rss
ƒ = 100kHz
C
oss
eff. (ER)
C
oss
eff. (TR)
V
GS
= 0V, V
DS
= 0V to 60V
i
GS
= 0V, V
DS
= 0V to 60V
h
Effective Output Capacitance (Energy Related)
i
V
Effective Output Capacitance (Time Related)
h
Diode Characteristics
Symbol
Parameter
Min. Typ. Max.
Units
Conditions
I
S
Continuous Source Current
––– –––
A
MOSFET symbol
D
S
350
c
(Body Diode)
showing the
integral reverse
G
I
SM
Pulsed Source Current
(Body Diode)
ꢁdi
Diode Forward Voltage
Reverse Recovery Time
––– –––
1280
p-n junction diode.
T
J
= 25°C, I
S
= 195A, V
GS
= 0V
g
V
SD
t
rr
––– ––– 1.3
V
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
V
R
= 64V,
––– 130 200
––– 140 210
––– 450 680
––– 530 800
ns
I
F
= 195A
di/dt = 100A/µs
g
Q
rr
Reverse Recovery Charge
nC
I
RRM
t
on
Reverse Recovery Current
Forward Turn-On Time
–––
9.1
–––
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 195A. Note that current
limitations arising from heating of the device leads may occur with
I
SD
≤
195A, di/dt
≤
1740A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
ꢀ
Pulse width
≤
400µs; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
some lead mounting arrangements. Refer to App Notes (AN-1140).
Repetitive rating;
pulse width limited by max. junction
temperature.
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
When mounted on 1″ square PCB (FR-4 or G-10 Material).
For recom
.
.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.022mH
mended footprint and soldering techniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C.
R
G
= 25
Ω
, I
AS
= 195A, V
GS
=10V. Part not recommended for use
above this value.
2
IRFP4368PbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
4.8V
4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
4.8V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
4.5V
60µs PULSE WIDTH
Tj = 25°C
60µs PULSE WIDTH
≤
Tj = 175°C
≤
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
100
10
2.5
2.0
1.5
1.0
0.5
I
= 195A
= 10V
V
= 25V
D
DS
60µs PULSE WIDTH
V
≤
GS
T
= 175°C
J
T
= 25°C
J
1.0
1
2
3
4
5
6
7
-60 -40 -20
T
0
20 40 60 80
100120140160180
, Junction Temperature (°C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4.
Normalized On-Resistance vs. Temperature
Fig 3.
Typical Transfer Characteristics
1E+006
100000
10000
1000
12.0
V
C
= 0V,
f = 1 MHZ
GS
I =
195A
D
= C
+ C
, C
SHORTED
iss
gs gd
ds
C
= C
10.0
rss
gd
V
V
= 60V
= 38V
DS
DS
C
= C
+ C
oss
ds
gd
8.0
6.0
4.0
2.0
0.0
C
C
iss
oss
C
rss
100
1
10
, Drain-to-Source Voltage (V)
100
0
50 100
150 200 250 300 350 400
, Total
Gate Charge (nC)
V
Q
DS
G
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFP4368PbF
10000
1000
100
10
1000
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
100
10
1
100µsec
T
= 25°C
J
1msec
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
DC
10
1
0.1
1
100
0.0
0.4
0.8
1.2
1.6
2.0
V
, Drain-to-Source Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode Forward Voltage
350
95
90
85
80
75
70
Id = 5.0mA
300
250
200
150
100
50
Limited By Package
0
25
50
75
100
125
150
175
-60 -40 -20
0
T
20 40 60 80
100120140160180
, Temperature ( °C )
J
T
, Case Temperature (°C)
C
Fig 10.
Drain-to-Source Breakdown Voltage
Fig 9.
Maximum Drain Current vs. Case Temperature
6.0
2000
I
D
TOP
33A
53A
5.0
4.0
3.0
2.0
1.0
0.0
1500
1000
500
0
BOTTOM 195A
10
20
V
30
40
50
60
70
80
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
J
Drain-to-Source Voltage (V)
DS,
Fig 12.
Maximum Avalanche Energy vs. DrainCurrent
Fig 11.
Typical C
OSS
Stored Energy
4
IRFP4368PbF
1
0.1
D = 0.50
0.20
0.10
0.05
R
1
R
1
R
2
R
2
R
3
R
3
R
4
R
4
Ri (°C/W)
τ
i (sec)
0.01
0.02
0.01
0.0145
0.0661
0.1257
0.0838
0.000024
0.000148
0.002766
0.017517
τ
τ
J
τ
J
τ
C
τ
1
τ
1
Ci=
τ
i
/
Ri
τ
τ
τ
2
τ
2
3
τ
3
4
τ
4
0.001
0.0001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
Tj = 150°C and
∆
0.01
Tstart =25°C (Single Pulse)
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
Tstart = 150°C.
j = 25°C and
∆Τ
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
500
400
300
200
100
0
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆
T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche =
t
av
·f
TOP
BOTTOM 1.0%
Duty Cycle
= 195A
Single Pulse
I
D
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
25
50
75
100
125
150
175
I
av
= 2
D
T/ [1.3·BV·Z
th
]
Starting T
, Junction Temperature (°C)
E
AS (AR)
= P
D (ave)
·t
av
J
Fig 15.
Maximum Avalanche Energy vs. Temperature
5
IRFP4368PbF
4.0
3.5
3.0
2.5
30
25
20
15
10
5
I
= 72A
= 64V
F
V
R
T =
25°C
J
T =
125°C
J
I
I
I
= 250µA
= 1.0mA
= 1.0A
D
D
D
2.0
1.5
1.0
0.5
-75 -50 -25
0
25 50 75
100 125 150 175 200
, Temperature ( °C )
0
200
400
600
800
1000
T
di /dt
(A/µs)
J
F
Fig. 17
– Typical Recovery Current vs. di
f
/dt
Fig 16.
Threshold Voltage vs. Temperature
30
25
20
15
10
5
1000
920
840
760
680
600
520
440
360
280
200
I
= 108A
= 64V
I
= 72A
V =
64V
R
F
F
V
R
T =
25°C
T =
25°C
J
J
T =
125°C
J
T =
125°C
J
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt
(A/µs)
di /dt
(A/µs)
F
F
Fig. 18
– Typical Recovery Current vs. di
f
/dt
Fig. 19
– Typical Stored Charge vs. di
f
/dt
1000
I
= 108A
= 64V
F
920
840
760
680
600
520
440
360
280
200
V
R
T =
25°C
J
T =
125°C
J
0
200
400
600
800
1000
di /dt
(A/µs)
F
Fig. 20
– Typical Stored Charge vs. di
f
/dt
6
IRFP4368PbF
Driver Gate Drive
P.W.
P
.
W.
Period
Period
D =
D.U.T
+
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Current
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 20.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
R
G
V
DD
–
I
A
AS
V
2
GS
0.01
Ω
t
p
I
AS
Fig 21b.
Unclamped Inductive Waveforms
Fig 21a.
Unclamped Inductive Test Circuit
L
D
V
DS
V
DS
90%
+
–
V
DD
10%
V
GS
D.U.T
V
GS
Pulse Width < 1µs
Duty Factor < 0.1%
t
d(on)
t
d(off)
t
r
t
f
Fig 22a.
Switching Time Test Circuit
Fig 22b.
Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
Vgs(th)
0
1K
Qgs1
Qgs2
Qgd
Qgodr
Fig 23a.
Gate Charge Test Circuit
Fig 23b.
Gate Charge Waveform
7
IRFP4368PbF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
TO-247AC Part Marking Information
TO-247AC package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
8
