Infineon-Technologies-IRFP4468PBF
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PD -97134
IRFP4468PbF
HEXFET
®
Power MOSFET
Applications
D
V
DSS
R
DS(on)
typ.
100V
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
2.0m
2.6m
:
:
max.
G
I
D
I
D
290A
c
(Silicon Limited)
195A
S
(Package Limited)
Benefits
l
Improved Gate,
Avalanche and Dynamic
dV/dt
Ruggedness
D
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
S
D
G
TO-247AC
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
D
@ T
C
= 25°C
I
DM
Parameter
Max.
290
c
200
Units
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
A
Continuous Drain Current, V
GS
@ 10V (Wire Bond Limited)
Pulsed Drain Current
d
195
1120
520
P
D
@T
C
= 25°C
Maximum Power Dissipation
Linear Derating Factor
W
3.4
W/°C
V
V
GS
± 20
Gate-to-Source Voltage
10
Peak Diode Recovery
f
dv/dt
T
J
V/ns
-55 to
+ 175
Operating Junction and
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
°C
300
10lb
x
in (1.1N
x
m)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy
e
E
AS (Thermally limited)
740
mJ
A
Avalanche Current
ꢀd
I
AR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy
g
E
AR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.29
–––
40
Units
R
θ
JC
R
θ
CS
R
θ
JA
Junction-to-Case
k
Case-to-Sink, Flat Greased Surface
0.24
–––
°C/W
Junction-to-Ambient
jk
1
5/21/08
IRFP4468PbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
Parameter
Min. Typ. Max.
Units
100 ––– –––
––– 0.09 ––– V/°C
Reference to 25°C, I
D
= 5mA
d
Conditions
V
GS
= 0V, I
D
= 250
μ
A
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
V
Δ
V
(BR)DSS
/
Δ
T
J
R
DS(on)
–––
2.0
2.0
2.6
4.0
20
V
GS
= 10V, I
D
= 180A
g
V
DS
= V
GS
, I
D
= 250
μ
A
m
Ω
V
V
GS(th)
–––
I
DSS
Drain-to-Source Leakage Current
––– –––
μ
A V
DS
= 100V, V
GS
= 0V
V
DS
= 80V, V
GS
= 0V, T
J
= 125°C
nA V
GS
= 20V
––– ––– 250
––– ––– 100
––– ––– -100
I
GSS
R
G
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
V
GS
= -20V
–––
0.8
–––
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max.
Units
Conditions
V
DS
= 50V, I
D
= 180A
310 ––– –––
S
Q
g
––– 360 540
nC I
D
= 180A
V
DS
=50V
Q
gs
Gate-to-Source Charge
–––
–––
81
89
–––
Q
gd
Gate-to-Drain (“Miller”) Charge
Total Gate Charge Sync. (Q
g
– Q
gd
)
Turn-On Delay Time
V
GS
= 10V
g
I
D
= 180A, V
DS
=0V, V
GS
= 10V
ns V
DD
= 65V
Q
sync
––– 270 –––
––– 52 –––
t
d(on)
t
r
Rise Time
––– 230 –––
––– 160 –––
––– 260 –––
––– 19860 –––
––– 1360 –––
––– 540 –––
––– 1550 –––
––– 900 –––
I
D
= 180A
t
d(off)
Turn-Off Delay Time
R
G
= 2.7
Ω
V
GS
= 10V
g
t
f
Fall Time
C
iss
Input Capacitance
pF V
GS
= 0V
C
oss
Output Capacitance
V
DS
= 50V
C
rss
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
h
ƒ = 100 kHz,
See Fig. 5
V
GS
= 0V, V
DS
= 0V to 80V
i
, See Fig. 11
V
GS
= 0V, V
DS
= 0V to 80V
h
C
oss
eff. (ER)
C
oss
eff. (TR)
Diode Characteristics
Symbol
Parameter
Min. Typ. Max.
Units
Conditions
I
S
Continuous Source Current
––– –––
A
MOSFET symbol
290
c
D
(Body Diode)
showing the
I
SM
Pulsed Source Current
––– –––
1120
A
integral reverse
G
(Body Diode)
ꢀd
p-n junction diode.
S
V
SD
t
rr
Diode Forward Voltage
––– –––
––– 100
––– 110
––– 370
––– 420
1.3
V
T
J
= 25°C, I
S
= 180A, V
GS
= 0V
g
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
V
R
= 85V,
Reverse Recovery Time
Reverse Recovery Charge
ns
I
F
= 180A
di/dt = 100A/
μ
s
g
Q
rr
nC
I
RRM
t
on
Reverse Recovery Current
Forward Turn-On Time
–––
6.9
–––
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
I
SD
≤
180A, di/dt
≤
600A/
μ
s, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
ꢁ
Pulse width
≤
400
μ
s; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
temperature. Bond wire current limit is 195A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements.
(Refer to AN-1140)
Repetitive rating;
pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.045mH
R
G
= 25
Ω
, I
AS
= 180A, V
GS
=10V. Part not recommended for use
above this value .
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
.
When mounted on 1″ square PCB (FR-4 or G-10 Material).
For recom
mended footprint and soldering techniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C
2
IRFP4468PbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.5V
4.0V
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.5V
4.0V
TOP
TOP
BOTTOM
BOTTOM
4.0V
4.0V
≤
60
μ
s PULSE WIDTH
Tj = 25°C
≤
60
μ
s PULSE WIDTH
Tj = 175°C
1
0.01
0.1
1
10
100
0.1
1
10
, Drain-to-Source Voltage (V)
DS
100
V
, Drain-to-Source Voltage (V)
V
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
100
10
2.5
2.0
1.5
1.0
0.5
I
= 180A
= 10V
D
V
GS
T
= 175°C
J
T
= 25°C
= 25V
J
V
DS
≤
60
μ
s PULSE WIDTH
1
2.0
3.0
4.0
5.0
6.0
7.0
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
V
, Gate-to-Source Voltage (V)
GS
T
, Junction Temperature (°C)
J
Fig 4.
Normalized On-Resistance vs. Temperature
Fig 3.
Typical Transfer Characteristics
16
35000
30000
25000
20000
15000
10000
5000
0
V
C
= 0V,
f = 100 kHz
GS
I =
180A
D
= C
+ C
, C
SHORTED
iss
gs
gd ds
V
V
V
= 80V
= 50V
= 20V
DS
DS
DS
C
= C
rss
gd
C
= C
+ C
ds
12
8
oss
gd
Ciss
4
Coss
Crss
0
0
50 100
150 200 250 300 350 400 450
Total Gate Charge (nC)
1
10
100
Q
G
V
, Drain-to-Source Voltage (V)
DS
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFP4468PbF
1000
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
100
10
1
100
μ
sec
1msec
T
= 25°C
J
LIMITED BY PACKAGE
10msec
DC
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
0.1
0.1
0.1
1
10
100
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
, Source-to-Drain Voltage (V)
V
, Drain-toSource Voltage (V)
V
DS
SD
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
300
250
200
150
100
50
120
110
100
90
LIMITED BY PACKAGE
I
= 5mA
D
0
25
50
75
100
125
150
175
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
T
, Case Temperature (°C)
C
T
, Junction Temperature (°C)
J
Fig 9.
Maximum Drain Current vs.
Fig 10.
Drain-to-Source Breakdown Voltage
Case Temperature
3000
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
I
D
TOP
30A
2500
2000
1500
1000
500
41A
180A
BOTTOM
0
25
50
75
100
125
150
175
0
20
40
60
80
100
Starting T
, Junction Temperature (°C)
V
Drain-to-Source Voltage (V)
J
DS,
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy Vs. DrainCurrent
4
IRFP4468PbF
1
0.1
D = 0.50
0.20
0.10
R
1
R
1
R
2
R
2
R
3
R
3
0.05
0.02
τι
(sec)
Ri (°C/W)
0.01
τ
J
τ
J
τ
τ
C
τ
0.063359 0.000278
0.110878 0.005836
0.114838 0.053606
τ
1
τ
1
τ
2
τ
2
3
τ
3
0.01
Ci=
τ
i
/
Ri
Ci=
τ
i
/
Ri
0.001
0.0001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t
, Rectangular Pulse Duration (sec)
1
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
Δ
Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
ΔΤ
j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
800
600
400
200
0
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
Δ
T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche =
t
av
·f
TOP
BOTTOM 1%
Duty Cycle
= 180A
Single Pulse
I
D
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
25
50
75
100
125
150
175
I
av
= 2
D
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Starting T
, Junction Temperature (°C)
J
Fig 15.
Maximum Avalanche Energy vs. Temperature
5
IRFP4468PbF
4.5
4.0
3.5
3.0
2.5
2.0
1.5
32
24
16
8
I
I
I
= 1.0A
D
D
D
= 1.0mA
= 250
μ
A
I
= 72A
= 85V
F
V
R
T
= 125°C
J
T
= 25°C
J
0
1.0
100 200 300 400 500 600 700 800 900
1000
-75 -50 -25
0
J
25 50 75
100 125 150 175
, Temperature ( °C )
di /
dt – (A /
μ
s)
T
f
Fig. 17
– Typical Recovery Current vs. di
f
/dt
Fig 16.
Threshold Voltage Vs. Temperature
1500
40
32
24
16
1000
500
0
I
= 72A
= 85V
I
= 108A
= 85V
F
F
V
V
R
R
8
0
T
= 125°C
T
= 125°C
= 25°C
J
J
T
= 25°C
T
J
J
100 200 300 400 500 600 700 800 900
1000
100 200 300 400 500 600 700 800 900
1000
di /
dt – (A /
μ
s)
di /
dt – (A /
μ
s)
f
f
Fig. 18
– Typical Recovery Current vs. di
f
/dt
Fig. 19
– Typical Stored Charge vs. di
f
/dt
2000
I
= 108A
= 85V
F
V
T
R
= 125°C
= 25°C
J
1500
1000
500
0
T
J
100 200 300 400 500 600 700 800 900
1000
di /
dt – (A /
μ
s)
f
Fig. 20
– Typical Stored Charge vs. di
f
/dt
6
IRFP4468PbF
Driver Gate Drive
P.W.
P
.
W.
Period
Period
D =
D.U.T
+
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Current
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 21.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
V
2
GS
0.01
Ω
t
p
I
AS
Fig 22b.
Unclamped Inductive Waveforms
Fig 22a.
Unclamped Inductive Test Circuit
R
D
V
DS
V
DS
90%
V
GS
D.U.T.
R
G
+
V
DD
–
V
GS
10%
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a.
Switching Time Test Circuit
Fig 23b.
Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.
T
.
Vds
Vgs
50K
Ω
.2
μ
F
12V
.3
μ
F
+
V
DS
D.U.
T
.
–
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a.
Gate Charge Test Circuit
Fig 24b.
Gate Charge Waveform
7
IRFP4468PbF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
TO-247AC Part Marking Information
EX
A
M
P
LE: THIS
IS
A
N
I
RFPE30
W
I
T H
A
S S E MB L Y
P
A
R
T
N
U
M
B
ER
IN
T
ER
N
A
T
I
O
NAL
RE
C
T
I
FIER
L
O
GO
L
O
T CODE 5657
A
S
SE
M
B
LED
O
N WW
3
5, 2001
IN
T
H
E
A
S
SE
M
B
LY LI
N
E “H”
IRFPE30
135H
57
56
DA
T
E
C
ODE
YE
A
R 1 =
2
001
W
E
EK
3
5
AS S E MB L Y
L
O
T CODE
Note: “P” in a
s
s
e
mb
l
y lin
e
p
o
s
i
tion
indicates “
L
e
ad
–
F
r
e
e”
LINE H
TO-247AC packages are not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
8
