Infineon-Technologies-IRFP4568PBF
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PD –
96175
IRFP4568PbF
HEXFET
®
Power MOSFET
Applications
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
D
S
V
DSS
R
DS(on)
typ.
150V
4.8m
5.9m
171
G
max.
I
D
(Silicon Limited)
Benefits
l
Improved Gate,
Avalanche and Dynamic
dV/dt
D
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
S
D
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
G
TO-247AC
IRFP4568PbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
Parameter
Max.
171
Units
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Pulsed Drain Current
121
A
684
P
D
@T
C
= 25°C
W
517
Maximum Power Dissipation
Linear Derating Factor
3.45
W/°C
V
V
GS
± 30
Gate-to-Source Voltage
18.5
Peak Diode Recovery
dv/dt
T
J
V/ns
-55 to
+ 175
Operating Junction and
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
°C
300
10lb in (1.1N m)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy
E
AS (Thermally limited)
763
mJ
A
Avalanche Current
I
AR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy
E
AR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.29
–––
40
Units
R
θ
JC
Junction-to-Case
R
θ
CS
R
θ
JA
0.24
–––
°C/W
Case-to-Sink, Flat Greased Surface
Junction-to-Ambient
1
09/08/08
IRFP4568PbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Min. Typ. Max.
Units
150 ––– –––
––– 0.17 ––– V/°C
Reference to 25°C, I
D
= 5mA
Conditions
V
GS
= 0V, I
D
= 250µA
V
∆
V
(BR)DSS
/
∆
T
J
R
DS(on)
––– 4.8
3.0 ––– 5.0
––– –––
20
5.9
V
GS
= 10V, I
D
= 103A
V
DS
= V
GS
, I
D
= 250µA
m
Ω
V
V
GS(th)
I
DSS
Drain-to-Source Leakage Current
V
DS
=150V, V
GS
= 0V
µA
––– ––– 250
––– ––– 100
––– ––– -100
––– 1.0 –––
V
DS
= 150V, V
GS
= 0V, T
J
= 125°C
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
V
GS
= 20V
nA
V
GS
= -20V
R
G
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
Parameter
Forward Transconductance
Min. Typ. Max.
Units
Conditions
V
DS
= 50V, I
D
= 103A
gfs
Q
g
162 ––– –––
S
Total Gate Charge
––– 151 227
I
D
= 103A
Q
gs
Q
gd
Gate-to-Source Charge
–––
–––
–––
–––
52
55
96
27
–––
–––
–––
–––
V
DS
= 75V
nC
Gate-to-Drain (“Miller”) Charge
Total Gate Charge Sync. (Q
g
– Q
gd
)
V
GS
= 10V
Q
sync
t
d(on)
t
r
I
D
= 103A, V
DS
=0V, V
GS
= 10V
V
DD
= 98V
Turn-On Delay Time
Rise Time
––– 119 –––
I
D
=103A
ns
t
d(off)
t
f
Turn-Off Delay Time
–––
–––
47
84
–––
–––
R
G
=1.0
Ω
V
GS
= 10V
Fall Time
C
iss
C
oss
C
rss
Input Capacitance
––– 10470 –––
––– 977 –––
––– 203 –––
––– 897 –––
––– 1272 –––
V
GS
= 0V
Output Capacitance
V
DS
= 50V
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
ƒ = 1.0MHz,
(See Fig 5)
GS
= 0V, V
DS
= 0V to 120V
pF
C
oss
eff. (ER)
oss
eff. (TR)
V
(SeeFig.11)
C
V
GS
= 0V, V
DS
= 0V to 120V
Diode Characteristics
Symbol
Parameter
Continuous Source Current
Min. Typ. Max.
Units
Conditions
MOSFET symbol
I
S
D
S
––– ––– 171
A
(Body Diode)
showing the
G
I
SM
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
integral reverse
––– ––– 684
A
V
p-n junction diode.
V
SD
t
rr
––– –––
1.3
––– 110 –––
––– 133 –––
––– 515 –––
––– 758 –––
––– 8.8 –––
T
J
= 25°C, I
S
= 103A, V
GS
= 0V
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
V
R
= 100V,
I
F
= 103A
di/dt = 100A/µs
ns
Q
rr
Reverse Recovery Charge
nC
A
I
RRM
t
on
Reverse Recovery Current
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Pulse width
≤
400µs; duty cycle
≤
2%.
ꢀ
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
Repetitive rating;
pulse width limited by max. junction
temperature.
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.144mH
R
G
= 25
Ω
, I
AS
= 103A, V
GS
=10V. Part not recommended for use
above this value.
.
When mounted on 1″ square PCB (FR-4 or G-10 Material).
For recom
mended footprint and soldering techniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C.
I
SD
≤
103A, di/dt
≤
360A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
2
IRFP4568PbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
TOP
BOTTOM
BOTTOM
1
4.5V
60µs PULSE WIDTH
≤
Tj = 25°C
0.1
0.01
60µs PULSE WIDTH
Tj = 175°C
≤
4.5V
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
100
10
3.0
2.5
2.0
1.5
1.0
0.5
I
= 103A
= 10V
D
V
GS
T
= 175°C
J
T
= 25°C
J
1
V
= 50V
DS
≤
60µs PULSE WIDTH
0.1
3
4
5
6
7
8
9
-60 -40 -20
0 20
40 60 80
100120140160180
, Junction Temperature (°C)
T
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4.
Normalized On-Resistance vs. Temperature
Fig 3.
Typical Transfer Characteristics
14.0
1000000
100000
10000
1000
V
= 0V,
= C
f = 1 MHZ
GS
I =
103A
D
C
C
C
+ C
, C
SHORTED
ds
iss
gs
gd
12.0
= C
rss
oss
gd
= C
+ C
V
V
= 120V
= 75V
DS
DS
ds
gd
10.0
8.0
6.0
4.0
2.0
0.0
VDS= 30V
C
iss
C
oss
C
rss
100
10
0
50
100
150
200
1
10
100
1000
Q ,
Total Gate Charge (nC)
V
, Drain-to-Source Voltage (V)
G
DS
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFP4568PbF
10000
1000
100
10
1000
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
T
= 25°C
J
100µsec
100
10
1msec
DC
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
0.1
1.0
0.1
1
10
100
1000
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
, Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
V
DS
SD
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
190
185
180
175
170
165
160
155
150
145
140
180
Id = 5mA
160
140
120
100
80
60
40
20
0
-60 -40 -20
0 20
40 60 80
100120140160180
25
50
75
100
125
150
175
T
, Temperature ( °C )
T
, Case Temperature (°C)
J
Fig 9.
Maxi
C
mum Drain Current vs.
Fig 10.
Drain-to-Source Breakdown Voltage
Case Temperature
3500
3000
2500
2000
1500
1000
500
12.0
I
D
TOP
21.5A
29.3A
BOTTOM 103A
10.0
8.0
6.0
4.0
2.0
0.0
0
25
50
75
100
125
150
175
0
20 40 60
80 100
120 140 160
Starting T
, Junction Temperature (°C)
J
V
Drain-to-Source Voltage (V)
Fig 11.
Typi
c
D
a
S
l
,
C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy vs. DrainCurrent
4
IRFP4568PbF
1
0.1
D = 0.50
0.20
0.10
0.05
0.01
R
1
R
1
R
2
R
2
R
3
R
3
0.02
0.01
Ri (°C/W)
τ
i (sec)
τ
J
τ
J
τ
C
τ
0.06336 0.000278
τ
τ
1
τ
1
τ
2
τ
2
0.11088 0.005836
3
τ
3
0.001
0.0001
0.11484 0.053606
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ci=
τ
i
/
Ri
SINGLE PULSE
( THERMAL RESPONSE )
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆
Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆
Τ
j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
900
800
700
600
500
400
300
200
100
0
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
TOP
BOTTOM 1.0%
Duty Cycle
= 103A
Single Pulse
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆
T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
I
D
t
av =
Average time in avalanche.
D = Duty cycle in avalanche =
t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
25
50
75
100
125
150
175
I
av
= 2
D
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Starting T
, Junction Temperature (°C)
J
Fig 15.
Maximum Avalanche Energy vs. Temperature
5
IRFP4568PbF
6.0
5.5
5.0
4.5
4.0
3.5
3.0
60
50
40
30
20
10
0
I =
68A
F
V
= 100V
R
T =
25°C
J
T =
125°C
J
I
I
= 250µA
D
D
= 1.0mA
2.5
2.0
1.5
1.0
ID = 1.0A
-75 -50 -25
0
25 50 75
100 125 150 175
0
200
400
600
800
1000
T ,
Temperature ( °C )
di /dt
(A/µs)
J
F
Fig. 17
– Typical Recovery Current vs. di
f
/dt
Fig 16.
Threshold Voltage vs. Temperature
70
3600
I =
103A
I =
68A
F
F
3200
2800
2400
2000
1600
1200
800
60
50
40
30
20
10
0
V
= 100V
V
= 100V
R
R
T =
25°C
T =
25°C
J
J
T =
125°C
J
T =
125°C
J
400
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt
(A/µs)
di /dt
(A/µs)
F
F
Fig. 18
– Typical Recovery Current vs. di
f
/dt
Fig. 19
– Typical Stored Charge vs. di
f
/dt
4000
I =
103A
F
V
3600
3200
2800
2400
2000
1600
1200
800
= 100V
R
T =
25°C
J
T =
125°C
J
400
0
200
400
600
800
1000
di /dt
(A/µs)
F
Fig. 20
– Typical Stored Charge vs. di
f
/dt
6
IRFP4568PbF
Driver Gate Drive
P.W.
P
.
W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Current
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 21.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
V
2
GS
Ω
0.01
t
p
I
AS
Fig 22b.
Unclamped Inductive Waveforms
Fig 22a.
Unclamped Inductive Test Circuit
R
D
V
DS
V
DS
90%
V
GS
D.U.T.
R
G
+
V
DD
–
V
GS
10%
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a.
Switching Time Test Circuit
Fig 23b.
Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.
T
.
Vds
Vgs
50K
Ω
.2
µ
F
12V
.3
µ
F
+
V
DS
D.U.
T
.
–
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a.
Gate Charge Test Circuit
Fig 24b.
Gate Charge Waveform
7
IRFP4568PbF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
TO-247AC Part Marking Information
TO-247AC package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
8
