Infineon-Technologies-IRFR18N15DTRLP
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PD – 95061A
IRFR18N15DPbF
IRFU18N15DPbF
HEXFET
®
Power MOSFET
SMPS MOSFET
Applications
l
High frequency DC-DC converters
l
Lead-Free
V
DSS
150V
R
DS(on)
max
I
D
18A
0.125
Ω
Benefits
l
Low Gate to Drain Charge to Reduce
Switching Losses
l
Fully Characterized Capacitance Including
Effective C
OSS
to Simplify Design, (See
App. Note AN1001)
l
Fully Characterized Avalanche Voltage
and Current
D-Pak
IRFR18N15DPbF
I-Pak
IRFU18N15DPbF
Absolute Maximum Ratings
Parameter
Max.
Units
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
18
13
A
72
P
D
@T
C
= 25°C
Power Dissipation
110
W
W/°C
V
Linear Derating Factor
0.71
V
GS
dv/dt
T
J
Gate-to-Source Voltage
± 30
Peak Diode Recovery dv/dt
Operating Junction and
3.3
V/ns
-55 to
+ 175
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
°C
300 (1.6mm from case )
Typical SMPS Topologies
l
Telecom 48V input
DC-DC Active Clamp Reset Forward Converter
Notes
through
are on page 10
1
12/9/04
IRFR/U18N15DPbF
Static @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
150 –––
–––
––– 0.17
––– V/°C
Reference to 25°C, I
D
= 1mA
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
V
V
GS
= 0V, I
D
= 250µA
∆
V
(BR)DSS
/
∆
T
J
Breakdown Voltage Temp. Coefficient
R
DS(on)
V
GS(th)
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
––– –––
0.125
3.0 –––
5.5
Ω
V
V
GS
= 10V, I
D
= 11A
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 150V, V
GS
= 0V
V
DS
= 120V, V
GS
= 0V, T
J
= 150°C
V
GS
= 30V
––– ––– 25
––– –––
250
––– –––
100
––– –––
-100
I
DSS
Drain-to-Source Leakage Current
µA
nA
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
I
GSS
V
GS
= -30V
Dynamic @ T
J
= 25°C (unless otherwise specified)
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
g
fs
4.2
–––
–––
–––
–––
–––
–––
–––
––– –––
S
V
DS
= 50V, I
D
= 11A
I
D
= 11A
Q
g
28
7.6
14
43
11
21
Q
gs
Q
gd
t
d(on)
t
r
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Turn-On Delay Time
Rise Time
nC V
DS
= 120V
V
GS
= 10V,
V
DD
= 75V
8.8 –––
25 –––
15 –––
9.8 –––
I
D
= 11A
ns
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
R
G
= 6.8
Ω
V
GS
= 10V
V
GS
= 0V
C
iss
C
oss
C
rss
C
oss
C
oss
Input Capacitance
––– 900
–––
––– 190
–––
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
V
DS
= 25V
–––
49 –––
pF
ƒ = 1.0MHz
––– 1160
–––
V
GS
= 0V,
V
DS
= 1.0V,
ƒ = 1.0MHz
V
GS
= 0V,
V
DS
= 120V,
ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 120V
ꢀ
–––
–––
88 –––
95 –––
C
oss
eff.
Avalanche Characteristics
Parameter
Single Pulse Avalanche Energy
Typ.
Max.
200
11
Units
mJ
E
AS
I
AR
–––
–––
–––
Avalanche Current
A
E
AR
Repetitive Avalanche Energy
11
mJ
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
–––
–––
Max.
1.4
Units
R
θ
JC
R
θ
JA
R
θ
JA
Junction-to-Ambient (PCB mount)*
Junction-to-Ambient
50
°C/W
110
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
D
I
S
Continuous Source Current
(Body Diode)
MOSFET symbol
18
72
––– –––
––– –––
showing the
A
G
I
SM
Pulsed Source Current
(Body Diode)
integral reverse
p-n junction diode.
S
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 1.3
––– 130 190
––– 660 980
V
T
J
= 25°C, I
S
= 11A, V
GS
= 0V
ns
T
J
= 25°C, I
F
= 11A
Q
rr
t
on
nC di/dt
= 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
2
IRFR/U18N15DPbF
100
100
10
1
VGS
15V
VGS
15V
TOP
TOP
10V
10V
9.0V
8.0V
7.5V
7.0V
6.5V
9.0V
8.0V
7.5V
7.0V
6.5V
BOTTOM 6.0V
BOTTOM 6.0V
10
6.0V
6.0V
20µs PULSE WIDTH
20µs PULSE WIDTH
T =
25 C
J
°
T =
175 C
J
°
1
0.1
0.1
0.1
1
10
100
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
100
3.0
18A
=
I
D
2.5
2.0
1.5
1.0
0.5
0.0
°
T =
175 C
J
10
°
T =
25 C
J
V
= 50V
DS
20µs PULSE WIDTH
V
=
1
0V
GS
1
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
°
6
7
8
9
10 11
12
T ,
Junction Temperature (
C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
3
IRFR/U18N15DPbF
10000
20
16
12
8
V
= 0V,
f = 1 MHZ
I
D
= 11A
GS
C
= C
+ C
,
C
ds
SHORTED
iss
gs gd
V
V
V
= 120V
= 75V
= 30V
C
= C
DS
DS
DS
rss
gd
C
= C
+ C
oss
ds
gd
1000
100
10
Ciss
Coss
Crss
4
FOR TEST CIRCUIT
SEE FIGURE 13
1
10
100
1000
0
V
, Drain-to-Source Voltage (V)
DS
0
10
20
30
40
Q ,
Total Gate Charge (nC)
G
Fig 6.
Typical Gate Charge Vs.
Fig 5.
Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000
100
10
100
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
10
°
T =
175 C
10us
J
°
T =
25 C
J
100us
1ms
1
°
T =
25 C
C
J
°
T =
175 C
V
= 0 V
Single Pulse
GS
10ms
0.1
0.2
1
0.5
0.8
1.1
1.4
1
10
100
1000
V
,Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
4
IRFR/U18N15DPbF
R
D
20
16
12
8
V
DS
V
GS
D.U.T.
R
G
+
V
DD
–
V
GS
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
Fig 10a.
Switching Time Test Circuit
4
V
DS
90%
0
25
50
75
100
125
150
175
°
T ,
Case Temperature
( C)
C
10%
V
GS
t
t
r
t
t
f
Fig 9.
Maximum Drain Current Vs.
d(on)
d(off)
Case Temperature
Fig 10b.
Switching Time Waveforms
10
1
D = 0.50
0.20
0.10
0.05
P
2
DM
0.1
0.01
t
1
0.02
0.01
SINGLE PULSE
t
2
(THERMAL RESPONSE)
Notes:
1. Duty factor D =
2. Peak T
=
P
t /
t
1
x Z
+ T
thJC C
J
DM
0.00001
0.0001
0.001
0.01
0.1
t ,
Rectangular Pulse Duration (sec)
1
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
IRFR/U18N15DPbF
500
400
300
200
100
0
15V
I
D
TOP
4.4A
9.0A
BOTTOM 11A
DRIVER
L
V
DS
D.U.T
AS
R
G
+
–
V
DD
I
A
20V
0.01
Ω
t
p
Fig 12a.
Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
175
°
Starting T
, Junction Temperature
( C)
J
I
AS
Fig 12c.
Maximum Avalanche Energy
Fig 12b.
Unclamped Inductive Waveforms
Vs. Drain Current
Current Regulator
Same Type as D.U.
T
.
50K
Ω
Q
Q
G
.2
µ
F
12V
.3
µ
F
+
V
DS
Q
D.U.
T
.
–
GS
GD
V
GS
V
G
3mA
I
I
D
G
Current Sampling Resistors
Charge
Fig 13a.
Basic Gate Charge Waveform
Fig 13b.
Gate Charge Test Circuit
6
IRFR/U18N15DPbF
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current T
r
a
nsformer
D.U.T
–
+
–
–
+
R
G
•
dv/dt controlled by R
G
+
–
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
V
DD
Driver Gate Drive
P.W.
P
.
W.
Period
Period
D =
V
=10V
*
GS
D.U.
T
. I
W
aveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 14.
For N-Channel HEXFET
®
Power MOSFETs
7
IRFR/U18N15DPbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
E
X
AM
P
L
E: THIS
IS AN IRFR120
P
A
R
T NUMBER
WITH A
S
S
E
MBLY
LOT CODE 1234
INTERNATIONAL
RECTIFIER
LOGO
DAT E CODE
Y
E
A
R 9 =
1
999
WE E K
1
6
I
R
FU120
916A
A
S
SE
M
BLED
O
N
W
W
1
6, 1999
IN THE A
S
SE
M
BL
Y
L
INE “A”
12
34
LINE A
Note:
“
P
“
i
n
a
ssemb
l
y li
n
e pos
i
ti
o
n
A
S
SE
M
BLY
LOT CODE
i
n
d
i
c
ates
“
L
e
ad
–
F
r
e
e”
OR
P
A
R
T NUMBER
DAT E
C
ODE
P =
DESIGN
A
TES LEAD-FREE
PRODUCT (OP
T
IONAL)
I
N
TERNATI
O
N
A
L
RECTIF
I
E
R
L
O
GO
I
R
FU120
12 34
Y
E
A
R 9 =
1
999
AS S E MB L Y
L
O
T CODE
W
E
EK 16
A=
A
S
SE
M
BLY
SITE CODE
8
IRFR/U18N15DPbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
P
A
R
T NUMBER
E
X
AM
P
L
E: THIS
IS AN IR
F
U120
INT
E
RNAT
I
O
N
A
L
WIT H AS S E MB L Y
DAT E C
O
D
E
Y
E
A
R 9 =
1
999
WEE K 19
RE
C
T
I
F
I
E
R
LO
G
O
IR
F
U120
919A
78
L
O
T CODE 5678
AS
S
E
M
B
L
E
D
ON
W
W
1
9, 1999
IN T
H
E
A
S
SE
M
BLY
LINE
“
A”
56
LI
N
E A
AS S E MB L Y
L
O
T CODE
Note:
“
P
”
i
n
a
ssemb
l
y li
n
e
pos
i
t
i
o
n
i nd
i
c
a
t
e
s
“
L
e
ad-F
r
e
e”
OR
P
A
RT NUMBER
D
A
T E
C
ODE
I
N
TERNATI
O
N
A
L
REC
T
I
F
I
E
R
L
O
GO
IR
F
U120
56 78
P =
DES
I
G
N
A
T
E
S
L
EAD-FREE
P
R
ODUCT (OP
T
I
O
N
AL)
Y
E
AR 9 =
1
999
A
S
S
E
MB
L
Y
L
O
T CO
D
E
WE EK
19
A =
A
S S E MB L Y S IT E
C
ODE
9
IRFR/U18N15DPbF
D-Pak (TO-252AA)
T
a
pe & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRL
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
FEED DIRECTION
NOTES :
1. CONTROLLING
DIMENSION : MILLIMETER.
2. ALL
DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE
CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
Repetitive rating;
pulse width limited by
Pulse width
≤
300µs; duty cycle
≤
2%.
max. junction temperature.
Starting T
J
= 25°C, L = 3.3mH
R
G
= 25
Ω
, I
AS
= 11A.
ꢀ
C
oss
eff. is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
I
SD
≤
11A, di/dt
≤
170A/µs, V
DD
≤
V
(BR)DSS
T
J
≤
175°C
,
*
When mounted on 1″ square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to application note #AN-994.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
10
Note: For
the most current drawings please refer to the IR website at:
