Infineon-Technologies-IRFR4104TRPBF
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PD – 95425B
IRFR4104PbF
IRFU4104PbF
HEXFET
®
Power MOSFET
Features
D
l
l
l
l
l
l
Advanced Process Technology
V
DSS
= 40V
Ultr
a
L
o
w
O
n-Resistance
175°
C
O
peratin
g
T
emperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
R
DS(on)
= 5.5m
Ω
G
I
D
= 42A
S
Description
This HEXFET
®
Power MOSFET utilizes the latest
processing techniques to achieve extremely low on-
resistanc
e
p
e
r
s
ilico
n
a
rea
.
A
dditiona
l
f
eature
s
o
f
t
his
design are
a 175°C junction operating temperature,
fas
t
s
witchin
g
s
pee
d
a
n
d
i
mprove
d
r
epetitiv
e
a
valanche
rating . These features combine to make this design
a
n
e
xtremel
y
e
fficien
t
a
n
d
r
eliabl
e
d
evic
e
f
o
r
u
s
e
i
n
a
wide variety of applications.
D-Pak
IRFR4104PbF
I-Pak
IRFU4104PbF
Absolute Maximum Ratings
Parameter
Max.
Units
(Silicon Limited)
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
I
I
I
I
@ T
= 25°C
C
119
D
D
D
@ T
= 100°C
C
84
A
(Package Limited)
@ T
= 25°C
C
42
480
140
DM
P
@T =
25°C
Power Dissipation
C
W
D
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
0.95
± 20
W/°C
V
V
GS
E
AS (Thermally limited)
145
310
mJ
Single Pulse Avalanche Energy Tested Value
Avalanche Current
E
AS
(Tested )
I
AR
See Fig.12a, 12b, 15, 16
A
Repetitive Avalanche Energy
E
AR
mJ
T
J
Operating Junction and
-55 to
+ 175
T
Storage Temperature Range
°C
STG
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
300 (1.6mm from case )
10 lbf
in (1.1N m)
Thermal Resistance
Parameter
Typ.
–––
–––
–––
Max.
1.05
40
Units
R
θ
R
θ
R
θ
Junction-to-Case
Junction-to-Ambient (PCB mount)
JC
JA
JA
°C/W
Junction-to-Ambient
110
HEXFET
®
is a registered trademark of International Rectifier.
1
09/21/10
IRFR/U4104PbF
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max.
Units
40 –––
–––
Conditions
V
GS
= 0V, I
D
= 250µA
V
(BR)DSS
∆
V
(BR)DSS
/
∆
T
J
R
DS(on)
V
Breakdown Voltage Temp. Coefficient
––– 0.032 –––
V/°C Reference
to 25°C, I
D
= 1mA
m
Ω
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
–––
2.0
4.3
–––
–––
–––
–––
–––
–––
59
5.5
4.0
V
GS
= 10V, I
D
= 42A
V
GS(th)
V
S
V
DS
= V
GS
, I
D
= 250µA
gfs
Forward Transconductance
58
–––
20
V
DS
= 10V, I
D
= 42A
DS
= 40V, V
GS
= 0V
I
DSS
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
µA
V
250
200
-200
89
V
DS
= 40V, V
GS
= 0V, T
J
= 125°C
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
nA V
GS
= 20V
V
GS
= -20V
I
D
= 42A
Q
g
Q
gs
Q
gd
t
d(on)
t
r
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Turn-On Delay Time
19
–––
–––
–––
–––
–––
–––
–––
nC V
DS
= 32V
V
GS
= 10V
24
17
V
DD
= 20V
Rise Time
69
I
D
= 42A
t
d(off)
t
f
Turn-Off Delay Time
37
ns R
G
= 6.8
Ω
V
GS
= 10V
Fall Time
36
L
D
Internal Drain Inductance
4.5
Between lead,
nH 6mm
(0.25in.)
from package
L
S
Internal Source Inductance
–––
7.5
–––
and center of die contact
C
iss
Input Capacitance
––– 2950 –––
V
GS
= 0V
C
oss
Output Capacitance
–––
–––
660
370
–––
–––
V
DS
= 25V
C
rss
Reverse Transfer Capacitance
Output Capacitance
pF ƒ
= 1.0MHz
C
oss
––– 2130 –––
V
GS
= 0V,
V
DS
= 1.0V,
ƒ = 1.0MHz
C
oss
Output Capacitance
–––
–––
590
850
–––
–––
V
GS
= 0V,
V
DS
= 32V,
ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 32V
C
oss
eff.
Effective Output Capacitance
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max.
Units
Conditions
I
Continuous Source Current
–––
–––
42
MOSFET symbol
S
(Body Diode)
A
showing the
I
Pulsed Source Current
–––
–––
480
integral reverse
SM
(Body Diode)
p-n junction diode.
V
t
Diode Forward Voltage
–––
–––
–––
–––
28
1.3
42
36
V
T =
25°C, I
= 42A, V
= 0V
SD
J
S
GS
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
ns T
= 25°C, I
= 42A, V
DD
= 20V
J F
rr
di/dt = 100A/µs
Q
t
24
nC
rr
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
on
2
IRFR/U4104PbF
1000
100
10
1000
100
10
V
GS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
V
GS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
TOP
TOP
BOTTOM 4.5V
BOTTOM 4.5V
4.5V
4.5V
60µs PULSE WIDTH
Tj = 25°C
60µs PULSE WIDTH
Tj = 175°C
1
1
0.1
1
1
10
1
100
1
0.1
1
1
10
1
100
1
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
120
T
= 25°C
J
T
= 175°C
J
100
80
60
40
20
0
T
= 175°C
J
100
10
1
T =
25°C
J
V
= 20V
DS
V
= 10V
DS
60µs PULSE WIDTH
380µs PULSE WIDTH
4
6
8 10
0
20
40
60
80
100
V
, Gate-to-Source Voltage (V)
GS
I
Drain-to-Source Current (A)
D,
Fig 3.
Typical Transfer Characteristics
Fig 4.
Typical Forward Transconductance
Vs. Drain Current
3
IRFR/U4104PbF
5000
20
16
12
8
V
= 0V,
= C
f = 1 MHZ
GS
I =
42A
D
V
= 32V
C
C
C
+ C
, C
SHORTED
DS
VDS= 20V
iss
gs
gd
ds
= C
rss
oss
gd
4000
3000
2000
1000
0
= C
+ C
ds
gd
Ciss
Coss
Crss
4
0
0
20
Q
40
60
80
100
1
10
, Drain-to-Source Voltage (V)
100
Total Gate Charge (nC)
G
V
DS
Fig 6.
Typical Gate Charge Vs.
Fig 5.
Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
10000
1000
100
10
1000.0
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
100.0
10.0
1.0
T
= 175°C
J
100µsec
T
= 25°C
J
1msec
1
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
0.1
0.1
0
1
10
100
1000
0.0
0.5
1.0
1.5
2.0
V
, Drain-toSource Voltage (V)
DS
V
, Source-toDrain Voltage (V)
SD
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
4
IRFR/U4104PbF
2.0
1.5
1.0
0.5
120
100
80
60
40
20
0
I
= 42A
= 10V
D
LIMITED BY PACKAGE
V
GS
25
50
75
100
125
150
175
-60 -40 -20
T
0
20 40 60 80
100 120 140 160 180
T
, Case Temperature (°C)
, Junction Temperature (°C)
C
J
Fig 10.
Normalized On-Resistance
Fig 9.
Maximum Drain Current Vs.
Vs. Temperature
Case Temperature
10
1
D = 0.50
0.20
R
1
R
1
R
2
R
2
0.10
0.1
0.01
Ri (°C/W)
τ
i (sec)
τ
J
τ
J
τ
0.5067
0.000414
τ
0.05
C
τ
τ
1
τ
1
Ci=
τ
i
/
Ri
2
τ
2
0.02
0.01
0.5428
0.004081
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
IRFR/U4104PbF
600
500
400
300
200
100
0
15V
I
D
TOP
9.2A
13A
42A
DRIVER
+
L
V
BOTTOM
DS
D.U.T
AS
R
G
V
DD
–
I
A
2
V
0
G
V
S
Ω
0.01
t
p
Fig 12a.
Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
J
I
AS
Fig 12c.
Maximum Avalanche Energy
Fig 12b.
Unclamped Inductive Waveforms
Vs. Drain Current
Q
G
10 V
Q
Q
4.0
3.0
2.0
1.0
GS
GD
V
G
I
= 250µA
D
Charge
Fig 13a.
Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.
T
.
50K
Ω
.2
µ
F
12V
.3
µ
F
+
V
DS
D.U.
T
.
–
-75 -50 -25
0
25 50 75
100 125 150 175
V
GS
3mA
T ,
Temperature ( °C )
J
I
I
D
G
Current Sampling Resistors
Fig 14.
Threshold Voltage Vs. Temperature
Fig 13b.
Gate Charge Test Circuit
6
IRFR/U4104PbF
1000
100
10
Duty Cycle = Single Pulse
0.01
Allowed avalanche Current vs
avalanche pulsewidth, tav
∆
assuming
Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.05
0.10
1
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
tav (sec)
Fig 15.
Typical Avalanche Current Vs.Pulsewidth
160
Notes on Repetitive Avalanche Curves , Figures 15, 16:
TOP
BOTTOM 1%
Duty Cycle
= 42A
Single Pulse
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for
every part type.
I
D
120
80
40
0
2. Safe operation in Avalanche is allowed as long asT
jmax
is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. P
D (ave)
= Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆
T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as 25°C in Figure 15, 16).
t
av =
Average time in avalanche.
25
50
75
100
125
150
175
D = Duty cycle in avalanche =
t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see figure 11)
Starting T
, Junction Temperature (°C)
J
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
Fig 16.
Maximum Avalanche Energy
I
av
= 2
D
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Vs. Temperature
7
IRFR/U4104PbF
Driver Gate Drive
P.W.
P
.
W.
Period
Period
D =
D.U.T
+
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Curent
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 17.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
R
D
V
DS
V
GS
D.U.T.
R
G
+
V
DD
–
10V
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
Fig 18a.
Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 18b.
Switching Time Waveforms
8
IRFR/U4104PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EX
A
M
P
LE: THIS
IS
A
N
I
RFR120
P
A
R
T NU
M
B
ER
W
I
T H
A
S S
E
M
B
LY
L
O
T CO
D
E 1234
A
S
SE
M
B
LED
O
N WW 1
6
, 2001
IN THE
A
S
SE
M
B
LY LINE “
A
”
IN
T
ER
N
A
T
I
O
NAL
RE
C
T
IFIER
L
O
GO
D
A
T
E
C
O
D
E
Y
E
A
R 1 =
2
001
W
E
EK 16
IRFR120
116A
34
12
LINE A
Note: “P”
i
n
a
s
s
e
mb
l
y li
n
e
p
o
s
i
t
i
o
n
AS S E MB L Y
L
O
T CODE
i
n
dicates “
L
e
ad
–
Fr
e
e”
“P” in
a
s
s
e
mb
l
y lin
e
p
o
s
i
tion indicates
“L
e
ad
–
Fr
e
e” qua
l
ifi
c
at
i
o
n to the cons ume
r
-l
e
vel
P
A
R
T NU
M
B
ER
IN
T
ER
N
A
T
I
O
NAL
RE
C
T
IFIER
D
A
T
E
C
ODE
P =
DESI
G
N
A
T
ES LE
A
D
–
F
REE
PR
O
D
U
C
T (O
P
TI
O
NA
L
)
OR
IRFR120
12 34
L
O
GO
P =
DESI
G
N
A
T
ES LE
A
D
–
F
REE
PR
O
D
U
C
T Q
U
A
L
IFIED
T
O
T
H
E
CON
S
U
M
E
R LE
V
E
L
(
O
P
TI
O
NA
L
)
AS S E MB L Y
L
O
T CODE
Y
E
A
R 1 =
2
001
W
E
E K
16
A =
A
S S
E
M
B
L
Y S IT E
C
ODE
Notes:
1. For an Automotive Qualified version of this part please see
http://www.irf.com/product-info/datasheets/
data/auirfr4104.pdf
9
IRFR/U4104PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
P
A
R
T NU
M
B
ER
EX
A
M
P
LE: THIS
IS
A
N
I
R
F
U
120
I
N
T
ER
N
A
T
I
O
NAL
W
I
T H
A
S S
E
M
B
LY
DAT E
CODE
Y
E
A
R 1 =
2
001
WE E K
1
9
RE
C
T
I
F
I
ER
L
O
GO
IRFU
1
20
119A
78
L
O
T CODE 5
6
78
A
S
SE
M
B
LED
O
N WW
1
9, 2001
IN
T
HE
A
S
SE
M
B
LY LINE “
A
”
56
LI
N
E A
A
S
SE
M
B
LY
L
O
T CODE
Note: “P” in
a
s
s
e
mb
l
y lin
e
p
o
s
i
tion
in
d
i
c
ates L
ead-F
r
e
e”
OR
P
A
R
T NU
M
B
ER
DAT E
CODE
P =
DE S I
G
N
A
T E S
L
E
A
D
–
F R E E
PR
O
D
U
C
T
(
OP
T
I
O
NA
L
)
I
N
T
ER
N
A
T
I
ONAL
RE
C
T
IFIER
L
O
GO
IRFU
1
20
56 78
Y
E
A
R 1 =
2
001
A
S
SE
M
B
LY
L
O
T CO
D
E
W
E
EK
1
9
A=
A
S
SE
M
B
LY
SITE
C
ODE
Notes:
1. For an Automotive Qualified version of this part please see
http://www.irf.com/product-info/datasheets/
data/auirfr4104.pdf
10
IRFR/U4104PbF
D-Pak (TO-252AA)
T
a
pe & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRL
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
FEED DIRECTION
NOTES :
1. CONTROLLING
DIMENSION : MILLIMETER.
2. ALL
DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE
CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
C
oss
eff. is a fixed capacitance that gives the same charging time
Repetitive rating;
pulse width limited by
max. junction temperature. (See fig. 11).
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.16mH
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
ꢀ
Limited by T
Jmax
, see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
R
G
= 25
Ω
, I
AS
= 42A, V
GS
=10V. Part not
recommended for use above this value.
This value determined from sample failure population. 100%
tested to this value in production.
Pulse width
≤
1.0ms; duty cycle
≤
2%.
When mounted on 1″ square PCB (FR-4 or G-10 Material) .
For recommended footprint and soldering techniques refer to
application note #AN-994
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
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