Infineon-Technologies-IRFR5505TRPBF
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PD – 9.1610B
IRFR/U5505
HEXFET
®
Power MOSFET
l
Ultra Low On-Resistance
l
P-Channel
l
Surface Mount (IRFR5505)
l
Straight Lead (IRFU5505)
l
Advanced Process Technology
l
Fast Switching
D
V
DSS
= -55V
R
DS(on)
= 0.11
Ω
I
D
= -18A
G
l
Fully Avalanche Rated
S
Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low
on-resistance per silicon area.
This benefit,
combined with the fast switching speed and ruggedized
device design that HEXFET Power MOSFETs are well
know
n
f
or, provide
s
t
h
e
d
esigne
r
w
it
h
a
n
e
xtremel
y
e
fficient
and reliable device for use in a wide variety of applications.
I-Pa k
D
–
Pa k
T O
–
2 52 A A
TO -2 5 1 AA
The D-Pak is designed for surface mounting using vapor
phase, infrared, o
r
w
av
e
s
olderin
g
t
echniques.
Th
e
s
traight
lead version (IRFU series) is for through-hole mounting
applications. Power
dissipation levels up to 1.5 watts are
possible in typical surface mount applications.
Absolute Maximum Ratings
Parameter
Max.
Units
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
Continuous Drain Current, V
GS
@ -10V
Continuous Drain Current, V
GS
@ -10V
Pulsed Drain Current
-18
-11
A
-64
P
D
@T
C
= 25°C
Power Dissipation
57
W
W/°C
V
Linear Derating Factor
0.45
V
GS
E
AS
I
AR
Gate-to-Source Voltage
± 20
Single Pulse Avalanche Energy
Avalanche Current
150
mJ
A
-9.6
E
AR
dv/dt
T
J
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
5.7
mJ
V/ns
-5.0
-55 to
+ 150
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
–––
–––
Max.
2.2
50
Units
R
θ
JC
R
θ
JA
R
θ
JA
Junction-to-Ambient (PCB mount)**
Junction-to-Ambient
°C/W
110
8/25/97
IRFR/U5505
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
-55 –––
–––
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
V
V
GS
= 0V, I
D
= -250µA
∆
V
(BR)DSS
/
∆
T
J
Breakdown Voltage Temp. Coefficient
––– -0.049
––– V/°C Reference
to 25°C, I
D
= -1mA
R
DS(on)
V
GS(th)
g
fs
Static Drain-to-Source On-Resistance
––– –––
0.11
Ω
V
S
V
GS
= -10V, I
D
= -9.6A
V
DS
= V
GS
, I
D
= -250µA
V
DS
= -25V, I
D
= -9.6A
V
DS
= -55V, V
GS
= 0V
V
DS
= -44V, V
GS
= 0V, T
J
= 150°C
V
GS
= 20V
Gate Threshold Voltage
-2.0 –––
-4.0
4.2 –––
–––
Forward Transconductance
––– ––– -25
––– –––
-250
––– –––
-100
––– –––
100
––– ––– 32
––– ––– 7.1
––– ––– 15
I
DSS
Drain-to-Source Leakage Current
µA
nA
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
I
GSS
V
GS
= -20V
Q
g
I
D
= -9.6A
Q
gs
Q
gd
t
d(on)
t
r
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Turn-On Delay Time
Rise Time
nC V
DS
= -44V
V
GS
= -10V, See Fig. 6 and 13
–––
–––
–––
–––
12 –––
28 –––
20 –––
16 –––
V
DD
= -28V
I
D
= -9.6A
ns
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
R
G
= 2.6
Ω
R
D
= 2.8
Ω,
See Fig. 10
Between lead,
6mm (0.25in.)
from package
D
4.5
7.5
L
D
L
S
Internal Drain Inductance
Internal Source Inductance
–––
–––
–––
–––
nH
pF
G
and center of die contact
ꢀ
V
GS
= 0V
S
C
iss
C
oss
C
rss
Input Capacitance
––– 650
–––
––– 270
–––
––– 120
–––
Output Capacitance
V
DS
= -25V
Reverse Transfer Capacitance
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
MOSFET symbol
showing the
D
I
S
-18
––– –––
A
G
I
SM
Pulsed Source Current
(Body Diode)
integral reverse
––– –––
-64
––– ––– -1.6
p-n junction diode.
S
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
V
T
J
= 25°C, I
S
= -9.6A, V
GS
= 0V
––– 51
77
ns
T
J
= 25°C, I
F
= -9.6A
Q
rr
t
on
––– 110 160
nC di/dt
= 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Notes:
Pulse width
≤
300µs; duty cycle
≤
2%.
Repetitive rating;
pulse width limited by
max. junction temperature. ( See fig. 11 )
Starting T
J
= 25°C, L = 3.2mH
R
G
= 25
Ω
, I
AS
= -9.6A. (See Figure 12)
I
SD
≤
-9.6A, di/dt
≤
290A/µs, V
DD
≤
V
(BR)DSS
T
J
≤
150°C
ꢀ
This is applied for I-PAK, L
S
of D-PAK is measured between
lead and center of
die contact
,
** When
mounted on 1″ square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
IRFR/U5505
100
10
1
100
10
1
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
TOP
TOP
BOTTOM -4.5V
BOTTOM -4.5V
-4.5V
-4.5V
20µs PULSE WIDTH
T =
150 C
J
20µs PULSE WIDTH
°
°
T =
25
J
C
0.1
0.1
0.1
1
10
100
1
10
100
-V
DS
, Drain-to-Source Voltage (V)
-V
DS
, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
100
2.0
-16A
=
I
D
°
T =
25 C
J
1.5
1.0
0.5
0.0
°
T =
150 C
J
10
1
V
= -25V
DS
V
= -10V
20µs PULSE WIDTH
GS
0.1
4
5
6
7
8
9
10
-60 -40 -20
0
20 40 60 80
100 120 140 160
°
-V ,
Gate-to-Source Voltage (V)
GS
T ,
Junction Temperature (
C)
J
Fig 4.
Normalized On-Resistance
Fig 3.
Typical Transfer Characteristics
Vs. Temperature
IRFR/U5505
20
16
12
8
1200
I
D
= -9.6A
V
= 0V,
f = 1MHz
GS
C
= C
+ C
C
SHORTED
iss
gs
gd
ds
gd ,
ds
V
V
=-44V
=-28V
C
= C
= C
+ C
rss
DS
DS
1000
800
600
400
200
0
C
oss
gd
C
iss
C
C
oss
rss
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
1
10
10
0
10
20
30 40
-V ,
Drain-to-Source Voltage (V)
DS
Q ,
Total Gate Charge (nC)
G
Fig 5.
Typical Capacitance Vs.
Fig 6.
Typical Gate Charge Vs.
Drain-to-Source Voltage
Gate-to-Source Voltage
100
10
1
1000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
°
T =
150 C
J
100
10
1
10us
°
T =
25 C
J
100us
1ms
°
T =
25 C
C
J
°
T =
150 C
10ms
V
= 0 V
GS
1.8
Single Pulse
0.1
0.2
0.6
1.0
1.4
2.
1
10
100
-V ,Source-to-Drain
Voltage (V)
SD
-V ,
Drain-to-Source Voltage (V)
DS
Fig 7.
Typical Source-Drain Diode
Fig 8.
Maximum Safe Operating Area
Forward Voltage
IRFR/U5505
R
D
20
16
12
8
V
DS
V
GS
D.U.T.
R
G
–
+
V
DD
-10V
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
Fig 10a.
Switching Time Test Circuit
4
t
t
r
t
t
f
d(on)
d(off)
V
GS
10%
0
25
50
T
75
100
125
°
150
, Case Temperature
( C)
C
90%
V
DS
Fig 9.
Maximum Drain Current Vs.
Fig 10b.
Switching Time Waveforms
Case Temperature
10
D = 0.50
0.20
1
0.10
0.05
P
DM
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
0.1
t
1
t
2
Notes:
1. Duty factor D =
t /
t
1
2
2. Peak T
= P
x Z
+ T
C
J
DM
thJC
0.01
0.00001
0.0001
0.001
0.01
0.1
t ,
Rectangular Pulse Duration (sec)
1
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
IRFR/U5505
L
V
D S
350
300
250
200
150
100
50
I
D
TOP
-4.3A
-6.1A
BOTTOM -9.6A
–
+
D .U
.
T
AS
R
G
V
DD
I
A
D R IVER
-20V
0 .0 1
Ω
t
p
15V
Fig 12a.
Unclamped Inductive Test Circuit
I
AS
0
25
50
75
100
125
150
°
Starting T
, Junction Temperature
( C)
J
Fig 12c.
Maximum Avalanche Energy
Vs. Drain Current
t
p
V
(BR)DSS
Fig 12b.
Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.
T
.
50K
Ω
Q
G
.2
µ
F
12V
.3
µ
F
-10V
–
V
+
DS
Q
Q
GD
D.U.
T
.
GS
V
GS
V
G
-3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 13b.
Gate Charge Test Circuit
Fig 13a.
Basic Gate Charge Waveform
IRFR/U5505
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
D.U.T
*
–
+
–
–
+
R
G
•
dv/dt controlled by R
G
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
+
–
V
DD
V
GS
*
Reverse Polarity
of D.U.T for P-Channel
Driver Gate Drive
P
.
W.
Period
Period
D =
P.W.
V
[
=10V
] ***
GS
D.U.
T
. I
W
aveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
[
DD
]
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
[
]
SD
Ripple
≤
5%
***
V
GS
= 5.0V for Logic Level and 3V Drive Devices
Fig 14.
For P-Channel HEXFETS
IRFR/U5505
Package Outline
TO-252AA Outline
Dimensions are shown in millimeters (inches)
2.38 (.094)
2.19 (.086)
6.73 (.265)
6.35 (.250)
1
.
14 (.045)
0
.
89 (.035)
– A –
1.27 (.050)
0.88 (.035)
5.46 (.215)
5.21 (.205)
0.58 (.023)
0.46 (.018)
4
2
6.
4
5 (.245)
5.
6
8 (.224)
6.22 (.245)
5.97 (.235)
10.42 (.410)
9.
4
0 (.370)
1.02 (.040)
1.64 (.025)
LEAD ASS
I
G
NME
N
T
S
1 –
G
ATE
1
3
0.51 (.020)
MIN.
2 –
D
RA
I
N
– B –
3 –
S
O
UR CE
4 –
D
RA
I
N
1
.
52 (.060)
1
.
15 (.045)
0.89 (.035)
0.64 (.025)
3X
0.58 (.023)
0.46 (.018)
1.14 (.045)
0.76 (.030)
2X
0.25 (.010)
M A
M B
NOTES:
2.28 (.090)
1
2
3
4
D
I
M
E
NS
I
O
N
I
N
G & TOLERANC
I
N
G PER ANSI Y14
.
5M, 1982.
CONTROLL
I
N
G D
I
MEN
S
I
ON : INCH.
4.
5
7 (.180)
CONFORMS TO JEDEC OUTL
I
N
E TO-252AA.
D
I
M
E
NS
I
O
NS SHOWN ARE BEFORE SO
L
D
ER DI
P
,
SOLDER D
I
P M
A
X
. +0.16 (.006).
Part Marking Information
TO-252AA (D-Pak)
EXAM PLE
: THIS
IS AN IRFR120
W ITH
ASSEMBL Y
A
INTERNATIONAL
RECT IFIER
LOGO
LOT CODE 9U1P
FIRST PORTION
OF PART NUMBER
IRFR
12 0
9 U
1
P
ASSEMBL Y
SECOND PORTION
OF PART NUM
BER
L
O
T
CODE
IRFR/U5505
Package Outline
TO-251AA Outline
Dimensions are shown in millimeters (inches)
6.73 (.265)
6.35 (.250)
2.38 (.094)
2.19 (.086)
– A –
0.58 (.023)
0.46 (.018)
1.27 (.050)
5.46 (.215)
0.88 (.035)
5.21 (.205)
LEAD ASSIGNMENTS
1 –
G
ATE
4
2 –
D
RA
I
N
6.45 (.245)
5.68 (.224)
3 –
S
O
URCE
4 –
D
RA
I
N
6.22 (.245)
5.97 (.235)
1.52 (.060)
1.15 (.045)
1
2
3
– B –
NOTES:
1
2
3
4
D
I
M
E
NS
I
O
N
I
N
G & TOLERANC
I
N
G PER ANSI Y14
.
5M, 1982.
CONTROLL
I
N G
D
I
MEN
S
I
ON : INCH.
2.28 (.090)
1.91 (.075)
9.65 (.380)
8.89 (.350)
CONFORMS TO JEDEC O
U
T
L
I
N
E TO-252AA.
D
I
M
E
NS
I
O
NS SHOW
N ARE BEFORE SOLDER D
I
P
,
SOLDER D
I
P M
A
X
. +0.16 (.006).
1.14 (.045)
0.76 (.030)
1.14 (.045)
0.89 (.035)
3X
0.
8
9 (.035)
0.
6
4 (.025)
3X
0.25 (.010)
M A M
B
0.58 (.023)
0.46 (.018)
2.28 (.090)
2X
Part Marking Information
TO-251AA (I-Pak)
EXAM PLE
: THIS
IS AN IRF
U1 20
W ITH
ASSEM BLY
INTE RNATIONAL
RECTIFIER
LOGO
LOT CODE 9U1P
FIRST PORTION
OF PART NUM
BER
IRFU
120
9U 1
P
SECOND PORTION
OF PART NUM
BER
ASSEM BLY
LOT CODE
IRFR/U5505
T
a
pe & Reel Information
TO-252AA
T R
T R L
T R R
16 .3
( .64
1
15 .7
( .61
9
)
)
1 6 .3
( .6
4 1
1 5 .7
( .6
1 9
)
)
1 2 .1
(
.
4
76
1 1 .9
(
.
4
69
)
)
8 .1
(
.
3
1 8
7 .9
(
.
3
1 2
)
)
F
E
E D
D IR EC TIO N
F
E
E D
D IR EC TIO N
N O T
E
S
:
1 .
C O N T R O LL IN G
D IM EN S
I
O N
: M
I
L LIM ET ER .
2 .
A
L L
D IM E N SIO N S
AR E
S H O W N
IN M
I
L L IM
E
T E R S
(
I
N
C H
E
S
)
.
3 .
O U T L IN E
C O N FO R M S
TO E
I
A
–
48 1
& E
I
A
-5 4 1 .
1 3
IN C H
1 6
m m
N O T
E
S
:
1 .
O U T L IN E
C O N F O R M S
T O
E
IA-4 8 1 .
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
EUROPEAN HEADQUARTERS:
Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA:
7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897
IR GERMANY:
Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY:
Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR FAR EAST:
K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
IR SOUTHEAST ASIA:
315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371
Data and specifications subject to change without notice.
8/97
Note: For
the most current drawings please refer to the IR website at:
