Infineon-Technologies-IRFS3207TRLPBF
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PD – 95708D
IRFB3207PbF
IRFS3207PbF
IRFSL3207PbF
HEXFET
®
Power MOSFET
Applications
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
D
V
DSS
R
DS(on)
typ.
max.
75V
l
Hard Switched and High Frequency Circuits
3.6m
4.5m
170A
G
Benefits
S
I
D
l
Improved Gate,
Avalanche and Dynamic
dV/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
S
S
S
D
D
D
G
G
G
D
2
Pak
IRFS3207PbF
TO-262
IRFSL3207PbF
TO-220AB
IRFB3207PbF
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
Parameter
Continuous Drain Current, V
GS
@ 10V
Max.
170
Units
A
I
D
@ T
C
= 100°C
I
DM
Continuous Drain Current, V
GS
@ 10V
120
720
Pulsed Drain Current
P
D
@T
C
= 25°C
300
W
Maximum Power Dissipation
Linear Derating Factor
2.0
W/°C
V
V
GS
± 20
Gate-to-Source Voltage
5.8
Peak Diode Recovery
dV/dt
T
J
V/ns
°C
-55 to
+ 175
Operating Junction and
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
300
10lb in (1.1N m)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy
E
AS (Thermally limited)
910
mJ
A
Avalanche Current
I
AR
See Fig. 14, 15, 16a, 16b,
Repetitive Avalanche Energy
E
AR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.50
–––
62
Units
R
θ
Junction-to-Case
JC
CS
JA
JA
R
θ
R
θ
R
θ
0.50
–––
°C/W
Case-to-Sink, Flat Greased Surface , TO-220
Junction-to-Ambient, TO-220
Junction-to-Ambient (PCB Mount) , D
2
Pak
–––
40
1
03/06/06
IRF/B/S/SL3207PbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Min. Typ. Max.
Units
75 –––
–––
––– 0.069 –––
V/°C Reference
to 25°C, I
D
= 1mA
Conditions
V
GS
= 0V, I
D
= 250µA
V
∆
V
(BR)DSS
/
∆
T
J
R
DS(on)
–––
2.0
3.6
4.5
4.0
20
V
GS
= 10V, I
D
= 75A
m
Ω
V
V
GS(th)
–––
V
DS
= V
GS
, I
D
= 250µA
I
DSS
Drain-to-Source Leakage Current
––– –––
µA
V
V
V
V
DS
= 75V, V
GS
= 0V
DS
= 75V, V
GS
= 0V, T
J
= 125°C
GS
= 20V
––– ––– 250
––– ––– 200
––– –––
-200
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Input Resistance
nA
GS
= -20V
R
G
–––
1.2
–––
f = 1MHz, open drain
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Min. Typ. Max.
Units
Conditions
V
DS
= 50V, I
D
= 75A
150 ––– –––
S
Q
g
Total Gate Charge
––– 180 260
nC I
D
= 75A
V
DS
= 60V
Q
gs
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Turn-On Delay Time
–––
–––
–––
48
68
29
–––
–––
–––
Q
gd
V
GS
= 10V
t
d(on)
ns V
DD
= 48V
I
D
= 75A
t
r
Rise Time
––– 120 –––
t
d(off)
Turn-Off Delay Time
–––
–––
68
74
–––
–––
R =
2.6
Ω
G
V
GS
= 10V
t
f
Fall Time
C
iss
Input Capacitance
––– 7600 –––
––– 710 –––
––– 390 –––
––– 920 –––
––– 1010 –––
pF V
GS
= 0V
C
oss
Output Capacitance
V
DS
= 50V
ƒ = 1.0MHz
GS
= 0V, V
DS
= 0V to 60V
, See Fig.11
C
rss
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
C
oss
eff. (ER)
C
oss
eff. (TR)
V
V
GS
= 0V, V
DS
= 0V to 60V
, See Fig. 5
Diode Characteristics
Symbol
Parameter
Min. Typ. Max.
Units
Conditions
I
S
D
Continuous Source Current
––– –––
A
MOSFET symbol
170
(Body Diode)
showing the
G
I
SM
Pulsed Source Current
(Body Diode)
––– ––– 720
integral reverse
S
p-n junction diode.
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
––– –––
1.3
63
V
T
J
= 25°C, I
S
= 75A, V
GS
= 0V
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
V
R
= 64V,
–––
–––
–––
–––
–––
42
49
65
92
2.6
ns
I
F
= 75A
di/dt = 100A/µs
74
Q
rr
Reverse Recovery Charge
98
nC
140
–––
I
RRM
t
on
Reverse Recovery Current
Forward Turn-On Time
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
Calculated continuous current based on maximum allowable junction
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
temperature. Package limitation current is 75A.
Repetitive rating;
pulse width limited by max. junction
temperature.
.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.33mH
R
G
= 25
Ω
, I
AS
= 75A, V
GS
=10V. Part not recommended for use
above this value.
When mounted on 1″ square PCB (FR-4 or G-10 Material).
For recommended
footprint and soldering techniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C.
I
SD
≤
75A, di/dt
≤
500A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
ꢀ
Pulse width
≤
400µs; duty cycle
≤
2%.
2
IRF/B/S/SL3207PbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
4.5V
1
60µs PULSE WIDTH
60µs PULSE WIDTH
Tj = 25°C
≤
≤
Tj = 175°C
1
0.1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
2.5
2.0
1.5
1.0
0.5
1000.0
100.0
10.0
I
= 75A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
J
V
= 50V
DS
≤
60µs PULSE WIDTH
1.0
4.0
5.0
6.0
7.0
8.0
9.0
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
V
, Gate-to-Source Voltage (V)
GS
T
, Junction Temperature (°C)
J
Fig 4.
Normalized On-Resistance vs. Temperature
Fig 3.
Typical Transfer Characteristics
12000
10000
8000
6000
4000
2000
0
20
V
= 0V,
f = 1 MHZ
GS
I =
75A
D
V
= 60V
C
= C
+ C
, C
SHORTED
DS
iss
gs
gd ds
VDS= 38V
C
= C
rss
gd
16
12
8
C
= C
+ C
ds
oss
gd
Ciss
4
Coss
Crss
0
0
40
80
120 160 200 240 280
1
10
100
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
3
IRF/B/S/SL3207PbF
1000.0
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
100.0
10.0
1.0
100µsec
T
= 25°C
J
1msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
10msec
DC
V
= 0V
GS
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
, Source-to-Drain Voltage (V)
0.1
0.1
1
10
100
1000
V
, Drain-toSource Voltage (V)
V
DS
SD
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
100
90
200
150
100
50
Limited By Package
80
70
0
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
25
50
75
100
125
150
175
T
, Junction Temperature (°C)
J
T
, Case Temperature (°C)
C
Fig 9.
Maximum Drain Current vs.
Fig 10.
Drain-to-Source Breakdown Voltage
Case Temperature
4000
3.0
2.5
2.0
1.5
1.0
0.5
0.0
I
D
TOP
12A
16A
75A
3000
2000
1000
0
BOTTOM
25
50
75
100
125
150
175
20
30
V
40
50
60
70
80
Starting T
, Junction Temperature (°C)
Drain-to-Source Voltage (V)
J
DS,
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy Vs. DrainCurrent
4
IRF/B/S/SL3207PbF
1
0.1
D = 0.50
0.20
0.10
R
1
R
1
R
2
R
2
0.05
Ri (°C/W)
τ
i (sec)
0.2151 0.001175
τ
0.01
J
τ
J
τ
0.02
0.01
τ
C
τ
1
τ
1
Ci=
τ
i
/
Ri
τ
2
τ
2
0.2350 0.017994
0.001
0.0001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆
Tj = 150°C and
Tstart =25°C (Single Pulse)
Duty Cycle = Single Pulse
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assumin
g
∆Τ
j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
1000
800
600
400
200
0
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as neither T
jmax
nor I
av (max)
is exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆
T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche =
t
av
·f
TOP
BOTTOM 1%
Duty Cycle
= 75A
Single Pulse
I
D
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
25
50
75
100
125
150
175
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
Starting T
, Junction Temperature (°C)
J
I
av
= 2
D
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Fig 15.
Maximum Avalanche Energy vs. Temperature
5
IRF/B/S/SL3207PbF
16
14
12
10
8
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
I
I
I
= 1.0A
D
D
D
= 1.0mA
= 250µA
I
= 30A
6
F
V
T
= 64V
R
4
= 125°C
= 25°C
J
T
J
2
-75 -50 -25
0
J
25 50 75
100 125 150 175
, Temperature ( °C )
100 200 300 400 500 600 700 800 900
1000
T
di /
dt – (A / µs)
f
Fig. 17
– Typical Recovery Current vs. di
f
/dt
Fig 16.
Threshold Voltage Vs. Temperature
16
14
12
10
8
400
300
200
I
= 45A
= 64V
I
= 30A
= 64V
6
4
2
F
F
100
0
V
T
V
T
R
R
= 125°C
= 25°C
= 125°C
= 25°C
J
J
T
T
J
J
100 200 300 400 500 600 700 800 900
1000
100 200 300 400 500 600 700 800 900
1000
di /
dt – (A / µs)
f
di /
dt – (A / µs)
f
Fig. 18
– Typical Recovery Current vs. di
f
/dt
Fig. 19
– Typical Stored Charge vs. di
f
/dt
400
300
200
100
0
I
= 45A
= 64V
F
V
T
R
= 125°C
= 25°C
J
T
J
100 200 300 400 500 600 700 800 900
1000
di /
dt – (A / µs)
f
Fig. 20
– Typical Stored Charge vs. di
f
/dt
6
IRF/B/S/SL3207PbF
Driver Gate Drive
P.W.
P
.
W.
D =
D.U.T
Period
Period
+
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
–
+
di/dt
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Current
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 21.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
V
2
GS
Ω
0.01
t
p
I
AS
Fig 22b.
Unclamped Inductive Waveforms
Fig 22a.
Unclamped Inductive Test Circuit
L
D
V
DS
V
DS
90%
+
–
V
DD
10%
V
GS
D.U.T
V
GS
Pulse Width < 1µs
Duty Factor < 0.1%
t
d(on)
t
d(off)
t
r
t
f
Fig 23a.
Switching Time Test Circuit
Fig 23b.
Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
Vgs(th)
0
1K
Qgs1
Qgs2
Qgd
Qgodr
Fig 24a.
Gate Charge Test Circuit
Fig 24b.
Gate Charge Waveform
7
IRF/B/S/SL3207PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
TO-220AB packages are not recommended for Surface Mount Application.
8
IRF/B/S/SL3207PbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
9
IRF/B/S/SL3207PbF
D
2
Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D
2
Pak (TO-263AB) Part Marking Information
10
IRF/B/S/SL3207PbF
D
2
Pak (TO-263AB)
T
a
pe & Reel Information
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS
TO EIA-418.
2. CONTROLLING
DIMENSION: MILLIMETER.
3. DIMENSION
MEASURED @ HUB.
26.40 (1.039)
24.40 (.961)
4
3
4. INCLUDES
FLANGE DISTORTION @ OUTER EDGE.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
11
Note: For
the most current drawings please refer to the IR website at:
