Infineon-Technologies-IRFS4115TRLPBF
| Part # | Infineon-Technologies-IRFS4115TRLPBF |
Download  | Infineon-Technologies-IRFS4115TRLPBF |
PD – 96198A
IRFS4115PbF
IRFSL4115PbF
HEXFET
®
Power MOSFET
Applications
l
High Efficiency Synchronous Rectification in SMPS
D
V
DSS
R
DS(on)
typ.
150V
10.3m
12.1m
99A
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
max.
G
I
D
(Silicon Limited)
Benefits
I
D
(Package Limited)
195A
S
l
Improved Gate,
Avalanche and Dynamic
dV/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
D
SOA
D
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
S
S
D
G
G
D
2
Pak
IRFS4115PbF
TO-262
IRFSL4115PbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
D
@ T
C
= 25°C
I
DM
Parameter
Max.
99
Units
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Wire Bond Limited)
Pulsed Drain Current
70
A
195
396
375
2.5
P
D
@T
C
= 25°C
W
Maximum Power Dissipation
Linear Derating Factor
W/°C
V
V
GS
± 20
18
Gate-to-Source Voltage
Peak Diode Recovery
dv/dt
T
J
V/ns
-55 to
+ 175
Operating Junction and
T
STG
Storage Temperature Range
°C
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
10lb in (1.1N m)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy
E
AS (Thermally limited)
830
mJ
A
Avalanche Current
I
AR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy
E
AR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.4
Units
R
θ
Junction-to-Case
JC
°C/W
R
θ
JA
–––
40
Junction-to-Ambient
1
03/09/11
IRFS/SL4115PbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
Parameter
Min. Typ. Max.
Units
Conditions
V
GS
= 0V, I
D
= 250
μ
A
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
150 ––– –––
V
Reference to 25°C, I
D
= 3.5mA
V
GS
= 10V, I
D
= 62A
V /
T
(BR)DSS
Δ
Δ
––– 0.18 ––– V/°C
J
R
DS(on)
V
GS(th)
I
DSS
––– 10.3 12.1
m
Ω
V
V
DS
= V
GS
, I
D
= 250
μ
A
V
DS
= 150V, V
GS
= 0V
V
DS
= 150V, V
GS
= 0V, T
J
= 125°C
V
GS
= 20V
3.0
–––
5.0
20
Drain-to-Source Leakage Current
––– –––
μ
A
––– ––– 250
––– ––– 100
––– –––
-100
I
GSS
R
G
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
nA
V
GS
= -20V
–––
2.3
–––
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Conditions
V
DS
= 50V, I
D
= 62A
Symbol
gfs
Q
g
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max.
Units
97
––– –––
S
I
D
= 62A
–––
–––
–––
–––
–––
–––
–––
–––
77
28
26
51
18
73
41
39
120
–––
–––
–––
–––
–––
–––
–––
nC
V
DS
= 75V
Q
gs
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Total Gate Charge Sync. (Q
g
– Q
gd
)
Turn-On Delay Time
V
GS
= 10V
Q
gd
I
D
= 62A, V
DS
=0V, V
GS
= 10V
V
DD
= 98V
Q
sync
t
d(on)
ns
I
D
= 62A
t
r
Rise Time
t
d(off)
R
G
= 2.2
Ω
V
GS
= 10V
Turn-Off Delay Time
t
f
Fall Time
V
GS
= 0V
C
iss
Input Capacitance
––– 5270 –––
––– 490 –––
––– 105 –––
pF
V
DS
= 50V
C
oss
Output Capacitance
C
rss
ƒ = 1.0 MHz,
See Fig. 5
V
GS
= 0V, V
DS
= 0V to 120V
, See Fig. 11
V
GS
= 0V, V
DS
= 0V to 120V
Reverse Transfer Capacitance
C
oss
eff. (ER)
C
oss
eff. (TR)
Effective Output Capacitance (Energy Related)
––– 460 –––
Effective Output Capacitance (Time Related)
––– 530 –––
Diode Characteristics
Conditions
Symbol
Parameter
Min. Typ. Max.
Units
D
I
S
MOSFET symbol
Continuous Source Current
––– –––
99
A
showing the
(Body Diode)
G
I
SM
integral reverse
p-n junction diode.
Pulsed Source Current
(Body Diode)
––– ––– 396
A
S
T
J
= 25°C, I
S
= 62A, V
GS
= 0V
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
––– –––
––– 86
1.3
V
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
V
R
= 130V,
I
F
= 62A
–––
ns
––– 110 –––
––– 300 –––
––– 450 –––
Q
rr
Reverse Recovery Charge
nC
A
di/dt = 100A/
μ
s
I
RRM
t
on
Reverse Recovery Current
Forward Turn-On Time
–––
6.5
–––
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 195A. Note that current
limitations arising from heating of the device leads may occur with
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
some lead mounting arrangements.
(Refer to AN-1140)
Repetitive rating;
pulse width limited by max. junction
temperature.
Recommended max EAS limit, starting T
J
= 25°C,
L = 0.17mH, R
G
= 25
Ω
, I
AS
= 100A, V
GS
=15V.
I
SD
≤
62A, di/dt
≤
1040A/
μ
s, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
ꢀ
Pulse width
≤
400
μ
s; duty cycle
≤
2%.
.
When mounted on 1″ square PCB (FR-4 or G-10 Material).
For recom
mended footprint and soldering techniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C.
R
θ
JC
value shown is at time zero.
2
IRFS/SL4115PbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
5.0V
VGS
15V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
5.0V
TOP
TOP
BOTTOM
BOTTOM
5.0V
1
60
μ
s PULSE WIDTH
Tj = 175°C
≤
5.0V
60
μ
s PULSE WIDTH
Tj = 25°C
≤
1
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
100
10
3.0
2.5
2.0
1.5
1.0
0.5
I
= 62A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
J
1
V
= 50V
DS
≤
60
μ
s PULSE WIDTH
0.1
2
4
6
8
10 12 14 16
-60 -40 -20
0 20
40 60 80
100120140160180
, Junction Temperature (°C)
T
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4.
Normalized On-Resistance vs. Temperature
Fig 3.
Typical Transfer Characteristics
100000
10000
1000
100
14.0
V
= 0V,
= C
f = 1 MHZ
GS
I =
62A
D
C
C
C
+ C
, C
SHORTED
ds
iss
gs
gd
V
V
V
= 120V
= 75V
= 30V
DS
DS
DS
12.0
10.0
8.0
= C
rss
oss
gd
= C
+ C
ds
gd
C
iss
C
oss
6.0
C
rss
4.0
2.0
10
0.0
1
10
100
1000
0
20
40
60
80
100
V
, Drain-to-Source Voltage (V)
Q ,
Total Gate Charge (nC)
DS
G
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFS/SL4115PbF
1000
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
100
10
1
J
100
μ
sec
1msec
DC
T
J
= 25°C
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
3.0
GS
0.1
1
0.0
0.5
V
1.0
1.5
2.0
2.5
3.5
1
10
100
1000
, Source-to-Drain Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
SD
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
200
190
180
170
160
150
140
120
100
80
60
40
20
0
Id = 3.5mA
-60 -40 -20
0 20
40 60 80
100120140160180
25
50
75
100
125
150
175
T
, Temperature ( °C )
T
, Case Temperature (°C)
J
C
Fig 9.
Maximum Drain Current vs.
Fig 10.
Drain-to-Source Breakdown Voltage
Case Temperature
6.0
5.0
4.0
3.0
2.0
1.0
0.0
6.0
5.0
4.0
3.0
2.0
1.0
I
I
I
= 250
μ
A
= 1.0mA
= 1.0A
D
D
D
-20
0
20 40 60 80
100 120 140 160
Drain-to-Source Voltage (V)
-75 -50 -25
0
25 50 75
100 125 150 175
T ,
Temperature ( °C )
J
V
DS,
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Threshold Voltage vs. Temperature
4
IRFS/SL4115PbF
1
0.1
D = 0.50
0.20
0.10
0.05
R
1
R
1
R
2
R
2
Ri (°C/W)
τ
i (sec)
0.01
0.02
0.01
τ
τ
J
τ
J
C
τ
C
0.245
0.0059149
τ
τ
1
τ
1
2
τ
2
0.155
0.0006322
C
i
=
τ
i
/
R
i
Ci =
τ
i
/
Ri
0.001
0.0001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig. 13
Maximum Effective Transient Thermal Impedance, Junction-to-Case
50
50
40
30
20
10
0
I =
62A
F
I =
42A
F
V
= 130V
V
= 130V
R
R
40
30
20
10
0
T =
25°C
T =
25°C
J
J
T =
125°C
J
T =
125°C
J
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt
(A/
μ
s)
di /dt
(A/
μ
s)
F
F
Fig. 15
– Typical Recovery Current vs. di
f
/dt
Fig. 14
– Typical Recovery Current vs. di
f
/dt
2500
3000
I =
42A
I =
62A
F
F
V
= 130V
V
= 130V
R
R
2000
1500
1000
500
0
2400
1800
1200
600
0
T =
25°C
T =
25°C
J
J
T =
125°C
J
T =
125°C
J
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt
(A/
μ
s)
di /dt
(A/
μ
s)
F
F
Fig. 16
– Typical Stored Charge vs. di
f
/dt
Fig. 17
– Typical Stored Charge vs. di
f
/dt
5
IRFS/SL4115PbF
Driver Gate Drive
P.W.
P
.
W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Current
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 18.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
V
2
GS
Ω
0.01
t
p
I
AS
Fig 19b.
Unclamped Inductive Waveforms
Fig 19a.
Unclamped Inductive Test Circuit
R
D
V
DS
V
DS
90%
V
GS
D.U.T.
R
G
+
V
DD
–
V
GS
10%
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 20a.
Switching Time Test Circuit
Fig 20b.
Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.
T
.
Vds
Vgs
50K
Ω
.2
μ
F
12V
.3
μ
F
+
V
DS
D.U.
T
.
–
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 21a.
Gate Charge Test Circuit
Fig 21b.
Gate Charge Waveform
6
IRFS/SL4115PbF
D
2
Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D
2
Pak (TO-263AB) Part Marking Information
7
IRFS/SL4115PbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
8
IRFS/SL4115PbF
D
2
Pak (TO-263AB)
T
a
pe & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS
TO EIA-418.
2. CONTROLLING
DIMENSION: MILLIMETER.
3. DIMENSION
MEASURED @ HUB.
4. INCLUDES
FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
9
