Infineon-Technologies-IRFS4620TRLPBF
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PD –
96203
IRFS4620PbF
IRFSL4620PbF
HEXFET
®
Power MOSFET
Applications
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
D
V
DSS
R
DS(on)
typ.
200V
63.7m
77.5m
24A
G
max.
l
Hard Switched and High Frequency Circuits
I
D
S
Benefits
l
Improved Gate,
Avalanche and Dynamic
dV/dt
D
D
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
S
D
S
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
G
G
D
2
Pak
IRFS4620PbF
TO-262
IRFSL4620PbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
Parameter
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Max.
24
Units
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
17
A
100
P
D
@T
C
= 25°C
W
144
Maximum Power Dissipation
Linear Derating Factor
0.96
W/°C
V
V
GS
± 20
Gate-to-Source Voltage
54
Peak Diode Recovery
dv/dt
T
J
V/ns
-55 to
+ 175
Operating Junction and
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
°C
300
Avalanche Characteristics
Single Pulse Avalanche Energy
E
AS (Thermally limited)
113
mJ
A
Avalanche Current
I
AR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy
E
AR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
1.045
40
Units
R
θ
JC
Junction-to-Case
°C/W
R
θ
JA
–––
Junction-to-Ambient (PCB Mount)
1
12/18/08
IRFS/SL4620PbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Min. Typ. Max.
Units
200 ––– –––
––– 0.23 –––
V/°C Reference
to 25°C, I
D
= 5mA
Conditions
V
GS
= 0V, I
D
= 250µA
V
∆
V
(BR)DSS
/
∆
T
J
R
DS(on)
––– 63.7 77.5
V
GS
= 10V, I
D
= 15A
m
Ω
V
GS(th)
3.0
–––
5.0
20
V
V
DS
= V
GS
, I
D
= 100µA
I
DSS
Drain-to-Source Leakage Current
––– –––
V
DS
= 200V, V
GS
= 0V
µA
––– ––– 250
––– ––– 100
––– ––– -100
V
DS
= 200V, V
GS
= 0V, T
J
= 125°C
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
V
GS
= 20V
nA
V
GS
= -20V
R
G(int)
–––
2.6
–––
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Min. Typ. Max.
Units
Conditions
V
DS
= 50V, I
D
= 15A
37
––– –––
S
Q
g
Total Gate Charge
–––
–––
–––
–––
25
8.2
7.9
17
38
I
D
= 15A
Q
gs
Q
gd
Q
sync
t
d(on)
t
r
Gate-to-Source Charge
–––
–––
–––
V
DS
= 100V
nC
Gate-to-Drain (“Miller”) Charge
Total Gate Charge Sync. (Q
g
– Q
gd
)
V
GS
= 10V
I
D
= 15A, V
DS
=0V, V
GS
= 10V
V
DD
= 130V
Turn-On Delay Time
––– 13.4 –––
––– 22.4 –––
––– 25.4 –––
––– 14.8 –––
––– 1710 –––
––– 125 –––
Rise Time
I
D
= 15A
ns
t
d(off)
t
f
Turn-Off Delay Time
R
G
= 7.3
Ω
V
GS
= 10V
Fall Time
C
iss
C
oss
C
rss
Input Capacitance
V
GS
= 0V
Output Capacitance
V
DS
= 50V
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
–––
30
–––
ƒ = 1.0MHz
(See Fig.5)
pF
C
oss
eff. (ER)
oss
eff. (TR)
––– 113 –––
––– 317 –––
V
GS
= 0V, V
DS
= 0V to 160V
(See Fig.11)
GS
= 0V, V
DS
= 0V to 160V
C
V
Diode Characteristics
Symbol
Parameter
Continuous Source Current
Min. Typ. Max.
Units
Conditions
MOSFET symbol
I
S
D
S
––– –––
24
(Body Diode)
showing the
A
G
I
SM
Pulsed Source Current
(Body Diode)
integral reverse
––– ––– 100
p-n junction diode.
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
––– –––
1.3
–––
–––
V
T
J
= 25°C, I
S
= 15A, V
GS
= 0V
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
V
R
= 100V,
I
F
= 15A
di/dt = 100A/µs
–––
–––
78
99
ns
Q
rr
Reverse Recovery Charge
––– 294 –––
––– 432 –––
nC
A
I
RRM
t
on
Reverse Recovery Current
Forward Turn-On Time
–––
7.6
–––
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating;
pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 1.0mH
R
G
= 25
Ω
, I
AS
= 15A, V
GS
=10V. Part not recommended for use
above this value .
I
SD
≤
15A, di/dt
≤
634A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
Pulse width
≤
400µs; duty cycle
≤
2%.
ꢀ
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
.
When mounted on 1″ square PCB (FR-4 or G-10 Material).
For recom
mended footprint and soldering techniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C
2
IRFS/SL4620PbF
1000
100
10
1000
100
10
VGS
15V
12V
VGS
15V
12V
TOP
TOP
10V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
BOTTOM
5.0V
1
5.0V
1
0.1
0.01
60µs PULSE WIDTH
Tj = 175°C
≤
60µs PULSE WIDTH
Tj = 25°C
≤
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
100
10
3.5
3.0
2.5
2.0
1.5
1.0
0.5
I
= 15A
D
V
= 10V
GS
T =
175°C
J
T
= 25°C
J
1
V
= 50V
DS
≤
60µs PULSE WIDTH
0.1
2
4
6
8
10
12
14
16
-60 -40 -20
0 20
40 60 80
100120140160180
, Junction Temperature (°C)
T
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4.
Normalized On-Resistance vs. Temperature
Fig 3.
Typical Transfer Characteristics
14.0
100000
10000
1000
100
V
= 0V,
= C
f = 1 MHZ
GS
I =
15A
D
C
C
C
+ C
, C
SHORTED
ds
iss
gs
gd
V
= 160V
= 100V
12.0
10.0
8.0
DS
= C
rss
oss
gd
V
DS
= C
+ C
ds
gd
VDS= 40V
C
iss
6.0
C
oss
4.0
C
rss
2.0
0.0
10
0
5
10
15
20
25
30
35
1
10
100
1000
Q ,
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFS/SL4620PbF
1000
100
10
100
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
100µsec
T
= 175°C
1msec
J
T
= 25°C
J
10
10msec
DC
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
1.4
GS
0.1
1.0
1
10
100
1000
0.2
0.4
V
0.6
0.8
1.0
1.2
1.6
V
, Drain-to-Source Voltage (V)
, Source-to-Drain Voltage (V)
DS
SD
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
260
250
240
230
220
210
200
190
30
Id = 5mA
25
20
15
10
5
0
-60 -40 -20
0 20
40 60 80
100120140160180
25
50
75
100
125
150
175
T ,
Temperature ( °C )
J
Fig 10.
Drain-to-Source Breakdown Voltage
T
, Case Temperature (°C)
Fig 9.
Max
i
C
mum Drain Current vs.
Case Temperature
3.0
500
I
D
450
400
350
300
250
200
150
100
50
TOP
2.05A
2.94A
BOTTOM 15A
2.5
2.0
1.5
1.0
0.5
0.0
0
-50
0
50
100
150
200
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
V
Drain-to-Source Voltage (V)
J
DS,
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy vs. DrainCurrent
4
IRFS/SL4620PbF
10
1
D = 0.50
0.20
0.10
0.05
R
1
R
1
R
2
R
2
Ri (°C/W)
τ
i (sec)
0.1
τ
J
τ
J
τ
0.456
0.000311
τ
C
τ
1
τ
1
Ci=
τ
i
/
Ri
τ
0.589
0.003759
0.02
0.01
2
τ
2
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
10
1
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆
Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Τ
j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
120
100
80
60
40
20
0
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆
T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche =
t
av
·f
TOP
BOTTOM 1.0%
Duty Cycle
= 15A
Single Pulse
I
D
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
25
50
75
100
125
150
175
I
av
= 2
D
T/ [1.3·BV·Z
th
]
Starting T
, Junction Temperature (°C)
E
AS (AR)
= P
D (ave)
·t
av
J
Fig 15.
Maximum Avalanche Energy vs. Temperature
5
IRFS/SL4620PbF
6.0
5.5
5.0
4.5
4.0
3.5
90
80
70
60
50
40
30
20
10
0
I =
10A
F
V
= 100V
R
T =
25°C
J
T =
125°C
J
I
I
= 100µA
= 250uA
D
D
3.0
2.5
2.0
1.5
1.0
ID = 1.0mA
ID = 1.0A
-75 -50 -25
0
25 50 75
100 125 150 175
0
200
400
600
800
1000
T ,
Temperature ( °C )
J
di /dt
(A/µs)
F
Fig. 17
– Typical Recovery Current vs. di
f
/dt
Fig 16.
Threshold Voltage vs. Temperature
90
2000
I =
10A
I =
15A
F
F
80
70
60
50
40
30
20
10
0
1800
1600
1400
1200
1000
800
V
= 100V
V
= 100V
R
R
T =
25°C
T =
25°C
J
J
T =
125°C
J
T =
125°C
J
600
400
200
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt
(A/µs)
di /dt
(A/µs)
F
F
Fig. 18
– Typical Recovery Current vs. di
f
/dt
Fig. 19
– Typical Stored Charge vs. di
f
/dt
2000
I =
15A
F
V
1800
1600
1400
1200
1000
800
= 100V
R
T =
25°C
J
T =
125°C
J
600
400
200
0
200
400
600
800
1000
di /dt
(A/µs)
F
Fig. 20
– Typical Stored Charge vs. di
f
/dt
6
IRFS/SL4620PbF
Driver Gate Drive
P.W.
P
.
W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Current
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 21.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
V
2
GS
Ω
0.01
t
p
I
AS
Fig 22b.
Unclamped Inductive Waveforms
Fig 22a.
Unclamped Inductive Test Circuit
R
D
V
DS
V
DS
90%
V
GS
D.U.T.
R
G
+
V
DD
–
V
GS
10%
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a.
Switching Time Test Circuit
Fig 23b.
Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.
T
.
Vds
Vgs
50K
Ω
.2
µ
F
12V
.3
µ
F
+
V
DS
D.U.
T
.
–
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a.
Gate Charge Test Circuit
Fig 24b.
Gate Charge Waveform
7
IRFS/SL4620PbF
D
2
Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D
2
Pak (TO-263AB) Part Marking Information
8
IRFS/SL4620PbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
9
IRFS/SL4620PbF
D
2
Pak (TO-263AB)
T
a
pe & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS
TO EIA-418.
2. CONTROLLING
DIMENSION: MILLIMETER.
3. DIMENSION
MEASURED @ HUB.
4. INCLUDES
FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
10
