Infineon-Technologies-IRFS7434TRL7PP

Part #Infineon-Technologies-IRFS7434TRL7PP
Download 
Infineon-Technologies-IRFS7434TRL7PP
Strong
IR
FET™  
IRFS7434-7PPbF  
Application  
HEXFET

®

Power MOSFET  
Brushed Motor drive applications  
BLDC Motor drive applications  

Battery powered circuits  
V

DSS  

40V  
Half-bridge and full-bridge topologies  
Synchronous rectifier applications  
Resonant mode power supplies  
OR-ing and redundant power switches  
DC/DC and AC/DC converters  
DC/AC Inverters  
R

DS(on) typ.  

0.70m
  
1.0m
  
362A
 
max  
I

D (Silicon Limited)  

I

D (Package Limited)  

240A  
Benefits  
Improved Gate,
 
Avalanche and Dynamic dV/dt Ruggedness  
Fully Characterized Capacitance and Avalanche SOA  
Enhanced body diode dV/dt and dI/dt Capability  
Lead-Free, RoHS Compliant  
G
D
S
Gate  
Drain  
Source  
Standard Pack  
Form  
Tube  
Base part number  
Package Type  
Orderable Part Number  
Quantity  
50  
IRFS7434-7PPbF  
IRFS7434TRL7PP  
IRFS7434-7PPbF  
D

2

Pak-7Pin  
Tape and Reel Left  
800  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
400  
350  
300  
250  
200  
150  
100  
50  
Limited By
 
Package  
I
= 100A  
D
T
T
= 125°C  
= 25°C  
J
J
0
4
6
8
10 12 14 16 18 20  
25  
50  
75  
100  
125  
150  
T
, Case Temperature (°C)  
C
V
Gate -to -Source Voltage
 
(V)  
GS,  
Fig 2.
 
Maximum Drain Current vs. Case Temperature  
Fig 1.
 
Typical On-Resistance vs. Gate Voltage  
1
© 2014 International Rectifier  
November 19, 2014  

IRFS7434-7PPbF  
Absolute Maximium Rating  
Symbol  
Parameter  
Max.  
362
 
229
  
Units  
I

D

@ T

C

= 25°C  
Continuous Drain Current, V

GS

@ 10V (Silicon Limited)  
I

D

@ T

C

= 100°C
 
Continuous Drain Current, V

GS

@ 10V (Silicon Limited)  
A
I

D

@ T

C

= 25°C  
I

DM  

Continuous Drain Current, V

GS

@ 10V (Wire Bond Limited)  
Pulsed Drain Current
  
240  
1300*
  
245  
P

D

@T

C

= 25°C  
Maximum Power Dissipation  
W
W/°C  
V
Linear Derating Factor  
1.96  
V

GS  

Gate-to-Source Voltage  
± 20  
T

J  

T

STG  

Operating Junction and  
Storage Temperature Range  
Soldering Temperature, for 10 seconds (1.6mm from case)  
-55 to
 
+ 150  
300  
°C  
Avalanche Characteristics  
E

AS (Thermally limited)  

E

AS (Thermally limited)  

I

AR  

E

AR  

384  
880  
Single Pulse Avalanche Energy
  
Single Pulse Avalanche Energy
 
  
Avalanche Current
  
mJ  
A
mJ  
See Fig 15, 16, 23a, 23b  
Repetitive Avalanche Energy
  
Thermal Resistance  
Symbol  
Parameter  
Typ.  
–––  
–––  
Max.  
0.51  
40  
Units  
°C/W  
Junction-to-Case
  
Junction-to-Ambient
  
R

JC  

R

JA  

Static @ T

J

= 25°C (unless otherwise specified)  
Symbol  
V

(BR)DSS  

Parameter  
Drain-to-Source Breakdown Voltage  
Breakdown Voltage Temp. Coefficient  
Min. Typ.
 
Max. Units  
40 –––
 
–––  
––– 0.03 ––– V/°C
 
Reference to 25°C, I

D

= 1mA
  
Conditions  
V

GS

= 0V, I

D

= 250µA  
V
V

(BR)DSS

/
T

J  

–––  
–––  
2.2  
0.7  
1.5  
3.0  
1.0  
–––  
3.9  
1.0  
V
V

GS

= 10V, I

D

= 100A
  

GS

= 6V, I

D

= 50A
  
R

DS(on)  

Static Drain-to-Source On-Resistance  
Gate Threshold Voltage  
m
  
V
V

GS(th)  

V

DS

= V

GS

, I

D

= 250µA  

DS

=40 V, V

GS

= 0V  
V

DS

=40V,V

GS

= 0V,T

J

=125°C  
––– –––  
V
I

DSS  

Drain-to-Source Leakage Current  
µA  
––– ––– 150  
––– ––– 100  
––– –––
 
-100  
Gate-to-Source Forward Leakage  
Gate-to-Source Reverse Leakage  
Gate Resistance  
V
V

GS

= 20V  

GS

= -20V  
I

GSS  

nA  
R

G  

–––  
2.0  
–––  
  
Notes:  
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 240A by  
source bonding technology. Note that current limitations arising from heating of the device leads may occur with  
some lead mounting arrangements. (Refer to AN-1140)  
Repetitive rating; pulse width limited by max. junction temperature.  
Limited by T

Jmax

, starting T

J

= 25°C, L = 0.077mH, R

G

= 50
, I

AS

= 100A, V

GS

=10V.  
I

SD

100A, di/dt
969A/µs, V

DD

V

(BR)DSS

, T

J


150°C.  
Pulse width
400µs; duty cycle
2%.  
C

oss

eff. (TR) is a fixed capacitance that gives the same charging time as C

oss

while V

DS

is rising from 0 to 80% V

DSS  

.
C

oss

eff. (ER) is a fixed capacitance that gives the same energy as C

oss

while V

DS

is rising from 0 to 80% V

DSS  

.
R

is measured at T

J

approximately 90°C.  
Limited by T

Jmax

, starting T

J

= 25°C, L = 1mH, R

G

= 50
, I

AS

= 42A, V

GS

=10V.  
When mounted on 1″ square PCB (FR-4 or G-10 Material).
Please refer to AN-994 for more details:  
*
Pulse drain current is limited by source bonding technology.  
2
© 2014 International Rectifier  
November 19, 2014  

IRFS7434-7PPbF  
Dynamic Electrical
 
Characteristics @ T

J

= 25°C (unless otherwise specified)  
Symbol  
gfs  
Parameter  
Forward Transconductance  
Total Gate Charge  
Min. Typ.
 
Max. Units  
Conditions  
V

DS

= 10V, I

D

=100A  
I

D

= 100A  
156 –––  
––– 210  
––– 55  
––– 66  
––– 144  
––– 23  
––– 125  
–––  
315  
–––  
–––  
–––  
–––  
–––  
S
Q

g  

Q

gs  

Gate-to-Source Charge  
Gate-to-Drain Charge  
Total Gate Charge Sync. (Qg– Qgd)  
Turn-On Delay Time  
V

DS

= 20V  
nC  
Q

gd  

V

GS

= 10V  
Q

sync  

t

d(on)  

t

r  

V

DD

= 26V  
I

D

= 100A  
Rise Time  
ns  
t

d(off)  

t

f  

Turn-Off Delay Time  
Fall Time  
––– 107  
––– 85  
–––  
–––  
R

G

= 2.6
  
V

GS

= 10V
  
C

iss  

C

oss  

C

rss  

Input Capacitance  
Output Capacitance  
Reverse Transfer Capacitance  
––– 10250
 
–––  
––– 1540
 
–––  
––– 1060
 
–––  
V

GS

= 0V  
V

DS

= 25V  
ƒ = 1.0MHz,
 
See Fig.7  
pF  
V

GS

= 0V, VDS = 0V to 32V
  
C

oss eff.(ER)
 

Effective Output Capacitance (Energy Related)
 
––– 1880
 
–––  
See Fig.11  
C

oss eff.(TR)
 

Output Capacitance (Time Related)  
––– 2147
 
–––  
V

GS

= 0V, VDS = 0V to 32V
  
Diode Characteristics  
Symbol  
I

S  

Parameter  
Continuous Source Current  
(Body Diode)
  
Pulsed Source Current  
(Body Diode)
  
Min. Typ.
 
Max. Units  
Conditions  
MOSFET symbol  
D
––– ––– 362
  
A
––– ––– 1300*
  
showing the  
G
integral reverse  
p-n junction diode.  
I

SM  

S
V

SD  

Diode Forward Voltage  
––– 0.9  
1.3  
V
T

J

= 25°C,I

S

= 100A,V

GS

= 0V
  
dv/dt  
Peak Diode Recovery dv/dt
  
––– 3.0  
––– 44  
––– 46  
––– 43  
––– 44  
––– 1.9  
––– V/ns
 
T

J

= 150°C,I

S

=100A,V

DS

= 40V
  
–––  
–––  
–––  
–––  
–––  
T

J

= 25°C  
V

DD

= 34V  
I

F

= 100A,  
t

rr  

Reverse Recovery Time  
ns  
T

J

= 125°C  
T

J

= 25°C
 
di/dt = 100A/µs
  
Q

rr  

Reverse Recovery Charge  
Reverse Recovery Current  
nC  
A
T

J

= 125°C  
I

RRM  

T

J

= 25°C  
3
© 2014 International Rectifier  
November 19, 2014  

IRFS7434-7PPbF  
1000  
100  
10  
1000  
100  
10  
VGS  
15V  
10V  
8.0V  
7.0V  
6.0V  
5.5V  
5.0V  
4.5V  
VGS  
15V  
10V  
8.0V  
7.0V  
6.0V  
5.5V  
5.0V  
4.5V  
TOP  
TOP  
BOTTOM  
BOTTOM  
4.5V  
4.5V  
60µs  
PULSE WIDTH  
60µs  
PULSE WIDTH  
Tj = 25°C  
Tj = 150°C  
1
0.1  
1
10  
100  
0.1  
1
10  
100  
V
, Drain-to-Source Voltage (V)  
DS  
V
, Drain-to-Source Voltage (V)  
DS  
Fig 4.
 
Typical Output Characteristics  
Fig 3.
 
Typical Output Characteristics  
1000  
100  
10  
2.0  
1.6  
1.2  
0.8  
0.4  
I
= 100A  
= 10V  
D
V
GS  
T
= 150°C  
J
T
= 25°C  
J
1
V
= 10V  
DS  
60µs PULSE WIDTH  
0.1  
2
3
4
5
6
7
8
-60 -40 -20  
T
0
20 40 60 80
 
100 120 140 160  
, Junction Temperature (°C)  
J
V
, Gate-to-Source Voltage (V)  
GS  
Fig 6.
 
Normalized On-Resistance vs. Temperature  
Fig 5.
 
Typical Transfer Characteristics  
100000  
10000  
1000  
14.0  
V
C
= 0V,  
f = 1 MHZ  
GS  
I
= 100A  
= C
 
+ C
 
, C
 
SHORTED  
D
iss  
gs  
gd ds  
12.0  
10.0  
8.0  
C
= C  
rss  
gd  
V
V
= 32V  
DS  
DS  
C
= C
 
+ C  
oss  
ds  
gd  
= 20V  
C
iss  
C
oss  
C
6.0  
rss  
4.0  
2.0  
100  
0.0  
0.1  
1
10  
100  
0
50  
100  
150  
200  
250  
300  
V
, Drain-to-Source Voltage (V)  
Q , Total
 
Gate Charge (nC)  
DS  
G
Fig 8.
 
Typical Gate Charge vs. Gate-to-Source Voltage  

Submit Datasheet Feedback

November 19, 2014  
Fig 7.
 
Typical Capacitance vs. Drain-to-Source Voltage  

www.irf.com

© 2014 International Rectifier  
4

IRFS7434-7PPbF  
10000  
1000  
100  
10  
1000  
100  
10  
OPERATION IN THIS AREA  
LIMITED BY R
 
(on)  
DS  
100µsec  
T
= 150°C  
J
Limited by Package  
T
= 25°C  
J
1msec  
10msec  
1
1
Tc = 25°C  
Tj = 150°C  
Single Pulse  
DC  
V
= 0V  
GS  
0.1  
0.1  
0.1  
1
10  
100  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
1.4  
1.6  
V
, Drain-to-Source Voltage (V)  
DS  
V
, Source-to-Drain Voltage (V)  
SD  
Fig 10.
 
Maximum Safe Operating Area  
Fig 9.
 
Typical Source-Drain Diode Forward Voltage  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
48  
Id = 1.0mA  
47  
46  
45  
44  
43  
42  
41  
40  
-5  
0
5
10 15 20 25 30 35 40 45  
-60  
-20  
20  
60  
100  
140  
180  
T
, Temperature ( °C )  
V
Drain-to-Source Voltage (V)  
J
DS,  
Fig 12.
 
Typical C

oss

Stored Energy  
Fig 11.
 
Drain-to–Source Breakdown Voltage  
10.0  
VGS = 5.5V  
VGS = 6.0V  
VGS = 7.0V  
VGS = 8.0V  
VGS = 10V  
8.0  
6.0  
4.0  
2.0  
0.0  
0
100  
200  
300  
400  
500  
I ,
 
Drain Current (A)  
D
Fig 13.
 
Typical On-Resistance vs. Drain Current  
© 2014 International Rectifier
 

5
November 19, 2014  

IRFS7434-7PPbF  
1
0.1  
D = 0.50  
0.20  
0.10  
0.05  
0.02  
0.01  
0.01  
SINGLE PULSE  
( THERMAL RESPONSE )  
0.001  
Notes:  
1. Duty Factor D = t1/t2  
2. Peak Tj = P dm x Zthjc + Tc  
0.0001  
1E-006  
1E-005  
0.0001  
0.001  
0.01  
0.1  
t
, Rectangular Pulse Duration (sec)  
1
Fig 14.
 
Maximum Effective Transient Thermal Impedance, Junction-to-Case  
1000  
100  
10  
Duty Cycle = Single Pulse  
Allowed avalanche Current vs avalanche  
pulsewidth, tav, assuming
Tj = 125°C and  
Tstart =25°C (Single Pulse)  
0.01  
0.05  
0.10  
Allowed avalanche Current vs avalanche  
pulsewidth, tav, assuming

j = 25°C and  
Tstart = 125°C.  
1
1.0E-06  
1.0E-05  
1.0E-04  
1.0E-03  
1.0E-02  
1.0E-01  
tav (sec)  
Fig 15.
Typical Avalanche Current vs. Pulse width  
400  
350  
300  
250  
200  
150  
100  
50  
Notes on Repetitive Avalanche Curves , Figures 14, 15:  
(For further info, see AN-1005 at www.irf.com)  
1.Avalanche failures assumption:  
TOP  
Single Pulse  
BOTTOM 1.0%
 
Duty Cycle  
I
= 100A  
D
Purely a thermal phenomenon and failure occurs at a  
temperature far in excess of T

jmax

. This is validated for every  
part type.  
2. Safe operation in Avalanche is allowed as long asT

jmax

is not  
exceeded.  
3. Equation below based on circuit and waveforms shown in Figures  
23a, 23b.  
4. P

D (ave)

= Average power dissipation per single avalanche pulse.  
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage  
increase during avalanche).  
6. I

av

= Allowable avalanche current.  
7.
T = Allowable rise in junction temperature, not to exceed T

jmax  

(assumed as 25°C in Figure 14, 15).  
t

av

= Average time in avalanche.  
0
D = Duty cycle in avalanche =
 
tav ·f  
Z

thJC

(D, t

av

) = Transient thermal resistance, see Figures 13)  
25  
50  
75  
100  
125  
150  
Starting T
 
, Junction Temperature (°C)  
J
PD (ave) = 1/2 ( 1.3·BV·I

av

) =
T/ Z

thJC  

I

av

= 2
T/ [1.3·BV·Z

th

]  
E

AS (AR)

= P

D (ave)· av  

t
Fig 16.
Maximum Avalanche Energy vs. Temperature  

www.irf.com

© 2014 International Rectifier  
6
November 19, 2014  

IRFS7434-7PPbF  
12  
10  
8
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
I
= 60A  
= 34V  
F
V
R
T =
 
25°C  
J
T =
 
125°C  
J
6
ID = 250µA  
ID = 1.0mA  
ID = 1.0A  
4
2
0
0
200  
400  
600  
800  
1000  
-75 -50 -25  
0
25 50 75
 
100 125 150  
di /dt
 
(A/µs)  
T
, Temperature ( °C )  
F
J
Fig 17.
 
Threshold Voltage vs. Temperature  
Fig 18.
 
Typical Recovery Current vs. dif/dt  
12  
10  
8
350  
I
= 100A  
= 34V  
I
= 60A  
= 34V  
F
F
V
V
R
300  
250  
200  
150  
100  
50  
R
T =
 
25°C  
T =
 
25°C  
J
J
T =
 
125°C  
J
T =
 
125°C  
J
6
4
2
0
200  
400  
600  
800  
1000  
0
200  
400  
600  
800  
1000  
di /dt
 
(A/µs)  
di /dt
 
(A/µs)  
F
F
Fig 20.
 
Typical Stored Charge vs. dif/dt  
Fig 19.
 
Typical Recovery Current vs. dif/dt  
300  
I
= 100A  
= 34V  
F
V
250  
200  
150  
100  
50  
R
T =
 
25°C  
J
T =
 
125°C  
J
0
0
200  
400  
600  
800  
1000  
di /dt
 
(A/µs)  
F
Fig 21.
 
Typical Stored Charge vs. dif/dt  
© 2014 International Rectifier
 

7
November 19, 2014  

IRFS7434-7PPbF  
Fig 22.
Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET

®

Power MOSFETs  
V
(BR)DSS  
t
p
15V  
DRIVER  
+
L
V
DS  
D.U.T  
AS  
R
G
V
DD  
–
I
A
20V  
I
0.01  
t
p
AS  
Fig 23a.
 
Unclamped Inductive Test Circuit  
Fig 23b.
 
Unclamped Inductive Waveforms  
Fig 24a.
 
Switching Time Test Circuit  
Fig 24b.
 
Switching Time Waveforms  
Id  
Vds  
Vgs  
Vgs(th)  
Qgs1  
Qgs2  
Qgd  
Qgodr  
Fig 25b.
 
Gate Charge Waveform  
Fig 25a.
 
Gate Charge Test Circuit  
8
© 2014 International Rectifier  
November 19, 2014  

IRFS7434-7PPbF  
D

2

Pak-7Pin Package
 
Outline
(Dimensions are shown in millimeters (inches))  
Note: For the most current drawing please refer to IR website at

9
© 2014 International Rectifier  
November 19, 2014  

IRFS7434-7PPbF  
D

2

Pak-7Pin Part
 
Marking Information  
D2Pak-7Pin Tape and Reel  
Note: For the most current drawing please refer to IR website at

© 2014 International Rectifier  
November 19, 2014  

IRFS7434-7PPbF  
Qualification Information

†  

Qualification Level  
Industrial  
Yes  
D

2

Pak-7Pin  
MSL1  
Moisture Sensitivity Level  
RoHS Compliant  
†
Qualification standards can be found at International Rectifier’s web site:
 

†† Applicable
 
version of JEDEC standard at the time of product release.  
Revision History  
Date  
Comments  

Updated E

AS (L =1mH)
 

= 880mJ
 
on page 2  

Updated note 9
 
“Limited by T

Jmax

, starting T

J

= 25°C, L = 1mH, R

G

= 50
, I

AS

= 42A, V

GS

=10V”. on
 
page 2  
11/19/2014  
IR WORLD HEADQUARTERS:
101 N. Sepulveda Blvd., El Segundo, California 90245, USA  
To contact International Rectifier, please visit

© 2014 International Rectifier  
November 19, 2014