Infineon-Technologies-IRFU420APBF
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IRFR420A, IRFU420A, SiHFR420A, SiHFU420A
Vishay Siliconix
Power MOSFET
FEATURES
• Low Gate Charge Q
g
Results in Simple Drive
Requirement
PRODUCT SUMMARY
V
DS
(V)
500
R
DS(on)
(
)
Q
g
(Max.) (nC)
Q
gs
(nC)
V
GS
= 10 V
3.0
• Improved
Gate, Avalanche and Dynamic
dV/dt Ruggedness
17
4.3
• Fully
Characterized
Capacitance
and
Avalanche Voltage and Current
• Effective C
oss
Specified
• Material
categorization: For definitions of compliance
Q
gd
(nC)
8.5
Configuration
Single
D
D
P
A
K
(TO-252)
I
P
A
K
(TO-251)
APPLICATIONS
• Switch Mode Power Supply (SMPS)
• Uninterruptible Power Supply
• High Speed Power Switching
D
D
G
S
G
S
D
G
S
N-Channel MOSFET
ORDERING INFORMATION
Package
DPAK (TO-252)
SiHFR420A-GE3
IRFR420APbF
SiHFR420A-E3
DPAK (TO-252)
DPAK (TO-252)
IPAK (TO-251)
SiHFU420A-GE3
IRFU420APbF
SiHFU420A-E3
Lead (Pb)-free and Halogen-free
SiHFR420ATR-GE3
a
IRFR420ATRPbF
a
SiHFR420AT-E3
a
SiHFR420ATRL-GE3
IRFR420ATRLPbF
SiHFR420ATL-E3
Lead (Pb)-free
Note
a. See
device orientation.
ABSOLUTE MAXIMUM RATINGS
(T
C
= 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
UNIT
Drain-Source Voltage
Gate-Source Voltage
V
DS
500
V
V
GS
30
3.3
T
C
= 25 °C
Continuous Drain Current
V
GS
at 10 V
I
D
T
C
=
1
00 °C
2.1
A
Pulsed Drain Current
a
I
DM
10
Linear Derating Factor
0.67
140
W/°C
mJ
A
Single Pulse Avalanche Energy
b
Repetitive Avalanche Current
a
Repetitive Avalanche Energy
a
E
AS
I
AR
2.5
E
AR
5.0
mJ
W
Maximum Power Dissipation
T
C
= 25 °C
P
D
83
Peak Diode Recovery dV/dt
c
dV/dt
T
J
, T
stg
3.4
V/ns
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
– 55 to + 150
300
d
°C
for 10 s
Notes
a. Repetitive
rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting
T
J
= 25 °C, L = 45 mH, R
g
= 25
, I
AS
= 2.5 A (see fig. 12).
c. I
SD
2.5 A, dI/dt
270 A/μs, V
DD
V
DS
, T
J
150 °C.
d. 1.6
mm from case.
S13-0165-Rev. C, 04-Feb-13
Document Number: 91274
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
IRFR420A, IRFU420A, SiHFR420A, SiHFU420A
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
62
UNIT
Maximum Junction-to-Ambient
Case-to-Sink, Flat, Greased Surface
Maximum Junction-to-Case (Drain)
R
thJA
R
thCS
R
thJC
–
0.50
–
–
°C/W
1.5
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
Static
Drain-Source Breakdown Voltage
V
DS
V
DS
/T
J
V
GS(th)
I
GSS
V
GS
= 0 V, I
D
= 250 μA
Reference to 25 °C, I
D
= 1 mA
V
DS
= V
GS
, I
D
= 250 μA
500
–
–
–
V
V/°C
V
V
DS
Temperature Coefficient
–
2.0
–
0.60
Gate-Source Threshold Voltage
Gate-Source Leakage
–
–
–
–
–
–
4.5
100
25
250
3.0
–
V
GS
V
DS
= 500 V, V
GS
= 0 V
DS
= 400 V, V
GS
= 0 V, T
J
= 125 °C
V
GS
= 10 V
I
D
= 1.5 A
b
V
DS
= 50 V, I
D
= 1.5 A
=
30 V
nA
–
Zero Gate Voltage Drain Current
I
DSS
μA
V
–
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
R
DS(on)
g
fs
–
1.4
S
Input Capacitance
C
iss
C
oss
C
rss
–
–
–
–
–
–
–
–
–
–
–
–
–
340
53
2.7
490
15
28
–
–
–
V
GS
= 0 V,
DS
= 25 V,
f = 1.0 MHz, see fig. 5
Output Capacitance
V
pF
pF
nC
Reverse Transfer Capacitance
–
V
DS
= 1.0 V, f = 1.0 MHz
–
Output Capacitance
C
oss
V
GS
= 0 V
V
DS
= 400 V, f = 1.0 MHz
–
Effective Output Capacitance
Total Gate Charge
C
oss
eff.
V
DS
= 0 V to 400 V
c
–
Q
g
17
4.3
8.5
–
I
D
= 2.5 A, V
DS
= 400 V,
see fig. 6 and 13
b
Gate-Source Charge
Gate-Drain Charge
Q
gs
Q
gd
t
d(on)
t
r
V
GS
= 10 V
–
–
Turn-On Delay Time
Rise Time
8.1
12
16
13
–
V
DD
= 250 V, I
D
= 2.5 A,
R
g
= 21
, R
D
= 97
, see fig. 10
b
ns
Turn-Off Delay Time
Fall Time
t
d(off)
t
f
–
–
Drain-Source Body Diode Characteristics
MOSFET symbol
showing the
integral reverse
p – n junction diode
D
Continuous Source-Drain Diode Current
Pulsed Diode Forward Current
a
I
S
–
–
–
–
3.3
10
A
G
I
SM
S
Body Diode Voltage
V
SD
t
rr
T
J
= 25 °C, I
S
= 2.5 A, V
GS
= 0 V
b
–
–
–
–
1.6
500
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Forward Turn-On Time
330
760
ns
μC
T
J
= 25 °C, I
F
= 2.5 A, dI/dt = 100 A/μs
b
Q
rr
t
on
1140
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
and L
D
)
Notes
a. Repetitive
rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse
width
300 μs; duty cycle
2 %.
c. C
oss
eff. is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 %to 80 % V
DS
.
S13-0165-Rev. C, 04-Feb-13
Document Number: 91274
2
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
IRFR420A, IRFU420A, SiHFR420A, SiHFU420A
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
10
10
1
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
°
T =
150 C
J
BOTTOM 4.5V
1
0.1
°
T =
25 C
J
0.1
0.01
4.5V
20μs PULSE WIDTH
V
= 50V
DS
°
T =
25 C
J
20μs PULSE WIDTH
0.01
0.1
1
10
100
4.0
5.0
6.0
7.0 8.0
9.0
V
, Drain-to-Source Voltage (V)
V
, Gate-to-Source Voltage (V)
DS
GS
Fig. 3 – Typical Transfer Characteristics
Fig. 1 –
Typical Output Characteristics
10
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VGS
2.5A
=
I
D
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
1
4.5V
20μs PULSE WIDTH
V
=
1
0V
°
T =
150 C
J
GS
0.1
1
10
100
-60 -40 -20
0
20 40 60 80
100 120 140 160
°
T ,
Junction Temperature (
C)
V
, Drain-to-Source Voltage (V)
J
DS
Fig. 2 – Typical Output Characteristics
Fig. 4 – Normalized On-Resistance vs. Temperature
S13-0165-Rev. C, 04-Feb-13
Document Number: 91274
3
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
IRFR420A, IRFU420A, SiHFR420A, SiHFU420A
Vishay Siliconix
10000
1000
100
10
10
V
C
= 0V,
f = 1 MHZ
GS
iss
= C
+ C
,
C
SHORTED
gs
gd
ds
C
= C
rss
gd
C
= C
+ C
°
oss
ds gd
T =
150 C
J
Ciss
1
Coss
°
T =
25 C
J
Crss
V
= 0 V
GS
0.1
1
0.4
0.6
0.8
1.0
1.2
1
10
100
1000
V
,Source-to-Drain Voltage (V)
SD
V
, Drain-to-Source Voltage (V)
DS
Fig. 5 – Typical Capacitance vs. Drain-to-Source Voltage
Fig. 7 – Typical Source-Drain Diode Forward Voltage
20
100
I
D
= 2.5A
V
V
V
= 400V
= 250V
= 100V
OPERATION IN THIS AREA LIMITED
DS
DS
DS
BY R
DS(on)
15
10
5
10
1
10us
100us
1ms
°
T =
25 C
J
10ms
C
°
T =
150 C
FOR TEST CIRCUIT
SEE FIGURE 13
Single Pulse
0.1
0
10
100
1000
10000
0
4
8
12
16
V
, Drain-to-Source Voltage (V)
Q
, Total Gate Charge (nC)
DS
G
Fig. 6 – Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 – Maximum Safe Operating Area
S13-0165-Rev. C, 04-Feb-13
Document Number: 91274
4
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
IRFR420A, IRFU420A, SiHFR420A, SiHFU420A
Vishay Siliconix
R
D
V
DS
5.0
4.0
3.0
2.0
1.0
0.0
V
GS
D.U.T.
R
g
+
V
–
DD
10 V
Pulse width
≤
1 µs
Duty factor
≤
0.1 %
Fig. 10a – Switching Time Test Circuit
V
DS
90 %
25
50
T
75
100
125
150
10 %
V
GS
°
C)
, Case Temperature
(
C
t
d(on)
t
r
t
d(off)
t
f
Fig. 9 – Maximum Drain Current vs. Case Temperature
Fig. 10b – Switching Time Waveforms
10
1
D = 0.50
0.20
0.10
P
DM
0.05
0.1
t
1
SINGLE PULSE
(THERMAL RESPONSE)
0.02
0.01
t
2
Notes:
1. Duty factor D =
t
/ t
1
2
2. Peak T
= P
x
Z
+ T
J
DM
thJC
C
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t ,
Rectangular Pulse Duration (sec)
1
Fig. 11 – Maximum Effective Transient Thermal Impedance, Junction-to-Case
V
DS
t
p
15 V
Driver
L
V
DS
D.U.T
R
g
+
–
V
A
I
AS
DD
I
AS
20 V
0.01
Ω
t
p
Fig. 12b – Unclamped Inductive Waveforms
Fig. 12a – Unclamped Inductive Test Circuit
S13-0165-Rev. C, 04-Feb-13
Document Number: 91274
5
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
IRFR420A, IRFU420A, SiHFR420A, SiHFU420A
Vishay Siliconix
700
300
250
200
150
100
50
I
D
TOP
1.1A
1.6A
BOTTOM 2.5A
650
600
550
0.0
0.5
I
1.0
1.5
2.0
2.5
0
25
50
75
100
125
150
, Avalanche Current ( A)
AV
°
Starting T
, Junction Temperature
( C)
J
Fig. 12d – Maximum Avalanche Energy vs. Drain Current
Fig. 12c – Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
Q
G
50 k
Ω
12 V
0.2 µF
10 V
0.3 µF
Q
GS
Q
GD
+
–
V
DS
D.U.T.
V
G
V
GS
3 mA
Charge
I
G
I
D
Current sampling resistors
Fig. 13a – Basic Gate Charge Waveform
Fig. 13b – Gate Charge Test Circuit
S13-0165-Rev. C, 04-Feb-13
Document Number: 91274
6
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
IRFR420A, IRFU420A, SiHFR420A, SiHFU420A
Vishay Siliconix
Peak Dio
d
e Recovery
d
V/
d
t Test Circuit
+
–
Circuit layout con
s
ideration
s
•
Low
s
tray inductance
•
G
round plane
•
Low leakage inductance
current tran
s
former
D.U.T.
+
–
–
+
R
g
•
dV/dt controlled by R
g
•
Driver
s
ame type a
s
D.U.T.
•
I
S
D
controlled by duty factor “D”
•
D.U.T. – device under te
s
t
+
–
V
DD
Driver gate drive
P.W.
P.W.
D =
Period
Period
V
GS
= 10 V
a
D.U.T. l
S
D
waveform
D.U.T. V
D
S
waveform
Rever
s
e
recovery
current
Body diode forward
current
dI/dt
Diode recovery
dV/dt
V
DD
Re-applied
voltage
Body diode forward drop
Inductor current
I
S
D
Ripple
≤
5 %
Note
a. V
GS
= 5 V for logic level device
s
Fig. 14 – For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
S13-0165-Rev. C, 04-Feb-13
Document Number: 91274
7
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Package Information
Vishay Siliconix
TO-252AA Case Outline
E
A
MILLIMETERS
INCHES
MAX.
C2
b3
DIM.
A
MIN.
MAX.
2.38
0.127
0.88
1.14
5.46
0.61
0.89
6.22
–
MIN.
0.086
–
2.18
–
0.094
0.005
0.035
0.045
0.215
0.024
0.035
0.245
–
A1
b
0.64
0.76
4.95
0.46
0.46
5.97
4.10
6.35
4.32
9.40
0.025
0.030
0.195
0.018
0.018
0.235
0.161
0.250
0.170
0.370
b2
b3
C
C2
D
D1
E
6.73
–
0.265
–
E1
H
b
C
b2
e
10.41
0.410
A1
e1
e
2.28 BSC
4.56 BSC
1.40
0.090 BSC
0.180 BSC
e1
L
1.78
1.27
1.02
1.52
0.055
0.070
0.050
0.040
0.060
L3
L4
L5
0.89
–
0.035
–
1.01
0.040
ECN: T13-0359-Rev. O, 03-Jun-13
DWG: 5347
E1
Notes
•
•
Dimension L3 is for reference only.
Xi’an, Mingxin, and GEM SH actual photo.
Revision: 03-Jun-13
Document Number: 71197
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Package Information
Vishay Siliconix
TO-251AA (HIGH VOLTAGE)
4
3
A
E1
E
Thermal
P
A
D
A
4
0.010
M
A B
C
0.25
c2
b
4
L2
4
A
θ
1
θ
2
D1
4
B
C
3
Seating
plane
5
C
B
C
L3
L1
(Dat
u
m A)
L
B
A
A1
3 x
b
2
3 x
b
c
V
ie
w
A – A
M
0.010
C A B
0.25
2 x e
Base
metal
5
Plating
(c)
b
1,
b
3
Lead tip
5
c1
(
b
,
b
2)
Section B – B and C – C
MILLIMETERS
INCHES
MILLIMETERS
INCHES
MAX.
DIM.
A
MIN.
2.18
0.89
0.64
0.65
0.76
0.76
4.95
0.46
0.41
0.46
5.97
MAX.
2.39
1.14
0.89
0.79
1.14
1.04
5.46
0.61
0.56
0.86
6.22
MIN.
0.086
0.035
0.025
0.026
0.030
0.030
0.195
0.018
0.016
0.018
0.235
MAX.
0.094
0.045
0.035
0.031
0.045
0.041
0.215
0.024
0.022
0.034
0.245
DIM.
D1
E
MIN.
5.21
6.35
4.32
MAX.
MIN.
0.205
0.250
0.170
–
6.73
–
–
0.265
–
A1
b
E1
e
b1
b2
b3
b4
c
2.29 BSC
2.29 BSC
L
8.89
1.91
0.89
1.14
0′
9.65
2.29
1.27
1.52
15′
0.350
0.075
0.035
0.045
0′
0.380
0.090
0.050
0.060
15′
L1
L2
L3
θ
1
θ
2
c1
c2
D
25′
35′
25′
35′
ECN: S-82111-Rev. A, 15-Sep-08
DWG: 5968
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension are shown in inches and millimeters.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005″) per side. These dimensions are measured at the
outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions b4, L2, E1 and D1.
5. Lead dimension uncontrolled in L3.
6. Dimension b1, b3 and c1 apply to base metal only.
7. Outline conforms to JEDEC outline TO-251AA.
Document Number: 91362
Revision: 15-Sep-08
1
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Please note that some Vishay documentation may still make reference
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Revision: 02-Oct-12
Document Number: 91000
1
