Infineon-Technologies-IRFU4510PBF
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PD –
97784
IRFR4510PbF
IRFU4510PbF
HEXFET
®
Power MOSFET
Applications
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
D
S
V
DSS
R
DS(on)
typ.
max.
I
D (Silicon Limited)
I
D (Package Limited)
100V
11.1m
13.9m
63A
G
l
Hard Switched and High Frequency Circuits
56A
Benefits
l
Improved Gate,
Avalanche and Dynamic
dV/dt
D
D
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
S
S
D
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
G
G
DPak
IRFR4510PbF
IPAK
IRFU4510PbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
D
@ T
C
= 25°C
I
DM
Parameter
Max.
63
Units
A
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Package Limited)
Pulsed Drain Current
45
56
252
143
P
D
@T
C
= 25°C
Maximum Power Dissipation
W
0.95
Linear Derating Factor
W/°C
V
± 20
V
GS
T
J
Gate-to-Source Voltage
-55 to
+ 175
Operating Junction and
T
S
T
G
Storage Temperature Range
°C
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
Avalanche Characteristics
E
AS
(
T
h
e
r
m
a
lly limited)
Single Pulse Avalanche Energy
127
mJ
A
Avalanche Current
I
AR
See Fig. 14, 15, 22a, 22b
Repetitive Avalanche Energy
E
AR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
–––
–––
Max.
1.05
50
Units
R
JC
R
JA
R
JA
Junction-to-Case
°C/W
Junction-to-Ambient (PCB Mount)
Junction-to-Ambient
110
ORDERING INFORMATION:
See detailed ordering and shipping information on the last page of this data sheet.
Notes
through
are on page 11
1
05/02/12
IRFR/U4510PbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max.
Units
Conditions
V
GS
= 0V, I
D
= 250
μ
A
100
–––
–––
2.0
–––
0.10
11.1
3.0
–––
–––
13.9
4.0
V
V
(BR)DSS
/
T
J
Breakdown Voltage Temp. Coefficient
V/°C Reference
to 25°C, I
D
= 5mA
R
DS(o
n
)
V
GS
(
th)
I
DSS
Static Drain-to-Source On-Resistance
m
V
GS
= 10V, I
D
= 38A
V
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 100
μ
A
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
–––
–––
–––
–––
0.61
20
V
DS
= 100V, V
GS
= 0V
μ
A
250
100
-100
–––
V
DS
= 100V, V
GS
= 0V, T
J
= 125°C
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
V
GS
= 20V
GS
= -20V
nA
V
R
G(int)
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max.
Units
Conditions
gfs
Forward Transconductance
62
–––
–––
S
V
DS
= 25V, I
D
= 38A
Q
g
Total Gate Charge
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
54
81
I
D
= 38A
Q
gs
Q
gd
Q
sync
t
d(on)
t
r
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Total Gate Charge Sync. (Q
g
– Q
gd
)
Turn-On Delay Time
Rise Time
14
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
V
DS
= 50V
GS
= 10V
nC
15
V
39
I
D
= 38A, V
DS
=0V, V
GS
= 10V
V
DD
= 65V
18
42
I
D
= 38A
ns
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
42
R
G
= 7.5
V
GS
= 10V
34
C
iss
C
oss
C
rss
Input Capacitance
3031
213
104
255
478
V
GS
= 0V
Output Capacitance
Reverse Transfer Capacitance
V
DS
= 50V
pF ƒ
= 1.0MHz
C
C
oss
eff. (ER)
Effective Output Capacitance (Energy Related)
oss
eff. (TR)
Effective Output Capacitance (Time Related)
V
GS
= 0V, V
DS
= 0V to 80V
V
GS
= 0V, V
DS
= 0V to 80V
Diode Characteristics
Symbol
Parameter
Min. Typ. Max.
Units
Conditions
D
S
I
S
Continuous Source Current
MOSFET symbol
–––
–––
56
(Body Diode)
Pulsed Source Current
showing the
integral reverse
A
V
G
I
SM
–––
–––
252
(Body Diode)
p-n junction diode.
T
J
= 25°C, I
S
= 38A, V
GS
= 0V
V
SD
dv/dt
t
rr
Diode Forward Voltage
Peak Diode Recovery
Reverse Recovery Time
–––
–––
–––
–––
–––
–––
–––
–––
7.0
34
1.3
–––
–––
–––
–––
–––
–––
V/ns T
J
= 175°C, I
S
= 38A, V
DS
= 100V
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
V
R
= 86V
ns
39
I
F
= 38A
di/dt = 100A/
μ
s
Q
rr
Reverse Recovery Charge
47
nC
A
61
I
RRM
t
on
Reverse Recovery Current
Forward Turn-On Time
2.4
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
IRFR/U4510PbF
1000
100
10
1000
100
10
VGS
15V
10V
6.0V
5.5V
5.0V
4.75V
4.5V
4.25V
VGS
15V
10V
6.0V
5.5V
5.0V
4.75V
4.5V
4.25V
TOP
TOP
BOTTOM
BOTTOM
4.25V
1
60
μ
s PULSE WIDTH
Tj = 25°C
60
μ
s PULSE WIDTH
Tj = 175°C
4.25V
0.1
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
100
10
2.6
2.2
1.8
1.4
1.0
0.6
0.2
I
= 38A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
= 25V
J
V
DS
60
μ
s PULSE WIDTH
1.0
2
3
4
5
6
7
8
9
-60 -40 -20
0 20
40 60 80
100120140160180
, Junction Temperature (°C)
T
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4.
Normalized On-Resistance vs. Temperature
Fig 3.
Typical Transfer Characteristics
14.0
100000
10000
1000
100
V
= 0V,
= C
f = 1 MHZ
I
= 38A
GS
D
C
C
C
+ C
, C
SHORTED
ds
iss
gs
gd
12.0
10.0
8.0
= C
V
V
V
= 80V
= 50V
= 20V
rss
oss
gd
= C
+ C
DS
DS
DS
ds
gd
C
iss
C
C
6.0
oss
rss
4.0
2.0
0.0
10
0
10
20
30
40
50
60
70
1
10
100
1000
Q , Total
Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFR/U4510PbF
1000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
100
μ
sec
1msec
T
= 175°C
100
10
J
Limited by
package
1
T
= 25°C
J
10msec
DC
0.1
0.01
Tc = 25°C
Tj = 175°C
Single Pulse
V
GS
= 0V
1.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
, Source-to-Drain Voltage (V)
0.1
1
10
100
1000
V
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
125
120
115
110
105
100
95
70
Id = 5mA
Limited by package
60
50
40
30
20
10
0
-60 -40 -20
0 20
40 60 80
100120140160180
25
50
75
100
125
150
175
T ,
Temperature ( °C )
J
Fig 10.
Drain-to-Source Breakdown Voltage
T
, Case Temperature (°C)
Fig 9.
Maxi
C
mum Drain Current vs.
Case Temperature
1.6
600
I
D
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
TOP
4.7A
12A
BOTTOM 38A
500
400
300
200
100
0
-20
0
20
40
60
80
100 120
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
J
V
Drain-to-Source Voltage (V)
DS,
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy vs. DrainCurrent
4
IRFR/U4510PbF
10
1
D = 0.50
0.20
0.10
0.05
R
1
R
1
R
2
R
2
R
3
R
3
0.1
Ri (°C/W)
i (sec)
J
J
C
0.3442 0.001031
0.0679 0.000061
0.6371 0.005883
1
1
2
2
3
3
0.02
0.01
Ci=
i
Ri
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
10
1
Allowed avalanche Current vs avalanche
Duty Cycle = Single Pulse
pulsewidth, tav, assuming
Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
150
125
100
75
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
TOP
BOTTOM 1.0%
Duty Cycle
= 38A
Single Pulse
I
D
6. I
av
= Allowable avalanche current.
7.
T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
50
t
av =
Average time in avalanche.
D = Duty cycle in avalanche =
t
av
·f
25
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
0
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
25
50
75
100
125
150
175
I
av
= 2
D
T/ [1.3·BV·Z
th
]
Starting T
, Junction Temperature (°C)
E
AS (AR)
= P
D (ave)
·t
av
J
Fig 15.
Maximum Avalanche Energy vs. Temperature
5
IRFR/U4510PbF
20
15
10
5
4.5
4.0
3.5
3.0
I =
25A
F
V
= 86V
R
T =
25°C
J
T =
125°C
J
I
I
I
I
= 100
μ
A
= 250
μ
A
= 1.0mA
= 1.0A
D
D
D
D
2.5
2.0
1.5
1.0
0
-75 -50 -25
0
25 50 75
100 125 150 175
0
200
400
600
800
1000
di /dt
(A/
μ
s)
T
, Temperature ( °C )
J
F
Fig. 17
– Typical Recovery Current vs. di
f
/dt
Fig 16.
Threshold Voltage vs. Temperature
20
350
I =
38A
I =
25A
F
F
300
250
200
150
100
50
V
= 86V
V
= 86V
R
R
T =
25°C
T =
25°C
J
J
15
10
5
T =
125°C
J
T =
125°C
J
0
0
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt
(A/
μ
s)
di /dt
(A/
μ
s)
F
F
Fig. 18
– Typical Recovery Current vs. di
f
/dt
Fig. 19
– Typical Stored Charge vs. di
f
/dt
350
I =
38A
F
300
250
200
150
100
50
V
= 86V
R
T =
25°C
J
T =
125°C
J
0
0
200
400
600
800
1000
di /dt
(A/
μ
s)
F
Fig. 20
– Typical Stored Charge vs. di
f
/dt
6
IRFR/U4510PbF
Driver Gate Drive
P.W.
P
.
W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
Driver same type as D.U.T.
I
SD
controlled by Duty Factor “D”
D.U.T. – Device Under Test
Inductor Current
I
SD
Ripple
5%
*
V
GS
= 5V for Logic Level Devices
Fig 21.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
V
2
GS
0.01
t
p
I
AS
Fig 22b.
Unclamped Inductive Waveforms
Fig 22a.
Unclamped Inductive Test Circuit
R
D
V
DS
V
DS
90%
V
GS
D.U.T.
R
G
+
V
DD
–
V
GS
10%
Pulse Width
µs
Duty Factor
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a.
Switching Time Test Circuit
Fig 23b.
Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.
T
.
Vds
Vgs
50K
.2
F
12V
.3
F
+
V
DS
D.U.
T
.
–
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a.
Gate Charge Test Circuit
Fig 24b.
Gate Charge Waveform
7
IRFR/U4510PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
8
IRFR/U4510PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
9
IRFR/U4510PbF
D-Pak (TO-252AA)
T
a
pe & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRL
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
FEED DIRECTION
NOTES :
1. CONTROLLING
DIMENSION : MILLIMETER.
2. ALL
DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE
CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
10
IRFR/U4510PbF
Orderable part number
Package Type
Standard Pack
Form Quantity
Note
IRFR4510PbF
IRFR4510TRPbF
IRFU4510PbF
D-PAK
D-PAK
I
–
PAK
Tube/Bulk
Tape and Reel
Tube/Bulk
75
2000
75
Qualification Information
†
Industrial
††
(per JEDEC JESD47F
†††
guidelines)
Qualification level
Comments: This family of products has passed JEDEC’s Industrial
qualification. IR’s Consumer qualification level is granted by extension of the
higher Industrial level.
MSL
1
D-PAK
(per JEDEC J-STD-020D
†††
)
Moisture Sensitivity Level
RoHS Compliant
Not app
l
i
c
ab
l
e
I-PAK
Yes
†
Qualification standards can be found at International Rectifier’s web site
http://www.irf.com/product-info/reliability
†† Higher
qualification ratings may be available should the user have such requirements. Please contact
your International Rectifier sales representative for further information:
http://www.irf.com/whoto-call/salesrep/
††† Applicable version of JEDEC standard at the time of product release.
Notes:
ꢀ
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
Repetitive rating;
pulse width limited by max. junction
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
temperature.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.18mH
R
G
= 50
, I
AS
= 38A, V
GS
=10V. Part not recommended for use
above this value.
I
SD
38A, di/dt
2031A/
μ
s, V
DD
V
(BR)DSS
, T
J
175°C.
Pulse width
400
μ
s; duty cycle
2%.
.
When mounted on 1″ square PCB (FR-4 or G-10 Material).
For recom
mended footprint and soldering techniques refer to application
note #AN-994.
R
is measured at T
J
approximately 90°C.
Data and specifications subject to change without notice
IR WORLD HEADQUARTERS:
101 N. Sepulveda Blvd., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
11
IMPORTANT NOTICE
T
h
e information given in this document shall in no
For further information on the product, technology,
event be regarded as a guarantee of conditions or
delivery terms and conditions and prices please
characteristics (“
B
e
schaffenheitsgarantie”) .
contact your nearest
I
n
fineon
T
e
chnologies office
W
i
t
h respect to any e
x
a
mples, hints or any typical
v
a
lues stated herein and/or any information
regarding the application of the product,
I
n
fineon
T
e
chnologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
WARNINGS
D
u
e to technical requirements products may
contain dangerous substances.
F
o
r information on
the types in question please contact your nearest
I
n
fineon
T
e
chnologies office.
In
a
ddition, any information given in this document
is subject to customer
’
s
c
ompliance with its
obligations stated in this document and any
applicable legal requirements, norms and
standards concerning customer
’
s
p
roducts and any
use of the product of
I
n
fineon
T
e
chnologies in
customer
’
s
a
pplications.
Exc
e
pt as otherwise explicitly approved by
I
n
fineon
T
e
chnologies in a written document signed by
authorized
representatives
of
I
n
fineon
T
e
chnologies,
I
n
fineon
T
e
chnologies’ products may
not be used in any applications where a failure of
the product or any consequences of the use thereof
can reasonably be e
x
p
ected to result in personal
injury.
T
h
e data contained in this document is exclusively
intended for technically trained staff.
I
t is
t
he
responsibility of customer
’
s
t
echnical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
