Infineon-Technologies-IRL100HS121
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IRL100HS121
Typical values (unless otherwise specified
)
Target Applications
Wireless charging
V
DSS
V
GS
R
DS(on)
(max
.
)
Adapter
Telecom
100V min.
Q
g tot
± 20V max
Q
gd
42m
@ 10V
V
gs(th)
3.7nC
1.6nC
1.7V
Benefits
Top View
Higher power density designs
Higher switching frequency
Uses OptiMOS
TM
5 Chip
Reduced parts count wherever
5V
supplies are available
D
D
G
1
2
3
6
5
4
D
D
S
D
S
Driven directly from microcontrollers
(slow switching)
System cost reductions
G
D
S
Gate
Drain
Source
Standard Pack
Form
Base part number
Package Type
Orderable Part Number
Quantity
IRL100HS121
PQFN 2mm x 2mm
Tape and Reel
4000
IRL100HS121
100
80
60
40
20
120
110
100
90
I
= 6.7A
D
VGS = 4.0V
VGS = 4.5V
VGS = 5.0V
VGS = 6.0V
VGS = 7.0V
VGS = 10V
80
T
= 125°C
= 25°C
70
J
60
50
T
J
40
30
20
10
0
4
8
12
16
20
24
3
4
5
6
7
8
9
10 11 12
I
, Drain Current (A)
V
Gate -to -Source Voltage
(V)
D
GS,
Figure 1
Typical On-Resistance vs. Gate Voltage
Figure 2
Typical On-Resistance vs. Drain Current
Final Datasheet
Please read the important Notice and Warnings at the end of this document
V2.2
2019-12-13
IRL100HS121
Table of Contents
Table of Contents
Final Datasheet
V2.2
2
2019-12-13
IRL100HS121
Parameters
1
Parameters
Table1
Key performance parameters
Values
Parameter
Units
V
DS
100
42
V
R
DS(on) max
m
A
I
D
@ T
C
= 25°C
I
D
@ T
A
= 25°C
11
5.1
A
Final Datasheet
V2.2
3
2019-12-13
IRL100HS121
Maximum ratings and thermal characteristics
2
Maximum ratings and thermal characteristics
Table 2
Maximum ratings (at T
J
= 25
°
C, unless otherwise specified)
Parameter
Symbol
Conditions
Values
Unit
I
D
I
D
T
C (Bottom)
= 25°C, V
GS
@ 10V
T
C (Bottom)
= 100°C, V
GS
@ 10V
11
7.8
I
D
T
C (Bottom)
= 25°C, V
GS
@ 10V
10.2
A
(Source Bonding Technologies Limited)
I
D
I
DM
P
D
P
D
P
D
V
GS
T
P
T
A
= 25°C, V
GS
@ 10V
T
C (Bottom)
= 25°C
T
C (Bottom)
= 25°C
T
C (Bottom)
= 100°C
T
A
= 25°C
5.1
41
11.5
5.8
2.5
± 20
270
Maximum Power Dissipation
Gate-to-Source Voltage
W
V
–
–
Peak Soldering Temperature
Operating Junction and
°C
T
J
,T
STG
–
-55 to
+ 175
Storage Temperature Range
Table 3
Thermal characteristics
Parameter
Symbol
Conditions
Min.
Typ.
–
–
–
–
Max.
13
90
60
42
Unit
–
–
–
–
–
–
–
–
R
JC
R
JC
°C/W
R
JA
R
JA
(<10s)
Table 4
Avalanche characteristics
Parameter
Symbol
Values
Unit
E
AS
I
AR
13
5.0
mJ
A
Notes:
Repetitive rating;
pulse width limited by max. junction temperature.
Starting T
J
= 25°C, L = 1.0mH, R
G
= 50
, I
AS
= 5.0A based on test data.
Pulse width
≤
400µs; duty cycle
≤
2%.
R
is measured at T
J
of approximately 90°C.
When mounted
on a 1 inch square PCB (FR-4). Please refer to AN-994 for more details.
Calculated continuous current based on maximum allowable junction temperature.
Current is limited to 10.2A by source bonding technology.
Final Datasheet
V2.2
2019-12-13
4
IRL100HS121
Electrical characteristics
3
Electrical characteristics
Table 5
Static characteristics
Values
Min. Typ.
Max.
Parameter
Symbol
Conditions
Unit
Drain-to-Source Breakdown Voltage
V
(BR)DSS
V
GS
= 0V, I
D
= 250µA
100
–
–
V
Breakdown Voltage Temp. Coe
ff
icient
Reference to 25°C, I
D
= 1mA
–
44
–
mV/°C
V
(BR)DSS
/
T
J
–
34
42
V
Static Drain-to-Source On-Resistance
R
DS(on)
m
–
1.1
–
–
–
–
–
45
1.7
-5.6
–
–
59
2.3
–
1.0
100
100
–
Gate Threshold Voltage
V
GS(th)
V
V
DS
= V
GS
, I
D
= 10µA
Gate Threshold Voltage Temp. Coe
ff
icient
Drain-to-Source Leakage Current
mV°/C
µA
V
GS(th)
/
T
J
I
DSS
I
GSS
I
GSS
R
G
V
DS
= 80V, V
GS
= 0V
V
GS
= 20V
V
GS
= -20V
–
Gate-to-Source Forward Leakage
Gate Resistance
nA
–
0.9
Table 6
Dynamic characteristics
Values
Min. Typ. Max.
Parameter
Symbol
Conditions
Unit
Forward Trans conductance
Total Gate Charge
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
Output Charge
Turn-On Delay Time
Rise Time
Turn-O
ff
Delay Time
Fall Time
gfs
Q
g
Q
gs1
Q
gs2
Q
gd
Q
godr
Q
sw
Q
oss
t
d(on)
t
r
t
d(o
ff
)
t
f
C
iss
C
oss
C
rss
V
DS
= 25V, I
D
= 6.7A
15
–
–
–
–
–
5.6
–
S
3.7
0.8
0.5
1.6
0.8
2.1
9.5
7.6
21
I
D
= 6.7A
V
DS
= 50V
V
GS
= 4.5V
See Fig.8
–
nC
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
V
DS
= 50V ,V
GS
= 0V
V
DD
= 50V
nC
ns
I
D
= 6.7A
8.7
R
G
= 2.7
V
GS
= 0V
V
DS
= 50V
ƒ = 1.0MHz
10.7
440
80
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
6.3
pF
Output Capacitance
Output Capacitance
C
oss
C
oss
V
GS
= 0V, V
DS
= 1.0V, ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 80V, ƒ = 1.0MHz
–
–
330
60
–
–
Table 7
Reverse Diode
Values
Parameter
Symbol
Conditions
Unit
Min. Typ. Max.
D
Continuous Source Current
Reverse Recovery Time
Reverse Recovery Charge
MOSFET symbol
I
S
–
–
11
showing the
G
A
V
ns
nC
integral reverse
p-n junction diode.
di/dt = 100A/µs
I
SM
S
–
–
–
–
22
28
41
V
SD
t
rr
Q
rr
1.2
–
–
–
–
Final Datasheet
V2.2
2019-12-13
5
IRL100HS121
Electrical characteristic diagrams
4
Electrical characteristic diagrams
100
10
1
100
10
1
60µs PULSE WIDTH
60µs PULSE WIDTH
Tj = 25°C
Tj = 175°C
2.7V
VGS
12V
10V
4.5V
4.0V
3.5V
3.3V
3.0V
2.7V
VGS
12V
10V
4.5V
4.0V
3.5V
3.3V
3.0V
2.7V
TOP
2.7V
TOP
BOTTOM
BOTTOM
0.1
0.1
0.1
1
10
100
0.1
1
10
100
V
DS
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
Figure 4
Typical Output Characteristics
Figure 3
Typical Output Characteristics
2.4
100
I
= 6.7A
= 10V
D
V
GS
2.0
1.6
1.2
0.8
0.4
T =
175°C
J
10
T =
25°C
J
V
= 25V
DS
60µs PULSE WIDTH
1
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
2
3
4
5
6
T
, Junction Temperature (°C)
V
, Gate-to-Source Voltage (V)
J
GS
Figure 5
Typical Transfer Characteristics
Figure 6
Normalized On-Resistance vs. Temperature
Final Datasheet
V2.2
6
2019-12-13
IRL100HS121
Electrical characteristic diagrams
14
12
10
8
10000
V
C
= 0V,
f = 1 MHZ
GS
I
= 6.7A
D
= C
+ C
, C
SHORTED
iss
gs
gd ds
V
= 80V
= 50V
= 20V
DS
C
= C
rss
gd
V
DS
C
= C
+ C
oss
ds gd
1000
100
10
V
DS
C
C
iss
oss
C
6
rss
4
2
0
1
0
2
4
6
8
10
0.1
1
10
100
Q ,
Total Gate Charge (nC)
V
, Drain-to-Source Voltage (V)
G
DS
Figure 8
Typical Gate Charge vs.
Gate-to-Source
Voltage
Figure 7
Typical Capacitance vs. Drain-to-Source
Voltage
100
100
OPERATION IN THIS AREA LIMITED BY R
(on)
DS
100µsec
10
T
= 175°C
J
10
1
1msec
LIMITED BY PACKAGE
T
= 25°C
1
J
10msec
DC
0.1
Tc = 25°C
Tj = 175°C
Single Pulse
V
GS
= 0V
1.2
0.1
0.01
0.4
0.6
0.8
1.0
1.4
0.1
1
10
100
V
, Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Figure 10
Maximum Safe Operating Area
Figure 9
Typical Source-Drain Diode Forward
Voltage
Final Datasheet
V2.2
2019-12-13
7
IRL100HS121
Electrical characteristic diagrams
12
3.0
2.5
2.0
1.5
1.0
0.5
LIMITED BY PACKAGE
10
8
6
I
I
I
I
= 10µA
= 250µA
= 1.0mA
= 1.0A
4
D
D
D
D
2
0
25
50
75
100
125
150
175
-75 -50 -25
0
25 50 75
100 125 150 175
, Temperature ( °C )
T
, Case Temperature (°C)
T
C
J
Figure 11
Maximum Drain Current vs. Case
Temperature
Figure 12
Typical Threshold Voltage vs. Junction
Temperature
60
50
40
30
20
10
I
D
TOP
1.1A
1.7A
5.0A
BOTTOM
0
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
J
Figure 13
Maximum Avalanche Energy vs. Drain Current
Final Datasheet
V2.2
8
2019-12-13
IRL100HS121
Electrical characteristic diagrams
100
Allowed avalanche Current vs avalanche pulsewidth, tav,
Single Pulse
assuming Tj
= 150°C and Tstart =25°C (Single Pulse)
10
0.01
1
0.05
0.10
0.1
Allowed avalanche Current vs avalanche pulsewidth,
tav, assuming
Tj =25°C and Tstart = 150°C.
0.01
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Figure 14
Typical Avalanche Current vs. Pulse Width
100
10
D = 0.50
0.20
0.10
1
0.02
0.05
0.01
0.1
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.01
1E-006
1E-005
0.0001
t
0.001
0.01
0.1
1
, Rectangular Pulse Duration (sec)
1
Figure 15
Maximum E
ff
ective Transient Thermal Impedance, Junction-to-Case
Final Datasheet
V2.2
2019-12-13
9
IRL100HS121
Electrical characteristic diagrams
Figure 16
Peak Diode Recovery dv/dt Test Circuit for N-Channel Power MOSFETs
Figure 17b
Gate Charge Waveform
Figure 17a
Gate Charge Test Circuit
Final Datasheet
V2.2
10
2019-12-13
IRL100HS121
Electrical characteristic diagrams
Figure 18b
Unclamped Inductive Waveforms
Figure 18a
Unclamped Inductive Test Circuit
Figure 19b
Switching Time Waveforms
Figure 19a
Switching Time Test Circuit
Final Datasheet
V2.2
2019-12-13
11
IRL100HS121
Package Information
5
Package Information
PQFN 2 x 2 Outline Package Details
For more information on board mounting, including footprint and stencil recommendation, please refer to application note
For more information on package inspection techniques, please refer to application note AN-1154:
PQFN 2 x 2 Part Marking
X
S121
_
YWLCP
Final Datasheet
V2.2
12
2019-12-13
IRL100HS121
Qualification Information
6
Qualification Information
Qualification Information
Qualification Level
Industrial
(per JEDEC JESD47F)
†
MSL1
(per JEDEC J-STD-020D)
†
Moisture Sensitivity Level
RoHS Compliant
PQFN 2 mm x 2 mm
Yes
†
Applicable version of JEDEC standard at the time of product release.
Final Datasheet
V2.2
14
2019-12-13
IRL100HS121
Revision History
Revision History
Major changes since the last revision
Revision
Page or Reference
Date
Description of changes
All pages
1.0
1.1
2015-12-03
2016-09-12
First release data sheet as Provisional.
Updated datasheet with revised package picture and outline drawings.
Datasheet is released as Provisional.
All page
Added Switch Time test data.
Datasheet is released as Provisional.
All pages
All pages
1.2
1.3
2016-10-17
2017-08-21
Parts tested as Unique datasheet with revised current and all other tests
Updated ds in New Infineon Template
Added Link for Package Information—pages 12, 13
Added IR—PQFN 2×2 Package Picture—page 1
Datasheet completed as Approved Not Released.
Datasheet is w/o “Approved Not Released”
All pages
All pages
2.0
2.1
2017-10-06
2018-05-08
First release data sheet on Web.
Corrected typo on part marking from “100HS121” to “S121” to matched
actual marking on the devices –page12
Features-Corrected from “IR MOSFET /OptiMOS™5” to “OptiMOS™5” to
in line with the technology positioning of product –page 1.
All pages
2.2
2019-12-13
Final Datasheet
V2.2
15
2019-12-13
Trademarks of Infineon Technologies AG
µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™,
DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™,
HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OPTIGA™,
OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™,
SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™
Trademarks updated November 2015
Other Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
For further information on the product, technology,
Edition 2015-05-06
Published by
Infineon Technologies AG
81726 Munich, Germany
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Bescha
ff
enheitsgarantie”) .
delivery terms and conditions and prices please
contact your nearest Infineon Technologies o
ff
ice
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement of
intellectual property rights of any third party.
WARNINGS
© 2016 Infineon Technologies AG.
All Rights Reserved.
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies o
ff
ice.
Do you have a question about this
document?
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In addition, any information given in this document
is subject to customer’s compliance with its
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applicable legal requirements, norms and standards
concerning customer’s products and any use of the
product of Infineon Technologies in customer’s
applications.
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any applications where a failure of the product or
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be expected to result in personal injury.
The data contained in this document is exclusively
intended for technically trained sta
ff
. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
