Infineon-Technologies-IRL2505STRLPBF
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PD – 95577
IRL2505LPbF
IRL2505SPbF
HEXFET
®
Power MOSFET
l
Logic-Level Gate Drive
l
Advanced Process Technology
l
Surface Mount (IRL2505S)
l
Low-profile through-hole (IRL2505L)
l
175°C Operating Temperature
l
Fast Switching
l
Fully Avalanche Rated
l
Lead-Free
Description
D
V
DSS
= 55V
R
DS(on)
= 0.008
Ω
G
I
D
= 104A
S
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low
on-resistance per silicon area.
This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs
ar
e
w
el
l
k
now
n
f
or, provide
s
t
h
e
d
esigne
r
w
it
h
a
n
e
xtremely
efficient and reliable device for use in a wide variety of
applications.
The D
2
Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-
resistance in any existing surface mount package. The
D
2
Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate
up to 2.0W in a typical surface mount application.
The through-hole version (IRL2505L) is available for low-
profil
e
a
pplications.
2
TO-262
D
Pak
Absolute Maximum Ratings
Parameter
Max.
104
74A
360
3.8
Units
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
Continuous Drain Current, V
GS
@ 10V
ꢀ
Continuous Drain Current, V
GS
@ 10V
ꢀ
Pulsed Drain Current
ꢀ
P
D
@T
A
= 25°C
P
D
@T
C
= 25°C
Power Dissipation
W
W
Power Dissipation
200
1.3
Linear Derating Factor
W/°C
V
V
GS
E
A
S
I
AR
Gate-to-Source Voltage
±16
500
54A
20
Single Pulse Avalanche Energy
ꢀ
Avalanche Current
mJ
E
AR
dv/dt
T
J
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
ꢀ
Operating Junction and
mJ
5.0
V/ns
-55 to
+ 175
300 (1.6mm from case )
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
°C
Thermal Resistance
Parameter
Junction-to-Case
Typ.
Max.
0.75
Units
°C/W
1
R
θ
JC
R
θ
JA
Junction-to-Ambient ( PCB Mounted,steady-state)**
40
07/19/04
IRL2505S/LPbF
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
55
V
V
GS
= 0V, I
D
= 250µA
∆
V
(BR)DSS
/
∆
T
J
Breakdown Voltage Temp. Coefficient
0.035
V/°C
Reference to 25°C, I
D
= 1mA
ꢀ
0.008
0.010
0.013
V
GS
= 10V, I
D
= 54A
GS
= 5.0V, I
D
= 54A
R
DS(on)
Static Drain-to-Source On-Resistance
Ω
V
V
GS
= 4.0V, I
D
= 45A
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 25V, I
D
= 54A
ꢀ
V
DS
= 55V, V
GS
= 0V
V
DS
= 44V, V
GS
= 0V, T
J
= 150°C
V
GS
= 16V
V
GS(th)
g
fs
Gate Threshold Voltage
1.0
59
2.0
V
S
Forward Transconductance
25
250
100
-100
130
25
67
µA
nA
I
D
SS
I
GSS
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
V
GS
= -16V
Q
g
I
D
= 54A
Q
gs
Q
gd
t
d(on)
t
r
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Turn-On Delay Time
nC
ns
V
DS
= 44V
V
GS
= 5.0V, See Fig. 6 and 13
ꢀ
V
DD
= 28V
12
Ris
e
T
ime
160
I
D
= 54A
t
d(off)
t
f
Turn-Off Delay Time
43
84
R
G
= 1.3
Ω,
V
GS
= 5.0V
R
D
= 0.50
Ω,
See Fig. 10
ꢀ
Between lead,
Fall
Time
L
S
Internal Source Inductance
7.5
nH
pF
and center of die contact
V
GS
= 0V
C
iss
C
oss
C
rss
Input Capacitance
5000
1100
390
Output Capacitance
V
DS
= 25V
Reverse Transfer Capacitance
= 1.0MHz, See Fig. 5
ꢀ
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
D
I
S
MOSFE
T
s
ymbol
104
showing the
A
G
I
SM
Pulsed Source Current
(Body Diode)
integral reverse
360
S
p-n junction diode.
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
1.3
140 210
650 970
V
T
J
= 25°C, I
S
= 54A, V
GS
= 0V
ns
T
J
= 25°C, I
F
= 54A
Q
rr
t
on
nC di/dt
= 100A/µs
ꢀ
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Notes:
Repetitive rating;
pulse width limited by
Pulse width
≤
300µs; duty cycle
≤
2%.
ꢀ
Uses IRL2505 data and test conditions
max. junction temperature. ( See fig. 11 )
V
DD
= 25V, starting T
J
= 25°C, L = 240µH
R
G
= 25
Ω
, I
AS
= 54A. (See Figure 12)
I
SD
≤
54A, di/dt
≤
230A/µs, V
DD
≤
V
(BR)DSS
T
J
≤
175°C
Caculated continuous current based on maximum allowable
junction temperature;for recommended current-handling of the
package refer to Design Tip # 93-4
,
** When mounted on 1″ square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
2
IRL2505S/LPbF
1000
100
10
1000
100
10
VGS
15V
VGS
15V
TOP
TOP
12V
10V
8.0V
6.0V
4.0V
3.0V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
BOTTOM 2.5V
2.5V
2.5V
20µs PULSE WIDTH
20µs PULSE WIDTH
T
= 25°C
T
= 175°C
J
J
1
1
0.1
A
A
0.1
1
10
100
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 2.
Typical Output Characteristics
Fig 1.
Typical Output Characteristics
1000
100
10
3.0
2.5
2.0
1.5
1.0
0.5
0.0
I
= 90A
D
T
J
= 25°C
T
J
= 175°C
V
DS
= 25V
20µs PULSE WIDTH
V
= 10V
GS
1
A
A
2.5
3.5
4.5
5.5
6.5
7.5
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
V
GS
, Gate-to-Source Voltage (V)
T ,
Junction Temperature (°C)
J
Fig 4.
Normalized On-Resistance
Fig 3.
Typical Transfer Characteristics
Vs
.
T
emperature
3
IRL2505S/LPbF
15
12
9
10000
I
= 54A
V
C
C
C
= 0V,
f = 1MHz
D
GS
iss
= C
+ C
,
C
SHORTED
gs
gd
ds
V
= 44V
= 28V
DS
= C
rss
oss
gd
V
DS
= C
+ C
ds
gd
8000
6000
4000
2000
0
C
C
iss
6
oss
3
C
rss
FOR TEST CIRCUIT
SEE FIGURE 13
0
A
A
1
10
100
0
40
80
120
160
200
V
, Drain-to-Source Voltage (V)
Q
, Total Gate Charge (nC)
DS
G
Fig 5.
Typical Capacitance Vs.
Fig 6.
Typical Gate Charge Vs.
Drain-to-Source Voltage
Gate-to-Source Voltage
1000
100
10
1000
100
10
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
10µs
100µs
T =
175°C
J
1ms
T =
25°C
J
10ms
T
T
= 25°C
= 175°C
Single Pulse
C
J
V
= 0V
GS
A
1
A
100
0.4
0.8
1.2
1.6
2.0
2.4
2.8
1
10
V
, Drain-to-Source Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 7.
Typical Source-Drain Diode
Fig 8.
Maximum Safe Operating Area
Forward Voltage
4
IRL2505S/LPbF
120
100
80
60
40
20
0
LIMITED BY PACKAGE
V
GS
D.U.T.
R
G
+
V
DD
–
5.0V
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
Fig 10a.
Switching Time Test Circuit
V
DS
90%
25
50
75
100
125
150
175
°
T ,
Case Temperature
( C)
10%
C
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 9.
Maximum Drain Current Vs.
Case Temperature
Fig 10b.
Switching Time Waveforms
1
D = 0.50
0.20
0.1
0.10
0.05
P
2
DM
t
1
0.02
0.01
t
2
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D =
t /
t
1
2. Peak T
= P
x Z
+ T
C
J
DM
thJC
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t ,
Rectangular Pulse Duration (sec)
1
Fi
g
1
1.
Maximu
m
E
ffectiv
e
T
ransien
t
T
herma
l
I
mpedance
,
J
unction-to-Case
5
IRL2505S/LPbF
1200
1000
800
600
400
200
0
I
D
L
TOP
22A
38A
BOTTOM 54A
V
DS
D.U.
T
.
R
+
–
G
V
DD
I
1
0
V
AS
t
p
0.01
Ω
Fig 12a.
Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
V
= 25V
50
DD
A
175
25
75
100
125
150
V
DD
Starting T
, Junction Temperature (°C)
J
V
DS
Fig 12c.
Maximum Avalanche Energy
I
AS
Vs. Drain Current
Fi
g
1
2b.
Unclampe
d
I
nductiv
e
W
aveforms
Current Regulator
Same Type as D.U.
T
.
50K
Ω
.2
µ
F
12V
Q
Q
G
.3
µ
F
10 V
+
V
DS
Q
D.U.
T
.
–
GS
GD
V
GS
V
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 13b.
Gate Charge Test Circuit
Fig 13a.
Basic Gate Charge Waveform
6
IRL2505S/LPbF
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
D.U.T
–
+
–
–
+
R
G
•
dv/dt controlled by R
G
+
–
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
V
DD
Driver Gate Drive
P
.
W.
Period
Period
D =
P.W.
V
=10V
*
GS
D.U.
T
. I
W
aveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fi
g
1
4
.
Fo
r
N
-Channe
l
H
EXFETS
7
IRL2505S/LPbF
D
2
Pak Package Outline
Dimensions are shown in millimeters (inches)
D
2
Pak Part Marking Information
THIS IS AN IR
F
530S W
I
TH
L
O
T CODE 8024
P
A
RT NUMBER
INTERNAT
I
O
N
A
L
REC
T
I
F
I
E
R
L
O
GO
A
S
S EMBLED
ON WW 02, 2000
IN T
H
E
A
S
SEMB
L
Y LINE
“
L”
F530S
D
A
TE
C
ODE
Y
E
A
R 0 =
2
000
W
E
EK 02
Note:
“
P
”
i
n
a
ss emb
l
y li
n
e
pos
i
ti
o
n
i
n
d
i
c
ates
“
Le
a
d-Free”
A
S
SEMB
L
Y
L
O
T CODE
LI
N
E L
OR
P
A
RT NUMBER
I
N
T
ERNATIONAL
REC
T
I
F
I
E
R
F530S
LOGO
DATE
C
ODE
P =
DE S I GN
A
T E S
L E AD-F R E E
PRODUCT (OPT
I
O
N
A
L)
Y
E
AR 0 =
2
000
A
S
SEMB
L
Y
L
O
T CODE
WEEK 02
A =
AS S E MB LY S IT E
C
ODE
8
IRL2505S/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
E
X
AM
P
L
E: THIS
IS AN IRL
3
103L
L
O
T CODE 1789
P
A
R
T NUMBER
I
N
T ERN
A
T I
O
N
A
L
RECTIFIER
L
O
GO
A
S
SEMBLED ON WW 19, 1997
IN THE A
S
SEMBLY
L
I
N
E
“
C
”
DATE
C
ODE
Y
E
A
R 7 =
1
997
WEE K
19
Note:
“
P
”
i
n
a
ssemb
l
y li
n
e
pos
i
ti
o
n
i
n
d
i
c
a
t
e
s
“
L
e
ad
–
F re
e
”
A
S
S
E
MB
L
Y
L
O
T CODE
LI
N
E C
OR
P
A
RT NUMBER
I
N
TERNATIONAL
REC
T
IFIER
L
O
GO
D
A
TE C
O
DE
P =
DES
I
G
NATES LE
A
D
-FREE
PRODUCT (OP
T
I
O
N
A
L)
Y
E
A
R 7 =
1
997
AS S E MB L Y
L
O
T CODE
WEEK 19
A =
A
S
SE
M
BLY
S
I
TE
C
ODE
9
IRL2505S/LPbF
D
2
Pak
T
a
pe & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1
.
6
0 (.063)
1
.
5
0 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
TRL
11.60 (.457)
11.40 (.449)
1
.
8
5 (.073)
1
.
6
5 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS
TO EIA-418.
2. CONTROLLING
DIMENSION: MILLIMETER.
3. DIMENSION
MEASURED @ HUB.
4. INCLUDES
FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
10
Note: For
the most current drawings please refer to the IR website at:
