Infineon-Technologies-IRLB3034PBF
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PD –
97363
IRLB3034PbF
HEXFET
®
Power MOSFET
Applications
l
DC Motor Drive
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
D
V
DSS
40V
R
DS(on)
typ.
1.4m
1.7m
343A
195A
max.
I
D (Silicon Limited)
I
D (Package Limited)
G
S
Benefits
l
Optimized for Logic Level Drive
l
Very Low R
DS(ON)
at 4.5V V
GS
l
Superior R*Q at 4.5V V
GS
l
Improved Gate,
Avalanche and Dynamic
dV/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
TO-220AB
IRLB3034PbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
Parameter
Max.
343
243
195
1372
375
2.5
Units
I
D
@ T
C
= 25°C
Continuous Drain Current, V
GS
@ 10V
(Silicon Limited)
I
D
@ T
C
= 100°C
I
D
@ T
C
= 25°C
I
DM
Continuous Drain Current, V
GS
@ 10V
(Silicon Limited)
A
Continuous Drain Current, V
GS
@ 10V (Package Limited)
Pulsed Drain Current
P
D
@T
C
= 25°C
W
Maximum Power Dissipation
Linear Derating Factor
W/°C
V
V
GS
±20
4.6
Gate-to-Source Voltage
Peak Diode Recovery
dv/dt
T
J
V/ns
Operating Junction and
-55 to
+ 175
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
°C
300
10lbf in (1.1N m)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy
E
AS (Thermally limited)
255
mJ
A
Avalanche Current
I
AR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy
E
AR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
0.5
Max.
0.4
Units
R
θ
JC
Junction-to-Case
R
θ
CS
R
θ
JA
–––
62
°C/W
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
–––
1
01/14/09
IRLB3034PbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max.
Units
40 –––
–––
––– 0.04 –––
V/°C Reference
to 25°C, I
D
= 5mA
Conditions
V
GS
= 0V, I
D
= 250µA
V
∆
V
(BR)DSS
/
∆
T
J
Breakdown Voltage Temp. Coefficient
–––
–––
1.0
1.4
1.6
1.7
2.0
2.5
20
V
GS
= 10V, I
D
= 195A
R
DS(on)
Static Drain-to-Source On-Resistance
m
Ω
V
GS
= 4.5V, I
D
= 172A
V
GS(th)
I
DSS
Gate Threshold Voltage
–––
V
V
DS
= V
GS
, I
D
= 250µA
Drain-to-Source Leakage Current
––– –––
V
DS
= 40V, V
GS
= 0V
V
DS
= 40V, V
GS
= 0V, T
J
= 125°C
V
GS
= 20V
µA
––– ––– 250
––– ––– 100
––– –––
-100
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
nA
V
GS
= -20V
R
G(int)
–––
2.1
–––
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Min. Typ. Max.
Units
Conditions
V
DS
= 10V, I
D
= 195A
286 ––– –––
S
Q
g
Total Gate Charge
––– 108 162
I
D
= 185A
Q
gs
Q
gd
Q
sync
t
d(on)
t
r
Gate-to-Source Charge
–––
–––
–––
–––
29
54
54
65
–––
–––
–––
–––
V
DS
= 20V
nC
Gate-to-Drain (“Miller”) Charge
Total Gate Charge Sync. (Q
g
– Q
gd
)
V
GS
= 4.5V
I
D
= 185A, V
DS
=0V, V
GS
= 4.5V
V
DD
= 26V
Turn-On Delay Time
Rise Time
––– 827 –––
––– 97 –––
I
D
= 195A
ns
t
d(off)
t
f
Turn-Off Delay Time
R
G
= 2.1
Ω
V
GS
= 4.5V
Fall Time
––– 355 –––
––– 10315 –––
––– 1980 –––
––– 935 –––
––– 2378 –––
––– 2986 –––
C
iss
C
oss
C
rss
Input Capacitance
V
GS
= 0V
Output Capacitance
V
DS
= 25V
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
ƒ = 1.0MHz
GS
= 0V, V
DS
= 0V to 32V
pF
C
oss
eff. (ER)
oss
eff. (TR)
V
C
V
GS
= 0V, V
DS
= 0V to 32V
Diode Characteristics
Symbol
Parameter
Continuous Source Current
Min. Typ. Max.
Units
Conditions
MOSFET symbol
D
S
I
S
––– –––
343
(Body Diode)
showing the
A
––– –––
G
I
SM
Pulsed Source Current
(Body Diode)
integral reverse
1372
p-n junction diode.
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
––– –––
1.3
–––
–––
–––
–––
–––
V
T
J
= 25°C, I
S
= 195A, V
GS
= 0V
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
V
R
= 34V,
–––
–––
–––
–––
–––
39
41
39
46
1.7
ns
I
F
= 195A
di/dt = 100A/µs
Q
rr
Reverse Recovery Charge
nC
A
I
RRM
t
on
Reverse Recovery Current
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
ꢀ
Pulse width
≤
400µs; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
Calcuted continuous current based on maximum allowable junction
temperature Bond wire current limit is 195A. Note that current
limitation arising from heating of the device leds may occur with
some lead mounting arrangements.
Repetitive rating;
pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.013mH
R
G
= 25
Ω
, I
AS
= 195A, V
GS
=10V. Part not recommended for use
above this value .
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
R
θ
is measured at T
J
approximately 90°C
.
I
SD
≤
195A, di/dt
≤
841A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
2
IRLB3034PbF
100000
10000
1000
100
100000
10000
1000
100
VGS
15V
10V
8.0V
4.5V
3.5V
3.0V
2.7V
2.5V
VGS
15V
10V
8.0V
4.5V
3.5V
3.0V
2.7V
2.5V
60µs PULSE WIDTH
Tj = 175°C
≤
TOP
60µs PULSE WIDTH
Tj = 25°C
TOP
≤
BOTTOM
BOTTOM
10
2.5V
2.5V
1
10
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
10000
1000
100
10
2.0
1.5
1.0
0.5
I
= 195A
= 10V
D
V
GS
T
= 175°C
J
T
= 25°C
J
1
V
= 25V
DS
≤
60µs PULSE WIDTH
0.1
1
2
3
4
5
-60 -40 -20
0 20
40 60 80
100120140160180
, Junction Temperature (°C)
T
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4.
Normalized On-Resistance vs. Temperature
Fig 3.
Typical Transfer Characteristics
100000
10000
1000
5.0
V
= 0V,
= C
f = 1 MHZ
GS
I =
185A
C
C
C
+ C
, C
SHORTED
ds
D
V
V
= 32V
= 20V
iss
gs
gd
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
DS
DS
= C
rss
oss
gd
= C
+ C
ds
gd
C
iss
C
oss
C
rss
100
1
10
100
0
20
40
60
80
100 120 140
V
, Drain-to-Source Voltage (V)
Q ,
Total Gate Charge (nC)
DS
G
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
3
IRLB3034PbF
10000
1000
100
10
10000
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
1000
100µsec
1msec
T
= 175°C
J
100
10
LIMITED BY PACKAGE
10msec
T
= 25°C
J
DC
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
0.1
1.0
0.1
1
10
100
0.0
0.5
1.0
1.5
2.0
2.5
V
, Drain-to-Source Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
350
50
48
46
44
42
40
Id = 5mA
Limited By Package
300
250
200
150
100
50
0
25
50
75
100
125
150
175
-60 -40 -20
0 20
40 60 80
100120140160180
T
, Case Temperature (°C)
T
, Temperature ( °C )
C
J
Fig 9.
Maximum Drain Current vs.
Fig 10.
Drain-to-Source Breakdown Voltage
Case Temperature
2.5
1200
I
D
TOP
38.9A
65.3A
1000
800
600
400
200
0
2.0
1.5
1.0
0.5
0.0
BOTTOM 195A
0
5
10 15 20 25 30 35 40 45
Drain-to-Source Voltage (V)
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
J
V
DS,
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy vs. DrainCurrent
4
IRLB3034PbF
1
D = 0.50
0.20
0.1
0.10
0.05
R
1
R
1
R
2
R
2
R
3
R
3
R
4
R
4
Ri (°C/W)
τ
i (sec)
0.02477
0.000025
τ
τ
J
τ
J
τ
C
τ
0.02
0.01
0.08004
0.000077
1
τ
1
Ci=
τ
i
/
Ri
τ
τ
τ
2
τ
2
3
τ
3
4
τ
4
0.01
0.19057 0.001656
0.10481 0.008408
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆
Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆
Τ
j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
300
250
200
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆
T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche =
t
av
·f
TOP
BOTTOM 1.0%
Duty Cycle
= 195A
Single Pulse
I
D
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
0
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
25
50
75
100
125
150
175
I
av
= 2
D
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Starting T
, Junction Temperature (°C)
J
Fig 15.
Maximum Avalanche Energy vs. Temperature
5
IRLB3034PbF
3.0
14
12
10
8
I =
78A
F
V
= 34V
2.5
2.0
1.5
R
T =
25°C
J
T =
125°C
J
6
I
I
= 250µA
D
D
1.0
0.5
0.0
= 1.0mA
4
ID = 1.0A
2
0
-75 -50 -25
0
25 50 75
100 125 150 175
0
100
200
300
400
500
T ,
Temperature ( °C )
di /dt
(A/µs)
J
F
Fig. 17
– Typical Recovery Current vs. di
f
/dt
Fig 16.
Threshold Voltage vs. Temperature
14
400
I =
117A
I =
78A
F
F
12
10
8
V
= 34V
V
= 34V
R
R
T =
25°C
T =
25°C
J
J
300
200
100
0
T =
125°C
J
T =
125°C
J
6
4
2
0
0
100
200
300
400
500
0
100
200
300
400
500
di /dt
(A/µs)
di /dt
(A/µs)
F
F
Fig. 18
– Typical Recovery Current vs. di
f
/dt
Fig. 19
– Typical Stored Charge vs. di
f
/dt
400
I =
117A
F
V
= 34V
R
T =
25°C
J
300
200
100
0
T =
125°C
J
0
100
200
300
400
500
di /dt
(A/µs)
F
Fig. 20
– Typical Stored Charge vs. di
f
/dt
6
IRLB3034PbF
Driver Gate Drive
P.W.
P
.
W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Current
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 21.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
V
2
GS
Ω
0.01
t
p
I
AS
Fig 22b.
Unclamped Inductive Waveforms
Fig 22a.
Unclamped Inductive Test Circuit
R
D
V
DS
V
DS
90%
V
GS
D.U.T.
R
G
+
V
DD
–
V
GS
10%
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a.
Switching Time Test Circuit
Fig 23b.
Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.
T
.
Vds
Vgs
50K
Ω
.2
µ
F
12V
.3
µ
F
+
V
DS
D.U.
T
.
–
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a.
Gate Charge Test Circuit
Fig 24b.
Gate Charge Waveform
7
IRLB3034PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
TO-220AB packages are not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
8
