Infineon-Technologies-IRLH5030TRPBF
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IRLH5030PbF
HEXFET
®
Power MOSFET
V
DS
100
9.9
V
R
DS(on) max
(@V
GS
= 4.5V)
Q
g (typical)
m
Ω
44
nC
R
G (typical)
1.2
Ω
I
D
88
A
(@T
mb
= 25°C)
PQFN 5X6 mm
Applications
•
Secondary Side Synchronous Rectification
•
Inverters for DC Motors
•
DC-DC Brick Applications
•
Boost Converters
Benefits
Features
≤
Ω
Low R
DSon
( 9.0m
)
Lower Conduction Losses
Enable better thermal dissipation
Increased Reliability
≤
Low Thermal Resistance to PCB (
0.8°C/W)
100% Rg tested
≤
Low Profile (
0.9 mm)
results in
Increased Power Density
Industry-Standard Pinout
Multi-Vendor Compatibility
Easier Manufacturing
Environmentally Friendlier
Increased Reliability
⇒
Compatible with Existing Surface Mount Techniques
RoHS Compliant Containing no Lead, no Bromide and no Halogen
MSL1, Industrial Qualification
Base Part Number
Package Type
Standard Pack
Form Quantity
Tape and Reel
Orderable part number
IRLH5030TRPBF
I
R
LH5030PBF
PQFN 5mm x 6mm
4000
Absolute Maximum Ratings
Parameter
Max.
±16
13
Units
V
V
GS
Gate-to-Source Voltage
I
D
@ T
A
= 25°C
I
D
@ T
A
= 70°C
I
D
@ T
mb
= 25°C
I
D
@ T
mb
= 100°C
I
DM
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
11
A
88
56
400
3.6
156
Power Dissipation
P
D
@T
A
= 25°C
P
D
@ T
mb
= 25°C
W
Power Dissipation
Linear Derating Factor
Operating Junction and
Storage Temperature Range
0.029
-55 to
+ 150
W/°C
°C
T
J
T
S
T
G
Notes
through
are on page 9
1
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1
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IRLH5030PbF
Static @ T
J
= 25°C (unless otherwise specified)
Parameter
Min. Typ. Max.
Units
100 ––– –––
––– 0.10 ––– V/°C
Reference to 25°C, I
D
= 1mA
Conditions
V
GS
= 0V, I
D
= 250
μ
A
BV
DSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
V
V
/ T
J
ΔΒ
DSS
Δ
R
DS(on)
–––
–––
1.0
7.2
7.9
9.0
9.9
2.5
V
GS
= 10V, I
D
= 50A
GS
= 4.5V, I
D
= 50A
m
Ω
V
V
GS(th)
Gate Threshold Voltage
–––
-5.9
–––
–––
–––
V
V
DS
= V
GS
, I
D
= 150
μ
A
V
Δ
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
160
–––
–––
–––
–––
–––
––– mV/°C
GS(th)
I
DSS
20
μ
A
V
DS
= 100V, V
GS
= 0V
V
DS
= 100V, V
GS
= 0V, T
J
= 125°C
V
GS
= 16V
250
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
100
nA
––– -100
V
GS
= -16V
V
DS
= 50V, I
D
= 50A
gfs
Q
g
Q
g
–––
94
–––
–––
66
S
nC V
GS
= 10V, V
DS
= 50V, I
D
= 50A
Total Gate Charge
44
Q
gs1
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
7.7
4.0
22
–––
–––
–––
V
DS
= 50V
Q
gs2
Q
gd
V
GS
= 4.5V
nC
I
D
= 50A
Q
godr
Gate Charge Overdrive
––– 10.3 –––
See Fig.17 & 18
Q
sw
Switch Charge (Q
gs2
+ Q
gd
)
Output Charge
–––
–––
26
20
–––
–––
Q
oss
nC
V
DS
= 16V, V
GS
= 0V
R
G
t
d(on)
t
r
Gate Resistance
Turn-On Delay Time
Rise Time
–––
–––
–––
–––
–––
1.2
21
72
41
41
–––
–––
–––
–––
–––
Ω
V
DD
= 50V, V
GS
= 4.5V
I
D
= 50A
R =1.8
ns
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
Ω
G
See Fig.15
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
––– 5185 –––
V
GS
= 0V
–––
–––
300
150
–––
–––
V
DS
= 50V
ƒ = 1.0MHz
pF
Avalanche Characteristics
Parameter
Typ.
–––
–––
Max.
230
50
Units
mJ
Single Pulse Avalanche Energy
E
AS
I
AR
Avalanche Current
A
Diode Characteristics
Parameter
Min. Typ. Max.
Units
Conditions
I
S
Continuous Source Current
MOSFET symbol
D
S
–––
–––
–––
–––
100
400
(Body Diode)
Pulsed Source Current
(Body Diode)
showing the
integral reverse
A
G
I
SM
p-n junction diode.
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
–––
–––
–––
–––
32
1.0
48
V
T
J
= 25°C, I
S
= 50A, V
GS
= 0V
ns T
J
= 25°C, I
F
= 50A, V
DD
= 50V
di/dt = 500A/
μ
s
nC
Q
rr
t
on
190
285
Time is dominated by parasitic Inductance
Thermal Resistance
Parameter
Typ.
0.5
Max.
0.8
15
Units
R
θ
JC-mb
Junction-to-Mounting Base
Junction-to-Case
R
θ
JC
(Top)
–––
–––
–––
°C/W
Junction-to-Ambient
Junction-to-Ambient
R
θ
JA
35
R
θ
JA
(<10s)
33
2
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IRLH5030PbF
1000
100
10
1000
100
10
VGS
10V
VGS
10V
TOP
TOP
5.0V
4.5V
3.5V
3.3V
3.0V
2.9V
2.7V
5.0V
4.5V
3.5V
3.3V
3.0V
2.9V
2.7V
BOTTOM
BOTTOM
2.7V
2.7V
60
μ
s PULSE WIDTH
Tj = 150°C
≤
60
μ
s PULSE WIDTH
≤
Tj = 25°C
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
100
10
2.5
2.0
1.5
1.0
0.5
I
= 50A
D
V
= 10V
GS
T
= 150°C
J
T
= 25°C
J
1
V
= 25V
DS
≤
60
μ
s PULSE WIDTH
0.1
1
2
3
4
5
6
7
8
9
10
-60 -40 -20
0
20 40 60 80
100 12
0
1
40 160
T
J
, Junction Temperature (°C)
V
, Gate-to-Source Voltage (V)
GS
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance vs. Temperature
100000
10000
1000
14.0
V
= 0V,
= C
f = 1 MHZ
GS
I =
50A
D
C
C
C
+ C
, C
SHORTED
ds
iss
gs
gd
12.0
= C
rss
oss
gd
V
V
V
= 80V
= 50V
= 20V
DS
DS
DS
= C
+ C
ds
gd
10.0
8.0
6.0
4.0
2.0
0.0
C
iss
C
C
oss
rss
100
1
10
100
1000
0
40
80
120
V
, Drain-to-Source Voltage (V)
Q
, Total
Gate Charge (nC)
DS
G
Fig 5.
Typical Capacitance vs.Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs.Gate-to-Source Voltage
3
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IRLH5030PbF
1000
100
10
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 150°C
J
100
μ
sec
T
= 25°C
1msec
J
10msec
1
1
Tc = 25°C
Tj = 150°C
0.1
DC
V
= 0V
1.2
Single Pulse
GS
0.01
0.1
0.1
1
10
100
1000
0.0
0.2
V
0.4
0.6
0.8
1.0
1.4
V
, Drain-to-Source Voltage (V)
, Source-to-Drain Voltage (V)
DS
SD
Fig 7.
Typical Source-Drain Diode Forward Voltage
Fig 8.
Maximum Safe Operating Area
100
2.5
80
60
40
20
0
2.0
1.5
1.0
0.5
I
I
I
I
= 150
μ
A
= 500
μ
A
= 1.0mA
= 1.0A
D
D
D
D
-75 -50 -25
0
25 50 75
100 125 150
25
50
T
75
100
125
150
, Case Temperature (°C)
T
, Temperature ( °C )
J
C
Fig 10.
Threshold Voltage vs. Temperature
Fig 9.
Maximum Drain Current vs.
Cas
e
T
emperature
10
1
D = 0.50
0.20
0.1
0.01
0.10
0.05
0.02
0.01
SINGLE PULSE
( THERMAL RESPONSE )
0.001
0.0001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t
, Rectangular Pulse Duration (sec)
1
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Mounting Base
4
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IRLH5030PbF
25
20
15
10
5
1000
900
800
700
600
500
400
300
200
100
0
I
= 50A
I
D
D
TOP
5.5A
12A
BOTTOM 50A
T
= 125°C
J
T
= 25°C
J
0
2
4
6
8
10 12 14 16 18 20
25
50
75
100
125
150
Starting T
, Junction Temperature (°C)
J
V
Gate -to -Source Voltage
(V)
GS,
Fig 13.
Maximum Avalanche Energy vs. Drain Current
Fig 12.
On-Resistance vs. Gate Voltage
1000
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
Δ
Tj = 125°C and
Tstart =25°C (Single Pulse)
100
10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
Δ
Τ
j = 25°C and
Tstart = 125°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.
Pulsewidth
5
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IRLH5030PbF
Driver Gate Drive
P.W.
P
.
W.
D =
Period
D.U.T
Period
+
*
=10V
V
GS
Circui
t
L
ayou
t
C
onsiderations
•
Lo
w
S
tra
y
I
nductance
•
Ground Plane
•
Lo
w
L
eakag
e
I
nductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/d
t
c
ontrolle
d
b
y
R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Curent
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 15.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
R
G
V
DD
–
I
A
AS
20V
I
AS
Ω
0.01
t
p
Fig 16b.
Unclamped Inductive Waveforms
Fig 16a.
Unclamped Inductive Test Circuit
R
D
V
DS
90%
V
DS
V
GS
D.U.T.
R
G
+
V
DD
–
10%
V
GS
1
V
GS
Puls
e
W
idth
≤ 1
µs
Dut
y
F
acto
r
≤ 0.1
t
d(on)
t
d(off)
t
r
t
f
Fig 17b.
Switching Time Waveforms
Fig 17a.
Switching Time Test Circuit
Id
Vds
Vgs
L
DUT
0
Vgs(th)
1K
Qgs1
Qgs2
Qgd
Qgodr
Fig 18a.
Gate Charge Test Circuit
Fig 18b.
Gate Charge Waveform
6
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IRLH5030PbF
PQFN 5×6 Outline “B” Package Details
PQFN 5×6 Outline “G” Package Details
For more information on board mounting, including footprint and stencil recommendation, please refer to application note AN-1136:
For more information on package inspection techniques, please refer to application note AN-
1
1
54:
7
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1
y9, 2015
IRLH5030PbF
PQFN 5×6 Part Marking
INTERNATIONAL
RECTIFIER LOGO
DATE CODE
PART NUMBER
XXXX
XYWWX
XXXXX
(“4 or 5 digits”)
ASSEMBLY
SITE CODE
(Per SCOP 200-002)
MARKING CODE
(Per Marking Spec)
PIN 1
IDENTIFIER
LOT CODE
(Eng Mode – Min last 4 digits of EATI#)
(Prod Mode – 4 digits of SPN code)
PQFN 5×6 Tape and Reel
REEL DIMENSIONS
TAPE DIMENSIONS
CODE
D
E
S
C
R
IPTI
O
N
Ao
Bo
Ko
W
Dimen
s
i
o
n des
i
gn to
a
ccommodate the component w
i
d
th
Dimen
s
i
o
n des
i
g
n to accommodate the component
l
e
nght
Di
m
en
s
i
o
n de
s
i
g
n to accommodate the component th
i
c
kne
s
s
Ove
r
a
l
l
w
i
dth of the ca
r
ri
e
r tape
P
1
Pit
c
h between s ucce
s
s i
v
e cav
i
t
y cente
r
s
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Note: All
d
i
m
ens
i
o
n a
r
e nom
i
n
a
l
P
a
c
k
a
ge
T
y
pe
R
e
el
Di
a
meter
(In
c
h)
QT Y
R
e
el
W
i
d
th
W1
Ao
(mm)
Bo
(mm)
Ko
(mm)
P1
(mm)
W
(
m
m)
Pin 1
Quad
r
a
nt
(mm)
5 X 6 P
Q
F
N
13
4000
12.4
6.300
5.300
1.20
8.00
12
Q1
8
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IRLH5030PbF
Qualification information
†
I
n
du
s
t
r
i
a
l
††
(
p
er
J
E
D
E
C JES
D
47F
†††
g
u
i
d
e
l
ines )
Qualification level
MS L 1
Moisture Sensitivity Level
RoHS compliant
PQFN 5mm x 6mm
(
p
er
J
E
D
E
C J-
S
T
D
-020D
†††
)
Yes
Qualification standards can be found at International Rectifier’s web site
Higher qualification ratings may be available should the user have such requirements.
Please contact your International Rectifier sales representative for further information:
Applicable version of JEDEC standard at the time of product release.
Notes:
Repetitive rating;
pulse width limited by max. junction temperature.
Starting T
J
= 25°C, L = 0.18mH, R
G
= 25
Ω
, I
AS
= 50A.
Pulse width
≤
400
μ
s; duty cycle
≤
2%.
R
is measured at T
J
of approximately 90°C.
θ
ꢀ
When mounted on 1 inch square
2 oz copper pad on 1.5×1.5 in. board of FR-4 material.
Calculated continuous current based on maximum allowable junction temperature.
Revision History
Date
Comment
•
Updated package outline for “option B” and
added package outline for “option G” on page 7
4/28/2015
•
U
pdated tape and reel on page 8.
•
•
Updated package outline for “option G” on page 7.
Updated “IFX logo” on page 1 and page 9.
5/19/2015
IR WORLD HEADQUARTERS:
101 N. Sepulveda Blvd., El Segundo, California 90245, USA
9
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