Infineon-Technologies-IRLR3114ZTRPBF
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PD – 97284A
IRLR3114ZPbF
IRLU3114ZPbF
Features
HEXFET
®
Power MOSFET
Advanced Process Technology
Ultr
a
L
o
w
O
n-Resistance
175°
C
O
peratin
g
T
emperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Logic Level
D
V
DSS
= 40V
G
R
DS(on)
= 4.9m
Ω
Description
Thi
s
H
EXFET
®
Powe
r
M
OSFE
T
u
tilize
s
t
h
e
l
atest
processing techniques to achieve extremely low
on-resistanc
e
p
e
r
s
ilico
n
a
rea. Additiona
l
f
eatures
of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitiv
e
a
valanch
e
r
ating. Thes
e
f
eature
s
c
ombine
to make this design an extremely efficient and
reliable device for use in a wide variety of
applications.
S
D-Pak
IRLR3114ZPbF
I-Pak
IRLU3114ZPbF
Absolute Maximum Ratings
Parameter
Max.
Units
I
I
I
I
@ T
= 25°C
C
130
(Silicon Limited)
(Silicon Limited)
(Package Limited)
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
D
D
D
@ T
= 100°C
C
89
A
@ T
= 25°C
C
42
500
140
DM
P
@T =
25°C
Power Dissipation
C
W
D
Linear Derating Factor
0.95
±16
W/°C
V
V
Gate-to-Source Voltage
GS
E
AS (Thermally limited)
130
260
mJ
Single Pulse Avalanche Energy
E
AS
(Tested )
Single Pulse Avalanche Energy Tested Value
Avalanche Current
I
AR
See Fig.12a, 12b, 15, 16
A
E
AR
mJ
Repetitive Avalanche Energy
T
J
-55 to
+ 175
Operating Junction and
T
°C
Storage Temperature Range
STG
Reflow Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
300
10 lbf
in (1.1N m)
Thermal Resistance
Parameter
Typ.
–––
–––
–––
Max.
1.05
40
Units
R
θ
JC
Junction-to-Case
R
θ
JA
R
θ
JA
°C/W
Junction-to-Ambient (PCB mount)
Junction-to-Ambient
110
HEXFET
®
i
s
a
r
egistere
d
t
rademar
k
o
f
I
nternationa
l
R
ectifier.
1
10/01/10
IRLR/U3114ZPbF
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max.
Units
40 –––
–––
Conditions
V
GS
= 0V, I
D
= 250µA
V
(BR)DSS
V
∆
V
(BR)DSS
/
∆
T
J
R
DS(on)
Breakdown Voltage Temp. Coefficient
––– 0.032 –––
V/°C Reference
to 25°C, I
D
= 1mA
m
Ω
Static Drain-to-Source On-Resistance
–––
–––
1.0
3.9
5.2
–––
–––
–––
–––
–––
–––
40
4.9
6.5
V
GS
= 10V, I
D
= 42A
V
GS
= 4.5V, I
D
= 42A
V
DS
= V
GS
, I
D
= 100µA
V
DS
= 10V, I
D
= 42A
V
GS(th)
Gate Threshold Voltage
2.5
V
S
gfs
I
DSS
Forward Transconductance
Drain-to-Source Leakage Current
98
–––
20
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
µA
V
DS
= 40V, V
GS
= 0V
250
100
-100
56
V
DS
= 40V, V
GS
= 0V, T
J
= 125°C
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
nA V
GS
= 16V
GS
= -16V
I
D
= 42A
DS
= 20V
V
Q
g
Q
gs
Q
gd
t
d(on)
t
r
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Turn-On Delay Time
12
–––
–––
–––
–––
–––
–––
–––
nC
V
18
V
GS
= 4.5V
V
DD
= 20V
I
D
= 42A
25
Rise Time
140
33
t
d(off)
t
f
Turn-Off Delay Time
ns
R
G
= 3.7
Ω
V
GS
= 4.5V
Fall Time
50
D
S
L
D
Internal Drain Inductance
4.5
Between lead,
nH 6mm
(0.25in.)
from package
G
L
S
Internal Source Inductance
–––
7.5
–––
and center of die contact
V
GS
= 0V
DS
= 25V
pF ƒ
= 1.0MHz
C
iss
Input Capacitance
––– 3810 –––
C
oss
Output Capacitance
–––
–––
650
350
–––
–––
V
C
rss
Reverse Transfer Capacitance
Output Capacitance
C
oss
––– 2390 –––
V
GS
= 0V,
V
DS
= 1.0V,
ƒ = 1.0MHz
V
GS
= 0V,
V
DS
= 32V,
ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 32V
C
oss
Output Capacitance
–––
–––
580
820
–––
–––
C
oss
eff.
Effective Output Capacitance
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max.
Units
Conditions
MOSFET symbol
D
I
Continuous Source Current
–––
–––
130
S
(Body Diode)
Pulsed Source Current
A
showing the
integral reverse
G
I
–––
–––
500
SM
S
(Body Diode)
p-n junction diode.
V
t
Diode Forward Voltage
–––
–––
–––
–––
30
1.3
45
41
V
T =
25°C, I
= 42A, V
= 0V
SD
J S GS
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
ns T
= 25°C, I
= 42A, V
DD
= 20V
J F
rr
di/dt = 100A/µs
Q
t
27
nC
rr
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
on
2
IRLR/U3114ZPbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
4.5V
3.5V
3.0V
2.7V
2.5V
VGS
15V
10V
8.0V
4.5V
3.5V
3.0V
2.7V
2.5V
TOP
TOP
BOTTOM
BOTTOM
2.5V
1
60µs PULSE WIDTH
Tj = 175°C
≤
2.5V
60µs PULSE WIDTH
Tj = 25°C
≤
1
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
200
150
100
50
T
= 25°C
J
100
10
1
T
= 175°C
J
T
= 25°C
J
T
= 175°C
J
V
= 10V
DS
380µs PULSE WIDTH
V
= 15V
DS
≤
60µs PULSE WIDTH
0.1
0
1
2
3
4
5
6
7
0
20
40
60
80
100
I
,Drain-to-Source Current (A)
D
V
, Gate-to-Source Voltage (V)
GS
Fig 3.
Typical Transfer Characteristics
Fig 4.
Typical Forward Transconductance
vs. Drain Current
3
IRLR/U3114ZPbF
100000
6.0
5.0
4.0
3.0
2.0
1.0
0.0
V
= 0V,
= C
f = 1 MHZ
GS
I
= 42A
V
D
C
C
C
+ C
, C
SHORTED
iss
gs
gd
ds
= C
rss
oss
gd
= 32V
= 20V
= 8.0V
DS
= C
+ C
ds
gd
V
V
DS
DS
10000
1000
100
C
iss
C
oss
C
rss
1
10
, Drain-to-Source Voltage (V)
100
0
10
20
30
40
50
V
Q , Total
Gate Charge (nC)
DS
G
Fig 6.
Typical Gate Charge vs.
Fig 5.
Typical Capacitance vs.
Gate-to-Sourc
e
V
oltage
Drain-to-Sourc
e
V
oltage
1000
100
10
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
100µsec
1msec
10msec
Tc = 25°C
T
= 25°C
J
Tj = 175°C
Single Pulse
V
= 0V
GS
DC
1.0
1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
1
10
, Drain-to-Source Voltage (V)
100
V
, Source-to-Drain Voltage (V)
V
SD
DS
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
4
IRLR/U3114ZPbF
2.0
1.5
1.0
0.5
140
120
100
80
I
= 42A
D
V
= 10V
GS
Limited By Package
60
40
20
0
-60 -40 -20
0 20
40 60 80
100120140160180
, Junction Temperature (°C)
25
50
75
100
125
150
175
T
T
, Case Temperature (°C)
J
C
Fig 10.
Normalized On-Resistance
Fig 9.
Maximum Drain Current vs.
vs
.
T
emperature
Cas
e
T
emperature
10
1
D = 0.50
0.20
0.10
0.05
R
1
R
1
R
2
R
2
R
3
R
3
R
4
R
4
Ri (°C/W)
τ
i (sec)
0.1
0.01
0.0350
0.2433
0.4851
0.2867
0.000013
0.000077
0.001043
0.004658
τ
τ
J
τ
J
τ
C
τ
1
τ
1
Ci=
τ
i
/
Ri
τ
τ
τ
2
τ
2
3
τ
3
4
τ
4
0.02
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
IRLR/U3114ZPbF
600
500
400
300
200
100
0
15V
I
D
TOP
9.7A
17A
BOTTOM 42A
DRIVER
L
V
DS
D.U.T
AS
R
+
–
G
V
DD
I
A
2
V
0
G
V
S
Ω
0.01
t
p
Fig 12a.
Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
J
I
AS
Fig 12c.
Maximum Avalanche Energy
Fig 12b.
Unclamped Inductive Waveforms
vs. Drain Current
Q
G
10 V
Q
Q
3.0
2.5
2.0
1.5
1.0
0.5
GS
GD
V
G
Charge
Fig 13a.
Basic Gate Charge Waveform
I
I
I
I
= 150µA
= 250µA
= 1.0mA
= 1.0A
D
D
D
D
L
VCC
DUT
0
1K
-75 -50 -25
0
25 50 75
100 125 15
0
1
75 200
, Temperature ( °C )
T
J
Fig 14.
Threshold Voltage vs. Temperature
Fig 13b.
Gate Charge Test Circuit
6
IRLR/U3114ZPbF
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆
Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆
Τ
j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15.
Typical Avalanche Current vs.Pulsewidth
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long as
neither Tjmax nor Iav (max) is exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. P
D (ave)
= Average power dissipation per single
avalanche pulse.
150
100
50
TOP
BOTTOM 1.0%
Duty Cycle
= 42A
Single Pulse
I
D
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆
T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as 25°C in Figure 15, 16).
t
av =
Average time in avalanche.
0
D = Duty cycle in avalanche =
t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see figure 11)
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
J
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
Fig 16.
Maximum Avalanche Energy
I
av
= 2
D
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
vs
.
T
emperature
7
IRLR/U3114ZPbF
Driver Gate Drive
P.W.
P
.
W.
Period
Period
D =
D.U.T
+
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Curent
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 17.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
R
D
V
DS
V
GS
D.U.T.
R
G
+
V
DD
–
10V
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
Fig 18a.
Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 18b.
Switching Time Waveforms
8
IRLR/U3114ZPbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EX
A
M
P
LE: THIS
IS
A
N
I
RFR120
P
A
R
T NU
M
B
ER
W
I
T H
A
S S E M
B
LY
L
O
T CODE 1234
A
S
SE
M
B
LED
O
N WW
1
6, 2001
IN
T
H
E
A
S
SE
M
B
LY LI
N
E “
A
”
IN
T
ERN
A
T
I
O
NAL
RE
C
T
I
F
IER
L
O
GO
DAT E
CO
D
E
Y
E
A
R 1 =
2
001
WE E K
1
6
IRFR120
116A
34
12
LINE A
Note: “
P
” in
a
s
s
e
mb
l
y lin
e
p
o
s
i
ti
o
n
AS S
E
M
B
L Y
L
O
T CODE
indicates “L
ead-F ree”
“
P
” in
a
s
s
e
mb
l
y lin
e
p
o
s
i
tion indi
c
a
t
es
“L ead
–
F r
e
e” qua
l
ifi
c
at
i
o
n to the cons ume
r
-l
e
v
el
P
A
R
T NU
M
B
ER
IN
T
ERN
A
T
I
ONAL
RE
C
T
I
FIER
L
O
GO
DAT E
CODE
P =
DE
S
I
G
N
A
T
ES LE
A
D
–
FREE
PR
O
D
U
C
T (O
P
TI
O
N
A
L
)
OR
IRFR120
12 34
P =
DE
S
I
G
N
A
T
ES LE
A
D
–
FREE
PR
O
D
U
C
T Q
U
A
L
I
F
IED TOTHE
CO
N
S
U
M
E
R LE
V
E
L (
O
P
TI
O
N
A
L
)
AS S
E
M
B
L Y
L
O
T CODE
Y
E
A
R 1 =
2
001
WE E K
1
6
A =
A
S S E MB L Y S I T E
CODE
Notes:
9
IRLR/U3114ZPbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
P
A
R
T N
U
M
B
ER
EX
A
MP
L
E: THIS
IS
A
N
I
RFU120
W
I
T H
A
S S E MB
L
Y
IN
T
ER
N
A
T
I
O
N
A
L
RE
C
T
I
FIER
L
O
GO
D
A
T E
CO
D
E
Y
E
A
R 1 =
2001
WE E K
1
9
IR
F
U
1
20
119A
78
L
O
T CODE
5
678
A
S
SE
M
B
LED
O
N W
W
1
9, 2001
IN
T
H
E
A
S
SE
M
B
LY LI
N
E “A”
56
LINE A
AS S
E
M
B
L Y
L
O
T CODE
Note: “P” in
a
s
s
e
mb
l
y
l
in
e
p
o
s
i
t
i
o
n
indi
c
a
t
es L
e
a
d
–
Fr
e
e”
OR
P
A
R
T N
U
M
B
ER
D
A
T E
CO
D
E
P =
D
E
S
I
GN
A
T
ES LE
A
D-
F
REE
PR
O
D
U
C
T
(
O
P
T
I
O
N
A
L
)
IN
T
ER
N
A
T
I
O
N
A
L
RE
C
T
I
FIER
L
O
GO
IRFU120
56
78
Y
E
A
R 1 =
2001
AS S
E
M
B
LY
L
O
T CODE
WE E K
1
9
A=
A
S
SE
M
B
LY
SITE
C
ODE
Notes:
10
IRLR/U3114ZPbF
D-Pak (TO-252AA)
T
a
pe & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRL
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
FEED DIRECTION
NOTES :
1. CONTROLLING
DIMENSION : MILLIMETER.
2. ALL
DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE
CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
ꢀ
C
oss
eff. is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
Repetitive rating;
pulse width limited by
max. junction temperature. (See fig. 11).
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.15mH
R
G
= 25
Ω
, I
AS
= 42A, V
GS
=10V. Part not
recommended for use above this value.
Pulse width
≤
1.0ms; duty cycle
≤
2%.
.
Limited by T
Jmax
, see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
When mounted on 1″ square PCB (FR-4 or G-10 Material).
R
θ
is measured at T
J
approximately 90°C.
Data and specifications subject to change without notice.
This product has been designed
for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
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