Infineon-Technologies-IRLR3410TRRPBF
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PD – 95087A
IRLR/U3410PbF
HEXFET
®
Power MOSFET
l
Logic Level Gate Drive
l
Ultra Low On-Resistance
l
Surface Mount (IRLR3410)
l
Straight Lead (IRLU3410)
l
Advanced Process Technology
l
Fast Switching
D
V
DSS
= 100V
R
DS(on)
= 0.105
Ω
G
l
Fully Avalanche Rated
l
Lead-Free
I
D
= 17A
S
Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve the
lowest possible on-resistance per silicon area.
This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer
with an extremely efficient device for use in a wide
variety of applications.
D-PAK
I-PAK
TO-251AA
TO-252AA
The D-PAK is designed for surface mounting using
vapor phase,
infrared, or wave soldering techniques.
The straight lead version (IRFU series) is for through-
hole mounting applications.
Power dissipation levels
up to 1.5 watts are possible in typical surface mount
applications.
Absolute Maximum Ratings
Parameter
Max.
Units
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
ꢀ
17
12
A
60
P
D
@T
C
= 25°C
Power Dissipation
79
W
W/°C
V
Linear Derating Factor
0.53
± 16
150
9.0
7.9
5.0
V
GS
E
AS
I
AR
Gate-to-Source Voltage
Single Pulse Avalanche Energy
ꢀ
Avalanche Current
ꢀ
mJ
A
E
AR
dv/dt
T
J
Repetitive Avalanche Energy
ꢀ
Peak Diode Recovery dv/dt
Operating Junction and
mJ
V/ns
-55 to
+ 175
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
–––
–––
Max.
1.9
Units
°C/W
1
R
θ
JC
R
θ
JA
Junction-to-Ambient (PCB mount) **
Junction-to-Ambient
50
R
θ
JA
110
12/7/04
IRLR/U3410PbF
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
100 –––
–––
Conditions
V
GS
= 0V, I
D
= 250µA
V
(BR)DSS
V
∆
V
(BR)DSS
/
∆
T
J
Breakdown Voltage Temp. Coefficient
––– 0.122
––– V/°C
Reference to 25°C, I
D
= 1mA
––– –––
0.105
––– –––
0.125
––– –––
0.155
V
GS
= 10V, I
D
= 10A
R
DS(on)
Static Drain-to-Source On-Resistance
W
V
GS
= 5.0V, I
D
= 10A
V
GS
= 4.0V, I
D
= 9.0A
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 25V, I
D
= 9.0A
ꢀ
V
GS(th)
g
fs
Gate Threshold Voltage
1.0
7.7
––– 2.0
––– –––
V
S
Forward Transconductance
––– ––– 25
––– –––
250
––– –––
100
––– –––
-100
––– ––– 34
––– ––– 4.8
––– ––– 20
V
DS
= 100V, V
GS
= 0V
V
DS
= 80V, V
GS
= 0V, T
J
= 150°C
GS
= 16V
I
DSS
I
GSS
Drain-to-Source Leakage Current
µA
nA
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
V
V
GS
= -16V
I
D
= 9.0A
Q
g
Q
gs
Q
gd
t
d(on)
t
r
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Turn-On Delay Time
Rise Time
nC V
DS
= 80V
V
GS
= 5.0V, See Fig. 6 and 13
ꢀ
–––
–––
–––
–––
7.2 –––
53 –––
30 –––
26 –––
V
DD
= 50V
I
D
= 9.0A
ns
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
R
G
= 6.0
Ω,
V
GS
= 5.0V
R
D
= 5.5
Ω,
See Fig. 10
ꢀ
Between lead,
D
S
L
D
L
S
Internal Drain Inductance
Internal Source Inductance
4.5
nH
6mm (0.25in.)
G
from package
––– 7.5 –––
and center of die contact
V
GS
= 0V
C
iss
C
oss
C
rss
Input Capacitance
––– 800
–––
––– 160
–––
Output Capacitance
pF
V
DS
= 25V
Reverse Transfer Capacitance
–––
90 –––
ƒ = 1.0MHz, See Fig. 5
ꢀ
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
MOSFET symbol
showing the
D
S
I
S
17
60
––– –––
––– –––
A
G
I
SM
Pulsed Source Current
(Body Diode)
ꢀ
integral reverse
p-n junction diode.
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 1.3
––– 140 210
V
T
J
= 25°C, I
S
= 9.0A, V
GS
= 0V
ns
T
J
= 25°C, I
F
=9.0A
Q
rr
t
on
––– 740
1100 nC di/dt
= 100A/µs
ꢀ
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Notes:
Repetitive rating;
pulse width limited by
max. junction temperature. ( See fig. 11 )
V
DD
= 25V, starting T
J
= 25°C, L = 3.1mH
R
G
= 25
Ω
, I
AS
= 9.0A. (See Figure 12)
Pulse width
≤
300µs; duty cycle
≤
2%
ꢀ
Uses IRL530N data and test conditions
I
SD
≤
9.0A, di/dt
≤
540A/µs, V
DD
≤
V
(BR)DSS
T
J
≤
175°C
,
This is applied for I-PAK, L
S
of D-PAK is measured between lead and
center of
die contact
** When
mounted on 1″ square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
2
IRLR/U3410PbF
100
10
1
100
10
1
VGS
15V
VGS
15V
TOP
TOP
12V
10V
8.0V
6.0V
4.0V
3.0V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
BOTTOM 2.5V
2.5V
2.5V
20µs PULSE WIDTH
20µs PULSE WIDTH
T
= 175°C
T
= 25°C
J
J
0.1
0.1
0.1
A
A
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 2.
Typical Output Characteristics
Fig 1.
Typical Output Characteristics
3.0
2.5
2.0
1.5
1.0
0.5
0.0
100
I
= 15A
D
T
J
= 25°C
T
J
= 175°C
10
1
V
D
S
= 50V
20µs PULSE WIDTH
1
0
A
V
= 10V
GS
0.1
A
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
2
3
4
5
6
7
8
9
T ,
Junction Temperature (°C)
V
GS
, Gate-to-Source Voltage (V)
J
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
3
IRLR/U3410PbF
1400
15
12
9
V
C
C
C
= 0V,
f = 1MHz
I
= 9.0A
D
GS
iss
rss
oss
= C
+ C
,
C
SHORTED
V
V
V
= 80V
= 50V
= 20V
gs
gd
ds
DS
DS
DS
= C
gd
1200
1000
800
600
400
200
0
= C
+ C
ds
gd
C
iss
6
C
oss
C
rss
3
FOR TEST CIRCUIT
SEE FIGURE 13
0
A
A
1
10
100
0
10
20
30
40
50
V
, Drain-to-Source Voltage (V)
Q
, Total Gate Charge (nC)
DS
G
Fig 5.
Typical Capacitance Vs.
Fig 6.
Typical Gate Charge Vs.
Drain-to-Source Voltage
Gate-to-Source Voltage
100
10
1
1000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
T =
175°C
J
100
10
1
10µs
T =
25°C
J
100µs
1ms
T
T
= 25°C
C
J
= 175°C
Single Pulse
V
= 0V
10ms
GS
A
A
0.4
0.6
0.8
1.0
1.2
1.4
1
10
100
1000
V
, Drain-to-Source Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 7.
Typical Source-Drain Diode
Fig 8.
Maximum Safe Operating Area
Forward Voltage
4
IRLR/U3410PbF
20
15
10
5
R
D
V
DS
V
GS
D.U.T.
R
G
+
V
DD
–
5.0V
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
Fig 10a.
Switching Time Test Circuit
V
DS
90%
0
25
50
75
100
125
150
175
°
T ,
Case Temperature
( C)
C
10%
V
GS
Fig 9.
Maximum Drain Current Vs.
t
t
r
t
t
f
d(on)
d(off)
Case Temperature
Fig 10b.
Switching Time Waveforms
10
D = 0.50
0.20
1
0.10
0.05
P
2
DM
0.1
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
t
1
t
2
Notes:
1. Duty factor D =
t /
t
1
2. Peak T
=
P
x Z
+ T
C
J
DM
thJC
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t ,
Rectangular Pulse Duration (sec)
1
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
IRLR/U3410PbF
350
300
250
200
150
100
50
I
D
TOP
3.7A
6.4A
BOTTOM 9.0A
15V
DRIVER
+
L
V
DS
D.U.T
R
G
V
DD
–
I
A
AS
10V
Ω
0.01
t
p
Fig 12a.
Unclamped Inductive Test Circuit
V
= 25V
50
DD
0
A
175
25
75
100
125
150
Starting T
, Junction Temperature (°C)
V
(BR)DSS
J
t
p
Fig 12c.
Maximum Avalanche Energy
Vs. Drain Current
I
AS
Current Regulator
Same Type as D.U.
T
.
Fig 12b.
Unclamped Inductive Waveforms
50K
Ω
.2
µ
F
12V
.3
µ
F
Q
G
+
5.0 V
V
DS
D.U.
T
.
–
Q
Q
GD
GS
V
GS
V
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 13a.
Basic Gate Charge Waveform
Fig 13b.
Gate Charge Test Circuit
6
IRLR/U3410PbF
Peak Diode Recovery dv/dt Test Circuit
+
–
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
D.U.T
+
–
–
+
R
G
•
dv/dt controlled by R
G
+
–
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
V
DD
Driver Gate Drive
P.W.
P
.
W.
Period
Period
D =
V
=10V
*
GS
D.U.
T
. I
W
aveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 14.
For N-Channel HEXFETS
7
IRLR/U3410PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EX
A
M
P
LE: THIS
IS
A
N
I
RFR
1
20
P
A
R
T
N
U
M
B
ER
W
I
T H
A
S S E M
B
L Y
L
O
T CO
D
E 1234
A
S
SE
M
B
LED
O
N WW 16, 1999
IN THE
A
S
SE
M
B
LY LI
N
E “A”
IN
T
ERN
A
T
I
O
N
A
L
RE
C
T
I
F
IER
L
O
GO
DAT E
CODE
Y
E
A
R 9 =
1
999
W
E
E K
16
IRFU120
916A
12
34
LINE A
Note: “P” in
a
s
s
e
mb
l
y lin
e
p
o
s
i
t
i
o
n
A
S
SE
M
B
LY
L
O
T CODE
indicates “L
ead
–
Fr
e
e”
OR
P
A
R
T
N
U
M
B
ER
DAT E
CODE
P =
DE S IGNAT E S
L E AD-F R E E
PR
O
D
U
C
T (O
P
T
I
O
N
A
L
)
IN
T
ER
N
A
T
I
O
NAL
RE
C
T
I
F
IER
L
O
GO
IRFU120
12 34
Y
E
A
R 9 =
1
999
A
S
SE
M
B
LY
L
O
T CODE
W
E
E K
16
A=
A
S
SE
M
B
LY
SITE
C
ODE
8
IRLR/U3410PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
P
A
R
T
N
U
M
B
ER
E
X
A
M
P
LE: THIS
IS
A
N
I
RFU120
IN
T
ER
N
A
T
I
O
NAL
RE
C
T
I
F
IER
L
O
GO
W
I
TH
A
S
SE
M
B
LY
L
O
T CODE 5678
A
S
SE
M
B
LED
O
N W
W
1
9, 1999
IN
T
HE
A
S
SE
M
B
LY LINE “
A
”
DA
T
E
C
ODE
Y
E
A
R 9 =
1999
W
E
EK
1
9
IR
F
U120
919A
78
56
LINE A
A
S
SE
M
B
LY
L
O
T CODE
Note:
“P” i
n
a
s
s
e
mb
l
y
l
i
n
e
po
s
i
ti
o
n
i
n
d
i
c
ates “
L
e
ad
–
F
r
ee”
OR
P
A
R
T NU
M
B
ER
DA
T
E
C
ODE
P =
DE S IGNAT E S
L
E
A
D
–
F R EE
PR
O
D
U
C
T (O
P
TI
O
NA
L
)
IN
T
ERN
A
T
I
O
NAL
RE
C
T
I
FIER
L
O
GO
IRFU120
56 78
Y
E
A
R 9 =
1
999
A
S
SE
M
B
LY
L
O
T CODE
W
E
EK 19
A=
A
S
SE
M
B
LY
SITE
C
ODE
9
IRLR/U3410PbF
D-Pak (TO-252AA)
T
a
pe & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRL
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
FEED DIRECTION
NOTES :
1. CONTROLLING
DIMENSION : MILLIMETER.
2. ALL
DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE
CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
10
Note: For
the most current drawings please refer to the IR website at:
