Infineon-Technologies-IRLR7833TRPBF
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PD – 95092C
IRLR7833PbF
IRLU7833PbF
HEXFET
®
Power MOSFET
Applications
V
DSS
R
DS(on)
max
Qg
l
High Frequency Synchronous Buck
Converters for Computer Processor Power
l
High Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Industrial Use
l
Lead-Free
4.5m
30V
33nC
Benefits
l
Very Low RDS(on) at 4.5V V
GS
l
Ultra-Low Gate Impedance
l
Fully Characterized Avalanche Voltage
and Current
D-Pak
I-Pak
IRLR7833PbF IRLU7833PbF
Absolute Maximum Ratings
Parameter
Drain-to-Source Voltage
Max.
30
Units
V
V
DS
V
Gate-to-Source Voltage
± 20
140
99
GS
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
I
I
I
@ T
C
= 25°C
@ T
C
= 100°C
D
D
A
560
140
71
DM
Maximum Power Dissipation
Maximum Power Dissipation
P
P
@T
C
= 25°C
@T
C
= 100°C
W
D
D
Linear Derating Factor
Operating Junction and
0.95
-55 to
+ 175
W/°C
°C
T
J
T
Storage Temperature Range
STG
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
300 (1.6mm from case)
10 lbf in (1.1N m)
Thermal Resistance
Parameter
Typ.
–––
–––
–––
Max.
1.05
50
Units
R
θ
JC
R
θ
JA
R
θ
JA
Junction-to-Case
Junction-to-Ambient (PCB Mount)
Junction-to-Ambient
°C/W
110
Notes
through
ꢀ
are on page 11
1
05/19/09
IRLR/U7833PbF
Static @ T
J
= 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max.
Units
Conditions
V
GS
= 0V, I
D
= 250µA
BV
DSS
∆Β
30
–––
–––
V
∆
V
DSS
/ T
J
Breakdown Voltage Temp. Coefficient
–––
19
––– mV/°C
Reference to 25°C, I
D
= 1mA
R
DS(on)
Static Drain-to-Source On-Resistance
–––
–––
1.4
3.6
4.4
–––
-6.0
–––
–––
–––
–––
–––
33
4.5
5.5
2.3
V
GS
= 10V, I
D
= 15A
Ω
m
V
GS
= 4.5V, I
D
= 12A
V
DS
= V
GS
, I
D
= 250µA
V
GS(th)
Gate Threshold Voltage
V
∆
∆
V
GS(th)
/ T
J
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
66
––– mV/°C
I
DSS
1.0
µA
V
DS
= 24V, V
GS
= 0V
150
V
DS
= 24V, V
GS
= 0V, T
J
= 125°C
V
GS
= 20V
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
100
nA
-100
V
GS
= -20V
gfs
Q
g
–––
50
S
V
DS
= 15V, I
D
= 12A
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Q
gs1
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
8.7
2.1
13
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
V
DS
= 16V
GS
= 4.5V
Q
gs2
Q
gd
V
nC
I
D
= 12A
Q
godr
Gate Charge Overdrive
Switch Charge (Q
gs2
+ Q
gd
)
9.9
15
See Fig. 16
Q
sw
Q
oss
t
d(on)
t
r
Output Charge
22
nC V
DS
= 16V, V
GS
= 0V
DD
= 15V, V
GS
= 4.5V
Turn-On Delay Time
Rise Time
14
V
6.9
23
I
D
= 12A
ns
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
Clamped Inductive Load
15
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
––– 4010 –––
V
GS
= 0V
–––
–––
950
470
–––
–––
V
DS
= 15V
pF
ƒ = 1.0MHz
Avalanche Characteristics
Parameter
Typ.
–––
–––
–––
Max.
Units
mJ
A
Single Pulse Avalanche Energy
E
AS
I
AR
530
20
Avalanche Current
Repetitive Avalanche Energy
E
AR
14
mJ
Diode Characteristics
Parameter
Min. Typ. Max.
Units
Conditions
MOSFET symbol
140
D
S
I
S
Continuous Source Current
–––
–––
(Body Diode)
Pulsed Source Current
A
showing the
integral reverse
G
I
SM
–––
–––
560
(Body Diode)
p-n junction diode.
V
SD
t
rr
Diode Forward Voltage
–––
–––
–––
–––
39
1.0
58
55
V
T =
25°C, I
= 12A, V
= 0V
J S GS
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
ns T
= 25°C, I
= 12A, V
DD
= 15V
J F
Q
rr
t
on
di/dt = 100A/µs
37
nC
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
IRLR/U7833PbF
1000
100
10
1000
100
10
VGS
10V
VGS
10V
TOP
TOP
5.0V
4.5V
4.0V
3.5V
3.0V
2.8V
5.0V
4.5V
4.0V
3.5V
3.0V
2.8V
2.7V
BOTTOM
2.7V
BOTTOM
2.7V
2.7V
60µs PULSE WIDTH
Tj = 175°C
≤
60µs PULSE WIDTH
Tj = 25°C
≤
1
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
2.0
1.5
1.0
0.5
I
= 30A
D
V
= 10V
GS
100
10
T
= 175°C
J
T
= 25°C
J
V
= 25V
DS
≤
60µs PULSE WIDTH
1.0
1
2
3
4
5
-60 -40 -20
T
0
20 40 60 80
100 120 140 160 180
, Junction Temperature (°C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
vs. Temperature
3
IRLR/U7833PbF
6.0
5.0
4.0
3.0
2.0
1.0
0.0
100000
V
C
= 0V,
f = 1 MHZ
GS
I =
12A
D
= C
+ C
, C
SHORTED
iss
gs gd
ds
C
= C
V
V
= 24V
= 15V
rss
gd
DS
DS
C
= C
+ C
ds gd
oss
10000
1000
100
C
C
iss
oss
C
rss
0
10
20
30
40
50
1
10
, Drain-to-Source Voltage (V)
100
Q
Total Gate Charge (nC)
V
G
DS
Fig 6.
Typical Gate Charge vs.
Fig 5.
Typical Capacitance vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000.00
100.00
10.00
1.00
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
100µsec
1msec
T
= 25°C
J
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
10msec
100
GS
0.10
1
0.0
0.5
1.0
1.5
2.0
2.5
1
10
1000
V
, Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
4
IRLR/U7833PbF
2.5
2.0
1.5
1.0
0.5
0.0
150
125
100
75
LIMITED BY PACKAGE
I
= 250µA
D
50
25
0
25
50
75
100
125
150
175
-75 -50 -25
0
25 50 75
100 125 150 175
T
C
, Case Temperature (°C)
T
, Temperature ( °C )
J
Fig 9.
Maximum Drain Current vs.
Fig 10.
Threshold Voltage vs. Temperature
Case Temperature
10
1
D = 0.50
0.20
P
DM
0.10
0.05
0.1
t
1
SINGLE PULSE
0.02
0.01
t
2
(THERMAL RESPONSE)
Notes:
1. Duty factor D =
t
/ t
1
2
2. Peak T
= P
x
Z
+ T
J
DM
thJC
C
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t ,
Rectangular Pulse Duration (sec)
1
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
IRLR/U7833PbF
15V
15000
12500
10000
7500
5000
2500
0
I
D
TOP
8.2A
14A
DRIVER
+
L
V
DS
BOTTOM 20A
D.U.T
AS
R
G
V
DD
–
I
A
2
V
G
S
Ω
0.01
t
p
Fig 12a.
Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
Starting T
, Junction Temperature (°C)
J
Fig 12c.
Maximum Avalanche Energy
Vs. Drain Current
I
AS
R
D
V
DS
Fig 12b.
Unclamped Inductive Waveforms
V
GS
D.U.T.
R
G
+
V
DD
–
Current Regulator
Same Type as D.U.
T
.
V
GS
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
50K
Ω
.2
µ
F
12V
Fig 14a.
Switching Time Test Circuit
.3
µ
F
+
V
DS
V
DS
D.U.
T
.
–
90%
V
GS
3mA
10%
V
I
I
GS
G
D
Current Sampling Resistors
t
t
r
t
t
f
d(on)
d(off)
Fig 13.
Gate Charge Test Circuit
Fig 14b.
Switching Time Waveforms
6
IRLR/U7833PbF
Driver Gate Drive
P
.
W.
Period
D.U.T
Period
D =
P.W.
+
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Curent
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 15.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1
Qgs2
Qgd
Qgodr
Fig 16.
Gate Charge Waveform
7
IRLR/U7833PbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Synchronous FET
Control FET
The power loss equation for Q2 is approximated
by;
Special attention has been given to the power losses
in the switching elements of the circuit – Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the R
ds(on)
of the
MOSFE
T
,
b
ut these conduction losses are only about
one half of the total losses.
P
=
P
+
P
+
P
*
loss
conduction
drive
output
P
=
I
rms
2
×
R
ds(on)
loss
( )
Power losses in the control switch Q1 are given
by;
+
Q
×
V
×
f
(
)
g
g
⎛
⎜
Q
oss
⎞
⎠
P
loss
= P
conduction
+ P
switching
+ P
drive
+ P
output
+
×
V
×
f
+
Q
×
V
×
f
(
)
in
rr
in
⎝
2
This can be expanded and approximated by;
*dissipated primarily in Q1.
P
=
I
2
×
R
ds
(
on )
(
)
loss
rms
For the synchronous MOSFET Q2, R
ds(on)
is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly,
the output charge Q
oss
and re-
verse recovery charge Q
rr
both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFE
T
s
’ susceptibility to Cdv/dt turn on.
⎛
⎛
Q
gd
i
g
⎞
Q
g
s
2
i
g
⎞
⎟
⎜
⎟
⎜
+
I
×
×
V
×
f
+
I
×
×
V
×
f
in
in
⎝
⎠
⎝
⎠
+
Q
×
V
×
f
(
)
g
g
⎛
Q
oss
⎞
⎠
+
×
V
×
f
in
⎝
2
This simplified loss equation includes the terms Q
gs2
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and V
in
. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of
Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Q
gd
/Q
gs1
must be minimized to reduce the
potential for Cdv/dt turn on.
and Q
oss
which are new to Power MOSFE
T
d
ata sheets.
Q
gs2
is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Q
gs1
and Q
gs2
, can be seen from
Fig 16.
Q
gs2
indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached
and the time the drain cur-
rent rises to I
dmax
at which time the drain voltage be-
gins to change. Minimizing Q
gs2
is a critical factor in
reducing switching losses in Q1.
Q
oss
is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Q
oss
is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances C
ds
and C
dg
when multiplied by
the power supply input buss voltage.
Figure A:
Q
oss
Characteristic
8
IRLR/U7833PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
9
IRLR/U7833PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
OR
10
IRLR/U7833PbF
D-Pak (TO-252AA)
T
a
pe & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRL
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
FEED DIRECTION
NOTES :
1. CONTROLLING
DIMENSION : MILLIMETER.
2. ALL
DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE
CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
Calculated continuous current based on maximum allowable
Repetitive rating;
pulse width limited by
max. junction temperature.
junction temperature. Package limitation current is 30A.
Starting T
J
= 25°C, L = 2.6mH, R
G
= 25
Ω
,
I
AS
= 20A.
Pulse width
≤
400µs; duty cycle
≤
2%.
ꢀ
When mounted on 1″ square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to
application note #AN-994.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
11
