Infineon-Technologies-IRLS3034TRL7PP
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PD – 97362
IRLS3034-7PPbF
HEXFET
®
Power MOSFET
Applications
l
DC Motor Drive
D
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
V
DSS
R
DS(on)
typ.
40V
1.0m
1.4m
380A
Ω
Ω
c
max.
G
I
D
I
D
(Silicon Limited)
Benefits
l
Optimized for Logic Level Drive
l
Very Low R
DS(ON)
at 4.5V V
GS
l
Superior R*Q at 4.5V V
GS
l
Improved Gate,
Avalanche and Dynamic
dV/dt
Ruggedness
240A
S
(Package Limited)
D
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
S
S
S
S
S
G
D
2
Pak 7 Pin
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
D
@ T
C
= 25°C
I
DM
Parameter
Max.
380
c
270
c
240
Units
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Wire Bond Limited)
Pulsed Drain Current
d
A
1540
P
D
@T
C
= 25°C
380
W
Maximum Power Dissipation
2.5
Linear Derating Factor
W/°C
V
V
GS
± 20
Gate-to-Source Voltage
1.3
Peak Diode Recovery
f
dv/dt
T
J
V/ns
-55 to
+ 175
Operating Junction and
T
STG
Storage Temperature Range
°C
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
Avalanche Characteristics
Single Pulse Avalanche Energy
e
E
AS (Thermally limited)
250
mJ
A
Avalanche Current
ꢀd
I
AR
See Fig. 14, 15, 22a, 22b
Repetitive Avalanche Energy
d
E
AR
mJ
Thermal Resistance
Symbol
Parameter
Junction-to-Case
kl
Junction-to-Ambient
j
Typ.
–––
Max.
0.40
40
Units
°C/W
R
θ
JC
R
θ
JA
–––
1
1/12/09
IRLS3034-7PPbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
∆
V
(BR)DSS
/
∆
T
J
Parameter
Min. Typ. Max.
Units
40 –––
–––
––– 0.035 –––
V/°C Reference
to 25°C, I
D
= 5mA
d
Conditions
V
GS
= 0V, I
D
= 250µA
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
V
R
DS(on)
–––
1.0
1.2
–––
1.4
1.7
2.5
20
V
GS
= 10V, I
D
= 200A
g
m
Ω
V
GS
= 4.5V, I
D
= 180A
g
V
GS(th)
I
DSS
Gate Threshold Voltage
1.0
V
V
DS
= V
GS
, I
D
= 250µA
Drain-to-Source Leakage Current
––– –––
µA V
DS
= 40V, V
GS
= 0V
––– ––– 250
––– ––– 100
––– –––
-100
V
DS
= 40V, V
GS
= 0V, T
J
= 125°C
I
GSS
R
G
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
nA
V
GS
= 20V
V
GS
= -20V
–––
1.9
–––
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Q
g
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max.
Units
Conditions
V
DS
= 10V, I
D
= 220A
370 ––– –––
S
––– 120 180
nC I
D
= 170A
V
DS
=20V
Q
gs
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Total Gate Charge Sync. (Q
g
– Q
gd
)
Turn-On Delay Time
–––
–––
–––
–––
32
71
49
71
–––
–––
–––
–––
Q
gd
V
GS
= 4.5V
g
Q
sync
I
D
= 170A, V
DS
=0V, V
GS
= 4.5V
t
d(on)
ns V
DD
= 26V
t
r
Rise Time
––– 590 –––
––– 94 –––
I
D
= 220A
t
d(off)
Turn-Off Delay Time
R
G
= 2.7
Ω
V
GS
= 4.5V
g
t
f
Fall Time
––– 200 –––
––– 10990 –––
––– 2030 –––
––– 1100 –––
––– 2520 –––
––– 3060 –––
C
iss
Input Capacitance
pF V
GS
= 0V
C
oss
Output Capacitance
V
DS
= 40V
C
rss
Reverse Transfer Capacitance
ƒ = 1.0MHz,
See Fig. 5
V
GS
= 0V, V
DS
= 0V to 32V
i
, See Fig. 11
V
GS
= 0V, V
DS
= 0V to 32V
h
C
oss
eff. (ER)
C
oss
eff. (TR)
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
h
Diode Characteristics
Symbol
Parameter
Min. Typ. Max.
Units
Conditions
D
I
S
Continuous Source Current
––– –––
A
MOSFET symbol
380
c
(Body Diode)
Pulsed Source Current
(Body Diode)
ꢀ
d
showing the
integral reverse
G
I
SM
––– –––
1540
A
S
p-n junction diode.
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
––– –––
1.3
–––
–––
V
T
J
= 25°C, I
S
= 200A, V
GS
= 0V
g
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
V
R
= 34V,
–––
–––
46
49
ns
I
F
= 220A
di/dt = 100A/µs
g
Q
rr
Reverse Recovery Charge
––– 100 –––
––– 110 –––
nC
A
I
RRM
t
on
Reverse Recovery Current
Forward Turn-On Time
–––
3.7
–––
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
I
SD
≤
220A, di/dt
≤
1240A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
ꢀ
Pulse width
≤
400µs; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
temperature. Bond wire current limit is 240A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements.
(Refer to AN-1140)
Repetitive rating;
pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.010mH
R
G
= 25
Ω
, I
AS
= 220A, V
GS
=10V. Part not recommended for use
above this value .
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
.
When mounted on 1″ square PCB (FR-4 or G-10 Material).
For recom
mended footprint and soldering techniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C.
R
θ
JC
value shown is at time zero.
2
IRFLS3034-7PPbF
10000
1000
100
100000
10000
1000
100
VGS
10V
VGS
10V
60µs PULSE WIDTH
Tj = 25°C
≤
60µs PULSE WIDTH
Tj = 175°C
≤
TOP
TOP
5.0V
4.5V
4.0V
3.5V
3.0V
2.8V
2.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.8V
2.5V
BOTTOM
BOTTOM
10
2.5V
2.5V
10
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
100
10
2.0
1.5
1.0
0.5
I
= 200A
= 10V
D
V
GS
T
= 175°C
J
T
= 25°C
J
1
V
= 25V
DS
≤
60µs PULSE WIDTH
0.1
1
2
3
4
5
-60 -40 -20
T
0
20 40 60 80
100120140160180
, Junction Temperature (°C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4.
Normalized On-Resistance vs. Temperature
Fig 3.
Typical Transfer Characteristics
100000
10000
1000
5.0
V
= 0V,
= C
f = 1 MHZ
GS
I =
170A
D
V
V
= 32V
= 20V
C
C
C
+ C
, C
SHORTED
DS
DS
iss
gs
gd
ds
= C
rss
oss
gd
4.0
3.0
2.0
1.0
0.0
= C
+ C
ds
gd
C
iss
C
oss
C
rss
0.1
1
10
100
0
25
50
75
100
125
150
V
, Drain-to-Source Voltage (V)
Q , Total
Gate Charge (nC)
DS
G
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
3
IRLS3034-7PPbF
1000
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
100µsec
1msec
100
10
T
= 25°C
Limited by package
J
10msec
DC
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
3.0
GS
1.0
1
0.0
0.5
V
1.0
1.5
2.0
2.5
3.5
0
1
10
100
, Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
400
50
Id = 5mA
Limited By Package
48
46
44
42
40
300
200
100
0
25
50
75
100
125
150
175
-60 -40 -20
0 20
40 60 80
100120140160180
, Temperature ( °C )
T
, Case Temperature (°C)
T
C
J
Fig 10.
Drain-to-Source Breakdown Voltage
Fig 9.
Maximum Drain Current vs. Case Temperature
2.5
1200
I
D
TOP
47A
94A
1000
800
600
400
200
0
2.0
1.5
1.0
0.5
0.0
BOTTOM 220A
-5
0
5
10 15 20 25 30 35 40 45
Drain-to-Source Voltage (V)
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
J
V
DS,
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy Vs. DrainCurrent
4
IRFLS3034-7PPbF
1
D = 0.50
0.1
0.20
0.10
0.05
R
1
R
1
R
2
R
2
R
3
R
3
R
4
R
4
Ri (°C/W)
τ
i (sec)
0.00741 0.000005
τ
τ
J
τ
J
C
τ
0.05041 0.000038
0.18384 0.001161
0.15864 0.008809
τ
τ
1
τ
1
Ci=
τ
i
/
Ri
τ
τ
2
τ
2
3
τ
3
4
τ
4
0.02
0.01
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
∆
pulsewidth, tav, assuming
Tj = 150°C and
0.01
Tstart =25°C (Single Pulse)
0.05
0.10
Allowed avalanche Current vs avalanche
∆Τ
pulsewidth, tav, assuming
Tstart = 150°C.
j = 25°C and
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
300
250
200
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆
T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche =
t
av
·f
TOP
BOTTOM 1.0%
Duty Cycle
= 220A
Single Pulse
I
D
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
0
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
25
50
75
100
125
150
175
I
av
= 2
D
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Starting T
, Junction Temperature (°C)
J
Fig 15.
Maximum Avalanche Energy vs. Temperature
5
IRLS3034-7PPbF
3.0
2.5
2.0
1.5
16
14
12
10
8
I =
89A
F
V
= 34V
R
T =
25°C
J
T =
125°C
J
I
I
I
= 250µA
= 1.0mA
= 1.0A
D
D
D
1.0
0.5
0.0
6
4
2
-75 -50 -25
0
25 50 75
100 125 150 175
0
100 200 300 400 500 600 700
di /dt
(A/µs)
T
, Temperature ( °C )
J
F
Fig. 17
– Typical Recovery Current vs. di
f
/dt
Fig 16.
Threshold Voltage vs. Temperature
16
900
800
700
600
500
400
300
200
100
0
I
= 134A
= 34V
I
= 89A
= 34V
F
F
14
12
10
8
V
V
R
R
T =
25°C
T =
25°C
J
J
T =
125°C
J
T =
125°C
J
6
4
2
0
100 200 300 400 500 600 700
di /dt
(A/µs)
0
100 200 300 400 500 600 700 800
di /dt
(A/µs)
F
F
Fig. 18
– Typical Recovery Current vs. di
f
/dt
Fig. 19
– Typical Stored Charge vs. di
f
/dt
800
I =
134A
F
700
V
= 34V
R
T =
25°C
J
600
500
400
300
200
100
0
T =
125°C
J
0
100 200 300 400 500 600 700 800
di /dt
(A/µs)
F
Fig. 20
– Typical Stored Charge vs. di
f
/dt
6
IRFLS3034-7PPbF
Driver Gate Drive
P.W.
P
.
W.
D =
Period
D.U.T
Period
+
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Current
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 21.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
V
2
GS
0.01
Ω
t
p
I
AS
Fig 22b.
Unclamped Inductive Waveforms
Fig 22a.
Unclamped Inductive Test Circuit
R
D
V
DS
V
DS
90%
V
GS
D.U.T.
R
G
+
V
DD
–
V
GS
10%
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a.
Switching Time Test Circuit
Fig 23b.
Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.
T
.
Vds
Vgs
50K
Ω
.2
µ
F
12V
.3
µ
F
+
V
DS
D.U.
T
.
–
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a.
Gate Charge Test Circuit
Fig 24b.
Gate Charge Waveform
7
IRLS3034-7PPbF
D
2
Pak – 7 Pin Package Outline
Dimensions are shown in millimeters (inches)
8
IRFLS3034-7PPbF
D
2
Pak – 7 Pin Part Marking Information
ꢀ14
D
2
Pak – 7 Pin
T
a
pe and Reel
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
9
