Infineon-Technologies-IRLS3036TRL7PP
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PD -97148A
IRLS3036-7PPbF
HEXFET
®
Power MOSFET
Applications
l
DC Motor Drive
D
V
DSS
60V
R
DS(on)
typ.
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
1.5m
1.9m
300A
:
:
c
max.
I
D (Silicon Limited)
I
D (Package Limited)
G
240A
S
Benefits
l
Optimized for Logic Level Drive
l
Very Low R
DS(ON)
at 4.5V V
GS
l
Superior R*Q at 4.5V V
GS
l
Improved Gate,
Avalanche and Dynamic
dV/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
D
S
S
S
S
S
G
D
2
Pak 7 Pin
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
D
@ T
C
= 25°C
I
DM
Parameter
Max.
300
c
210
Units
A
Continuous Drain Current, V
GS
@ 10V
(Silicon Limited)
Continuous Drain Current, V
GS
@ 10V
(Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Package Limited)
Pulsed Drain Current
d
240
1000
380
P
D
@T
C
= 25°C
Maximum Power Dissipation
W
2.5
Linear Derating Factor
W/°C
V
V
GS
± 16
8.1
Gate-to-Source Voltage
Peak Diode Recovery
f
dv/dt
T
J
V/ns
Operating Junction and
-55 to
+ 175
300
T
STG
°C
Storage Temperature Range
Soldering Temperature, for 10 seconds (1.6mm from case)
Avalanche Characteristics
Single Pulse Avalanche Energy
e
E
AS (Thermally limited)
300
mJ
A
Avalanche Current
d
I
AR
See Fig. 14, 15, 22a, 22b
Repetitive Avalanche Energy
d
E
AR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.40
40
Units
°C/W
R
θ
JC
Junction-to-Case
kl
R
θ
JA
Junction-to-Ambient (PCB Mount, steady state)
j
–––
1
10/28/10
IRLS3036-7PPbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max.
Units
60 –––
–––
––– 0.059 ––– V/°C
Reference to 25°C, I
D
= 5mA
d
Conditions
V
GS
= 0V, I
D
= 250
μ
A
V
Δ
V
(BR)DSS
/
Δ
T
J
Breakdown Voltage Temp. Coefficient
–––
–––
1.0
1.5
1.7
1.9
2.2
2.5
20
V
GS
= 10V, I
D
= 180A
g
R
DS(on)
Static Drain-to-Source On-Resistance
m
Ω
V
V
GS
= 4.5V, I
D
= 150A
g
DS
= V
GS
, I
D
= 250
μ
A
V
GS(th)
I
DSS
Gate Threshold Voltage
–––
V
Drain-to-Source Leakage Current
––– –––
V
DS
= 60V, V
GS
= 0V
μ
A
––– ––– 250
––– ––– 100
––– ––– -100
V
DS
= 60V, V
GS
= 0V, T
J
= 125°C
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
V
GS
= 16V
nA
V
GS
= -16V
R
G(int)
–––
1.9
–––
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Min. Typ. Max.
Units
Conditions
V
DS
= 10V, I
D
= 180A
390 ––– –––
S
Q
g
Total Gate Charge
––– 110 160
I
D
= 180A
Q
gs
Q
gd
Q
sync
t
d(on)
t
r
Gate-to-Source Charge
–––
–––
–––
–––
33
53
57
81
–––
–––
–––
–––
V
DS
= 30V
nC
Gate-to-Drain (“Miller”) Charge
Total Gate Charge Sync. (Q
g
– Q
gd
)
Turn-On Delay Time
V
GS
= 4.5V
g
I
D
= 180A, V
DS
=0V, V
GS
= 4.5V
V
DD
= 39V
Rise Time
––– 540 –––
––– 89 –––
I
D
= 180A
R
G
= 2.1
Ω
V
GS
= 4.5V
g
V
GS
= 0V
ns
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
––– 170 –––
––– 11270 –––
––– 1025 –––
––– 520 –––
––– 1460 –––
––– 1630 –––
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
V
DS
= 50V
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
iꢀ
Effective Output Capacitance (Time Related)
h
pF ƒ
= 1.0MHz
V
GS
= 0V, V
DS
= 0V to 48V
i
C
oss
eff. (ER)
C
oss
eff. (TR)
V
GS
= 0V, V
DS
= 0V to 48V
h
Diode Characteristics
Symbol
Parameter
Continuous Source Current
Min. Typ. Max.
Units
Conditions
MOSFET symbol
D
S
I
S
––– –––
300
(Body Diode)
Pulsed Source Current
showing the
A
––– –––
G
I
SM
integral reverse
1000
(Body Diode)
ꢀ
e
p-n junction diode.
V
SD
t
rr
Diode Forward Voltage
––– –––
1.3
–––
–––
V
T
J
= 25°C, I
S
= 180A, V
GS
= 0V
g
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
V
R
= 51V,
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
57
60
ns
I
F
= 180A
di/dt = 100A/
μ
s
g
Q
rr
––– 140 –––
––– 160 –––
nC
A
I
RRM
t
on
Reverse Recovery Current
Forward Turn-On Time
–––
4.6
–––
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
ꢁ
Pulse width
≤
400
μ
s; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time as
Calculated continuous current based on maximum allowable junction
temperature Bond wire current limit is 240A. Note that current
limitation arising from heating of the device leds may occur with
some lead mounting arrangements.
Repetitive rating;
pulse width limited by max. junction
temperature.
C
oss
while V
DS
is rising from 0 to 80% V
DSS
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
When mounted on 1″ square PCB (FR-4 or G-10 Material). For
recommended footprint
and soldering techniquea refer to applocation
note # AN-
994 echniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C.
.
.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.018mH
R
G
= 25
Ω
, I
AS
= 180A, V
GS
=10V. Part not recommended for use
above this value .
R
θ
JC
value shown is at time zero.
I
SD
≤
180A, di/dt
≤
1070A/
μ
s, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
2
IRLS3036-7PPbF
1000
100
10
1000
100
10
VGS
15V
10V
4.5V
4.0V
3.5V
3.3V
3.0V
2.7V
VGS
15V
10V
4.5V
4.0V
3.5V
3.3V
3.0V
2.7V
TOP
TOP
BOTTOM
BOTTOM
1
2.7V
2.7V
≤
60
μ
s PULSE WIDTH
≤
60
μ
s PULSE WIDTH
Tj = 25°C
Tj = 175°C
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
2.5
2.0
1.5
1.0
0.5
1000
100
10
I
= 180A
= 10V
D
V
GS
T
= 175°C
J
T
= 25°C
J
V
= 25V
DS
≤
60
μ
s PULSE WIDTH
1
2.0
3.0
4.0
5.0
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
V
, Gate-to-Source Voltage (V)
GS
T
, Junction Temperature (°C)
J
Fig 4.
Normalized On-Resistance vs. Temperature
Fig 3.
Typical Transfer Characteristics
5
20000
15000
10000
5000
0
V
C
= 0V,
f = 100 kHz
GS
V
V
= 48V
= 30V
I =
180A
D
DS
DS
= C
+ C
, C
SHORTED
iss
gs
gd ds
C
= C
rss
gd
4
3
2
1
0
C
= C
+ C
oss
ds
gd
Ciss
Coss
Crss
0
20
Q
40
60
80
100 120 140
1
10
100
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
3
IRLS3036-7PPbF
1000
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
100
10
1
100
μ
sec
T
= 25°C
J
1msec
LIMITED BY PACKAGE
10msec
DC
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
1.4
GS
0.1
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.6
0.1
1
10
100
V
, Drain-toSource Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
300
80
70
60
50
LIMITED BY PACKAGE
I
= 5mA
D
250
200
150
100
50
0
25
50
75
100
125
150
175
-60 -40 -20
0
20 40 60 80
100 120 140 160 180
T
, Case Temperature (°C)
C
T
, Junction Temperature (°C)
J
Fig 9.
Maximum Drain Current vs.
Fig 10.
Drain-to-Source Breakdown Voltage
Case Temperature
4.0
3.0
2.0
1.0
0.0
1200
I
D
TOP
22A
37A
180A
1000
800
600
400
200
0
BOTTOM
0
10
20
30
40
50
60
70
25
50
75
100
125
150
175
V
Drain-to-Source Voltage (V)
Starting T
, Junction Temperature (°C)
J
DS,
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy Vs. DrainCurrent
4
IRLS3036-7PPbF
1
0.1
D = 0.50
0.20
0.10
R
1
R
1
R
2
R
2
R
3
R
3
τι
(sec)
Ri (°C/W)
0.05
0.02
0.01
τ
J
τ
J
τ
τ
C
τ
0.103731 0.000184
0.196542 0.001587
0.098271 0.006721
0.01
τ
1
τ
1
τ
2
τ
2
3
τ
3
Ci=
τ
i
/
Ri
Ci=
τ
i
/
Ri
0.001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
Δ
Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
ΔΤ
j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
300
250
200
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
Δ
T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche =
t
av
·f
TOP
BOTTOM 1%
Duty Cycle
= 180A
Single Pulse
I
D
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
0
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
25
50
75
100
125
150
175
I
av
= 2
D
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Starting T
, Junction Temperature (°C)
J
Fig 15.
Maximum Avalanche Energy vs. Temperature
5
IRLS3036-7PPbF
3.0
24
18
12
6
I
I
I
= 1.0A
D
D
D
= 1.0mA
= 250
μ
A
2.5
2.0
1.5
1.0
I
= 120A
= 51V
F
V
T
R
= 125°C
= 25°C
J
T
J
0
-75 -50 -25
0
J
25 50 75
100 125 150 175
, Temperature ( °C )
100 200 300 400 500 600 700 800 900
T
di /
dt – (A /
μ
s)
f
Fig. 17
– Typical Recovery Current vs. di
f
/dt
Fig 16.
Threshold Voltage Vs. Temperature
1000
24
800
600
400
200
0
18
12
I
= 120A
= 51V
I
= 180A
= 51V
F
F
6
0
V
V
T
R
R
T
= 125°C
= 125°C
= 25°C
J
J
T
= 25°C
T
J
J
100 200 300 400 500 600 700 800 900
100 200 300 400 500 600 700 800 900
di /
dt – (A /
μ
s)
di /
dt – (A /
μ
s)
f
f
Fig. 18
– Typical Recovery Current vs. di
f
/dt
Fig. 19
– Typical Stored Charge vs. di
f
/dt
1000
I
= 180A
= 51V
F
V
T
R
= 125°C
800
600
400
200
0
J
T
= 25°C
J
100 200 300 400 500 600 700 800 900
di /
dt – (A /
μ
s)
f
Fig. 20
– Typical Stored Charge vs. di
f
/dt
6
IRLS3036-7PPbF
Driver Gate Drive
P.W.
P
.
W.
Period
Period
D =
D.U.T
+
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Current
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 21.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
V
2
GS
0.01
Ω
t
p
I
AS
Fig 22b.
Unclamped Inductive Waveforms
Fig 22a.
Unclamped Inductive Test Circuit
R
D
V
DS
V
DS
90%
V
GS
D.U.T.
R
G
+
V
DD
–
V
GS
10%
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a.
Switching Time Test Circuit
Fig 23b.
Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.
T
.
Vds
Vgs
50K
Ω
.2
μ
F
12V
.3
μ
F
+
V
DS
D.U.
T
.
–
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a.
Gate Charge Test Circuit
Fig 24b.
Gate Charge Waveform
7
IRLS3036-7PPbF
D
2
Pak – 7 Pin Package Outline
Dimensions are shown in millimeters (inches)
8
IRLS3036-7PPbF
D
2
Pak – 7 Pin Part Marking Information
ꢀ
25
D
2
Pak – 7 Pin
T
a
pe and Reel
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
9
