Infineon-Technologies-IRLS4030TRL7PP
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PD –
97371
IRLS4030-7PPbF
HEXFET
®
Power MOSFET
Applications
l
DC Motor Drive
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
D
V
DSS
100V
R
DS(on)
typ.
3.2m
3.9m
Ω
Ω
G
max.
I
D
190A
S
Benefits
l
Optimized for Logic Level Drive
l
Very Low R
DS(ON)
at 4.5V V
GS
l
Superior R*Q at 4.5V V
GS
l
Improved Gate,
Avalanche and Dynamic
dV/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
D
S
S
S
S
S
G
D
2
Pak 7 Pin
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
Parameter
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
c
Max.
190
130
750
370
2.5
Units
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
A
P
D
@T
C
= 25°C
W
Maximum Power Dissipation
Linear Derating Factor
W/°C
V
V
GS
± 16
13
Gate-to-Source Voltage
Peak Diode Recovery
e
dv/dt
T
J
V/ns
°C
-55 to
+ 175
Operating Junction and
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
300
10lb
x
in (1.1N
x
m)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy
d
E
AS (Thermally limited)
320
mJ
A
Avalanche Current
c
I
AR
See Fig. 14, 15, 22a, 22b
Repetitive Avalanche Energy
f
E
AR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.40
40
Units
°C/W
R
θ
JC
Junction-to-Case
jk
R
θ
JA
–––
Junction-to-Ambient (PCB Mount)
ij
1
02/12/09
IRLS4030-7PPbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
Parameter
Min. Typ. Max.
Units
100 ––– –––
––– 0.10 ––– V/°C
Reference to 25°C, I
D
= 5mA
c
Conditions
V
GS
= 0V, I
D
= 250µA
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
V
∆
V
(BR)DSS
/
∆
T
J
R
DS(on)
–––
–––
1.0
3.2
3.3
–––
3.9
4.1
2.5
20
V
GS
= 10V, I
D
= 110A
f
V
GS
= 4.5V, I
D
= 94A
f
V
DS
= V
GS
, I
D
= 250µA
m
Ω
V
GS(th)
I
DSS
Gate Threshold Voltage
V
Drain-to-Source Leakage Current
––– –––
µA
V
DS
= 100V, V
GS
= 0V
––– ––– 250
––– ––– 100
––– –––
-100
V
DS
= 100V, V
GS
= 0V, T
J
= 125°C
I
GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
nA V
GS
= 16V
GS
= -16V
V
R
G(int)
–––
2.0
–––
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Q
g
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max.
Units
250 ––– –––
Conditions
V
DS
= 25V, I
D
= 110A
S
–––
–––
–––
–––
–––
93
27
43
50
53
140
–––
–––
–––
–––
nC I
D
= 110A
V
DS
= 50V
Q
gs
Gate-to-Source Charge
Gate-to-Drain (“Miller”) Charge
Total Gate Charge Sync. (Q
g
– Q
gd
)
Turn-On Delay Time
Q
gd
V
GS
= 4.5V
f
Q
sync
I
D
= 110A, V
DS
=0V, V
GS
= 4.5V
t
d(on)
ns
V
DD
= 65V
t
r
Rise Time
––– 160 –––
––– 110 –––
I
D
= 110A
t
d(off)
Turn-Off Delay Time
R
G
= 2.7
Ω
V
GS
= 4.5V
f
t
f
Fall Time
–––
87
–––
C
iss
Input Capacitance
––– 11490 –––
––– 680 –––
––– 300 –––
––– 760 –––
––– 1170 –––
V
GS
= 0V
C
oss
Output Capacitance
V
DS
= 50V
C
rss
Reverse Transfer Capacitance
pF ƒ
= 1.0MHz
C
oss
eff. (ER)
C
oss
eff. (TR)
V
GS
= 0V, V
DS
= 0V to 80V
h
Effective Output Capacitance (Energy Related)
h
V
GS
= 0V, V
DS
= 0V to 80V
g
Effective Output Capacitance (Time Related)
g
Diode Characteristics
Symbol
Parameter
Min. Typ. Max.
Units
Conditions
D
S
I
S
Continuous Source Current
––– –––
A
MOSFET symbol
190
(Body Diode)
Pulsed Source Current
(Body Diode)
ꢁc
showing the
integral reverse
G
I
SM
––– ––– 750
p-n junction diode.
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
––– –––
1.3
–––
–––
–––
V
T
J
= 25°C, I
S
= 110A, V
GS
= 0V
f
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
V
R
= 85V,
–––
–––
–––
53
63
99
ns
I
F
= 110A
di/dt = 100A/µs
f
Q
rr
Reverse Recovery Charge
nC
A
––– 155 –––
––– 3.3 –––
I
RRM
t
on
Reverse Recovery Current
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating;
pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.05mH
R
G
= 25
Ω
, I
AS
= 110A, V
GS
=10V. Part not recommended for use
above this value .
I
SD
≤
110A, di/dt
≤
1520A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
Pulse width
≤
400µs; duty cycle
≤
2%.
ꢀ
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
.
When mounted on 1″ square PCB (FR-4 or G-10 Material).
For recom
mended footprint and soldering techniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C.
R
θ
JC
value shown is at time zero.
2
IRLS4030-7PPbF
1000
100
10
1000
100
10
VGS
10V
VGS
10V
TOP
TOP
5.0V
4.5V
4.0V
3.5V
3.0V
2.7V
2.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.7V
2.5V
BOTTOM
BOTTOM
2.5V
2.5V
60µs PULSE WIDTH
≤
60µs PULSE WIDTH
≤
Tj = 25°C
Tj = 175°C
1
0.1
1
10
100
1000
0.1
1
10
100
1000
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
100
10
3.0
2.5
2.0
1.5
1.0
0.5
I
= 110A
= 10V
D
V
GS
T
= 175°C
J
T
= 25°C
J
1
V
= 25V
DS
≤
60µs PULSE WIDTH
0.1
1
2
3
4
5
-60 -40 -20
0 20
40 60 80
100120140160180
, Junction Temperature (°C)
T
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4.
Normalized On-Resistance vs. Temperature
Fig 3.
Typical Transfer Characteristics
100000
10000
1000
5.0
V
= 0V,
= C
f = 1 MHZ
GS
I =
110A
D
C
C
C
+ C
, C
SHORTED
V
V
= 80V
= 50V
iss
gs
gd
ds
DS
DS
= C
rss
oss
gd
4.0
3.0
2.0
1.0
0.0
= C
+ C
ds
gd
C
iss
C
oss
C
rss
100
0
20
40
60
80
100
120
1
10
100
1000
Q ,
Total Gate Charge (nC)
V
, Drain-to-Source Voltage (V)
G
DS
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
3
IRLS4030-7PPbF
10000
1000
100
10
1000
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
100
10
1
100µsec
1msec
T
= 25°C
J
10msec
DC
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
0.1
0.1
1
10
100
1000
0.0
0.5
1.0
1.5
2.0
V
, Drain-to-Source Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 8.
Maximum Safe Operating Area
Fig 7.
Typical Source-Drain Diode
Forward Voltage
200
180
160
140
120
100
80
125
120
115
110
105
100
95
Id = 5mA
60
40
20
0
25
50
75
100
125
150
175
-60 -40 -20
0 20
40 60 80
100120140160180
T
, Case Temperature (°C)
T ,
Temperature ( °C )
C
J
Fig 9.
Maximum Drain Current vs.
Fig 10.
Drain-to-Source Breakdown Voltage
Case Temperature
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1400
I
D
1200
1000
800
600
400
200
0
TOP
12A
16A
BOTTOM 110A
-20
0
20
40
60
80
100 120
25
50
75
100
125
150
175
Starting T
, Junction Temperature (°C)
J
V
Drain-to-Source Voltage (V)
DS,
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy vs. DrainCurrent
4
IRLS4030-7PPbF
1
0.1
D = 0.50
0.20
0.10
0.05
R
1
R
1
R
2
R
2
Ri (°C/W)
τ
i (sec)
0.02
0.01
0.01
τ
τ
J
τ
J
C
τ
C
0.176
0.000343
τ
τ
1
τ
1
2
τ
2
0.227
0.006073
C
i
=
τ
i
/
R
i
C
i
=
τ
i
/
Ri
0.001
0.0001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
∆
pulsewidth, tav, assuming
Tj = 150°C and
0.01
Tstart =25°C (Single Pulse)
0.05
0.10
1
Allowed avalanche Current vs avalanche
∆Τ
pulsewidth, tav, assuming
Tstart = 150°C.
j = 25°C and
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
400
300
200
100
0
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆
T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche =
t
av
·f
TOP
BOTTOM 1.0%
Duty Cycle
= 110A
Single Pulse
I
D
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
D
T/ Z
thJC
25
50
75
100
125
150
175
I
av
= 2
D
T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Starting T
, Junction Temperature (°C)
J
Fig 15.
Maximum Avalanche Energy vs. Temperature
5
IRLS4030-7PPbF
30
25
20
15
10
5
3.0
2.5
2.0
1.5
I =
75A
F
V
= 85V
R
T =
25°C
J
T =
125°C
J
I
I
I
= 250µA
= 1.0mA
= 1.0A
D
D
D
1.0
0.5
0.0
0
0
200
400
600
800
1000
-75 -50 -25
0
25 50 75
100 125 150 175
di /dt
(A/µs)
T
, Temperature ( °C )
F
J
Fig. 17
– Typical Recovery Current vs. di
f
/dt
Fig 16.
Threshold Voltage vs. Temperature
30
1400
I =
110A
I =
75A
F
F
V
= 85V
1200
1000
800
600
400
200
0
V
= 85V
R
25
20
15
10
5
R
T =
25°C
T =
25°C
J
J
T =
125°C
J
T =
125°C
J
0
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt
(A/µs)
di /dt
(A/µs)
F
F
Fig. 18
– Typical Recovery Current vs. di
f
/dt
Fig. 19
– Typical Stored Charge vs. di
f
/dt
1600
I =
110A
F
1400
V
= 85V
R
T =
25°C
J
1200
1000
800
600
400
200
0
T =
125°C
J
0
200
400
600
800
1000
di /dt
(A/µs)
F
Fig. 20
– Typical Stored Charge vs. di
f
/dt
6
IRLS4030-7PPbF
Driver Gate Drive
P.W.
P
.
W.
Period
Period
D =
D.U.T
+
*
=10V
V
GS
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
–
D.U.
T
. I
W
aveform
SD
+
–
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
–
+
D.U.
T
. V
W
aveform
DS
Diode Recovery
dv/dt
V
DD
V
DD
Re-Applied
Voltage
•
dv/dt controlled by R
G
R
G
+
–
Body Diode
Forward Drop
•
Driver same type as D.U.T.
•
I
SD
controlled by Duty Factor “D”
•
D.U.T. – Device Under Test
Inductor Current
I
SD
Ripple
≤
5%
*
V
GS
= 5V for Logic Level Devices
Fig 21.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
–
I
A
V
2
GS
0.01
Ω
t
p
I
AS
Fig 22b.
Unclamped Inductive Waveforms
Fig 22a.
Unclamped Inductive Test Circuit
R
D
V
DS
V
DS
90%
V
GS
D.U.T.
R
G
+
V
DD
–
V
GS
10%
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a.
Switching Time Test Circuit
Fig 23b.
Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.
T
.
Vds
Vgs
50K
Ω
.2
µ
F
12V
.3
µ
F
+
V
DS
D.U.
T
.
–
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a.
Gate Charge Test Circuit
Fig 24b.
Gate Charge Waveform
7
IRLS4030-7PPbF
D
2
Pak – 7 Pin Package Outline
Dimensions are shown in millimeters (inches)
8
IRLS4030-7PPbF
D
2
Pak – 7 Pin Part Marking Information
ꢀ14
D
2
Pak – 7 Pin
T
a
pe and Reel
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
9
