InventChip-IVST12050SA1L
| Part # | InventChip-IVST12050SA1L |
Download  | InventChip-IVST12050SA1L |
Aug. 2022
IVST12050SA1L
–
1200V 50m
Ω
SiC MODULE
Package
Features
⚫
⚫
⚫
⚫
⚫
High blocking voltage with low on-resistance
High speed switching with low capacitance
High operating junction temperature capability
Very fast and robust intrinsic body diode
Kelvin gate input easing driver circuit design
Applications
⚫
⚫
⚫
⚫
Solar inverters
UPS application
Part Number
Package
High voltage DC/DC converters
Switch mode power supplies
IVST12050SA1L
SOT 227
Absolute Maximum Ratings
(T
C
=25
°
C
unless otherwise specified)
Symbol
Parameter
Value
Unit
Test Conditions
Note
V
DS
Drain-Source voltage
Maximum DC voltage
1200
V
V
V
GS
=0V, I
D
=100
μ
A
Static (DC)
V
GSmax
(DC)
-5 to 22
<1% duty cycle, and pulse
width<200ns
V
GSmax
(Spike) Maximum
spike voltage
-10 to 25
V
V
V
GSon
V
GSoff
Recommended turn-on
voltage
20
±
0.5
Recommended turn-off
voltage
-3.5 to -2
V
64
45
A
A
V
GS
=20V, T
C
=25
°
C
V
GS
=20V, T
C
=100
°
C
I
D
Drain current (continuous)
Fig. 21
I
DM
P
TOT
T
stg
T
J
Drain current (pulsed)
160
A
Pulse width limited by SOA
Fig. 24
Total power dissipation
413
W
°
C
°
C
T
C
=25
°
C
Fig. 22
Storage temperature range
Operating junction temperature
-55 to 175
-55 to 175
Thermal Data
Symbol
Parameter
Value
Unit
Note
R
θ
(J-C)
Thermal Resistance from Junction to Case
0.363
°C
/W
Fig. 23
Rev0.5
Aug. 2022
Electrical Characteristics
(T
C
=25
°
C
unless otherwise specified)
Value
Symbol
Parameter
Unit
Test Conditions
Note
Min.
1.8
Typ.
5
Max.
100
Zero gate voltage drain
current
I
DSS
I
GSS
V
TH
μ
A
V
DS
=1200V, V
GS
=0V
Gate leakage current
±
100
nA
V
V
DS
=0V, V
GS
=-5~20V
V
GS
=V
DS
, I
D
=6mA
V
GS
=V
DS
, I
D
=6mA
@ T
C
=175
°
C
3.2
2.2
5
Gate threshold voltage
Fig. 8, 9
V
GS
=20V, I
D
=20A
@T
J
=25
°
C
50
80
65
m
Ω
m
Ω
Static drain-source on-
resistance
Fig. 4, 5, 6,
7
R
ON
V
GS
=20V, I
D
=20A
@T
J
=175
°
C
C
iss
Input capacitance
Output capacitance
Reverse transfer
2750
106
pF
pF
C
oss
Fig. 16
V
DS
=800V, V
GS
=0V,
f=1MH
Z
, V
AC
=25mV
C
rss
5.2
pF
capacitance
E
oss
Q
g
C
oss
stored energy
Total gate charge
Gate-source charge
Gate-drain charge
Gate input resistance
43
120
25
μ
J
nC
nC
nC
Ω
Fig. 17
Fig. 18
V
DS
=800V, I
D
=20A,
V
GS
=-5 to 20V
Q
gs
Q
gd
R
g
48
2.8
f=1MH
Z
E
ON
Turn-on switching energy
684.2
μ
J
μ
J
V
DS
=800V I
DS
=30A,
V
GS
=-3.5V~20V,
R
G(ext)
=3.3
Ω
,
E
OFF
t
d(on)
t
r
Turn-off switching energy
Turn-on delay time
Rise time
77.8
14.7
28.5
23.1
12.4
Fig. 19, 20
ns
L=270μH
t
d(off)
t
f
Turn-off delay time
Fall time
Rev0.5
Aug. 2022
Reverse Diode Characteristics
(T
C
=25
°
C
unless otherwise specified)
Value
Symbol
Parameter
Unit
Test Conditions
Note
Min.
Typ.
4.9
Max.
V
V
I
SD
=20A, V
GS
=0V
I
SD
=20A, V
GS
=0V,
T
J
=175
°
C
Fig. 10,
11, 12
V
SD
Diode forward voltage
4.4
V
GS
=-3.5V/+20V,
I
SD
=30A, V
R
=800V,
di/dt=2000A/us,
R
G(ext)
=16
Ω
,
t
rr
Reverse recovery time
54.6
233
ns
Q
rr
Reverse recovery charge
nC
I
RRM
Peak reverse recovery current
17.2
A
L=270
μ
H
Module Characteristics
Value
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
2.5
V
ISOL
Tstg
Isolation test voltage
Storage temperature
Terminal connection torque
Mounting torque
RMS, f=50Hz, t=1min
kV
℃
-40
1.1
1.1
150
1.5
Screw M4
Screw M4
N
·
m
N
·
m
g
M
G
1.5
Weight of module
27
Terminal to heatsink
Terminal to terminal
Terminal to heatsink
Terminal to terminal
10.61
10.37
6.7
mm
mm
mm
mm
Creepage distance
Clearance
4.05
Rev0.5
Aug. 2022
Typical Performance (curves)
Fig. 1 Output Curve @ T
J
=-55
°
C
Fig. 2 Output Curve @ T
J
=25
°
C
Fig. 3 Output Curve @ T
J
=175
°
C
Fig. 4 Ron vs. Temperature
Fig. 6 Ron vs. I
DS
@ Various Temperature
Fig. 5 Normalized Ron vs. Temperature
Rev0.5
Aug. 2022
Fig. 8 Transfer Curves @ Various Temperature
Fig. 7 Ron vs. Temperature @ Various V
GS
Fig. 9 Threshold Voltage vs. Temperature
Fig. 10 Body Diode Curves @ T
J
=-
55°C
Fig. 11 Body Diode Curves @ T
J
=25°C
Fig. 12 Body Diode Curves @ T
J
=17
5°C
Rev0.5
Aug. 2022
Fig. 13 3
rd
Quadrant Curves @ T
J
=-55
°C
Fig. 15 3
rd
Quadrant Curves @ T
J
=17
5°C
Fig. 17 Output Capacitor Stored Energy
Fig. 14 3
rd
Quadrant Curves @ T
J
=25°C
Fig. 16 Capacitance vs. V
DS
Fig. 18 Gate Charge Characteristics
Rev0.5
Aug. 2022
Fig. 19 Switching Energy vs. R
G(ext)
Fig. 20 Switching Times vs. R
G(ext)
Fig. 21 Continuous Drain Current vs. Case
Temperature
Fig. 22 Max. Power Dissipation Derating vs. Case
Temperature
Fig. 23 Thermal Impedance
Fig. 24 Safe Operating Area
Rev0.5
Aug. 2022
Notes
F
or further information please contact IVCT’
s Office.
C
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22 InventChip Technology Co., Ltd. All rights reserved.
The Information in this document is subject to change without notice.
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