IPS-FTB07N08N
| Part # | IPS-FTB07N08N |
Download  | IPS-FTB07N08N |
N-Channel MOSFET
Lead Free Package and Finish
Applications:
●
●
Adaptor
Charger
V
DSS
85V
R
DS(ON)
(Typ.)
I
D
●
SMPS
6m
Ω
120A
Features:
●
●
●
●
●
RoHS Compliant
Low ON Resistance
Low Gate Charge
Peak Current vs Pulse Width Curve
Inductive Switching Curves
Ordering Information
PART NUMBER
PACKAGE
BRAND
FTB07N08N TO-263
IPS
Absolute Maximum Ratings
T
C
=25
℃
unless otherwise specified
Symbol
Parameter
FTP07N08N
Units
V
V
DSS
Drain-to-Source Voltage
85
120
85
I
D
Continuous Drain Current
A
Continuous Drain Current T
C
=100
℃
Pulsed Drain Current (NOTE *1)
Power Dissipation
A
I
DM
P
D
480
208
1.8
A
W
Derating Factor above 25
℃
Gate-to-Source Voltage
W/
℃
V
V
GS
E
AS
T
L
±
20
650.25
300
Single Pulse Avalanche Energy(NOTE *2)
Maximum
T
e
mperature for Soldering
Operating Junction and Storage
T
e
mperature Range
mJ
℃
T
J
and T
STG
150
，
-55 to150
Thermal Resistance
Symbol
R
θ
JC
R
θ
JA
Parameter
Max.
0.55
65.2
Units
Test Conditions
Water cooled heatsink, P
D
adjusted for a
Junction-to-Case
℃
/W peak
junction temperature of +150
℃
.
Junction-to-Ambient
1 cubic foot chamber, free air.
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OFF Characteristics
T
C
=25
℃
unless otherwise specified
Symbol
BV
DSS
Parameter
Min. Typ. Max.
Units
Test Conditions
Drain-to-Source Breakdown Voltage
85
—
—
V
V
GS
=0V, I
D
=250
μ
A
V
DS
=85V, V
GS
=0V
T
J
=25
℃
—
—
1
I
DSS
Drain-to-Source Leakage Current
μ
A
V
DS
=68V, V
GS
=0V
T
J
=100
℃
—
—
100
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
—
—
—
—
+100
-100
V
GS
=+20V
I
GSS
nA
V
GS
= -20V
ON Characteristics
T
J
=25
℃
unless otherwise specified
Symbol
R
DS(ON)
V
GS(TH)
Parameter
Min. Typ.
Max.
7.5
4
Units
m
Ω
V
Test Conditions
V
GS
=10V, I
D
=60A
StaticDrain-to-Source On-Resistance
—
2
6.0
—
Gate Threshold Voltage
V
DS
=V
GS
,I
D
=250
μ
A
Pulse width
≤
300
μ
s; duty cycle
≤
2%
Dynamic Characteristics
Essentially independent of operating temperature
Symbol
Parameter
Min. Typ.
Max. Units
Test Conditions
C
iss
Input Capacitance
—
—
—
—
—
—
4572
494.4
253
—
V
GS
= 0V,V
DS
= 25V
f =1.0MHz
C
oss
C
rss
Q
g
Output Capacitance
—
—
—
—
—
pF
nC
Reverse Transfer Capacitance
T
o
tal Gate Charge
74.4
21.9
22.4
I
D
=60A,V
DD
=64V
V
GS
= 10V
Q
gs
Q
gd
Gate-to-Source Charge
Gate-to-Drain (
“
Miller
”
) Charge
Resistive Switching Characteristics
Essentially independent of operating temperature
Symbol
Parameter
Min. Typ.
Max. Units
Test Conditions
t
d(ON)
Turn-on Delay Time
—
—
—
—
35.7
65.6
67.2
21.87
—
t
rise
Rise Time
—
V
DD
=40V, I
D
=60A,
ns
—
V
GS
=10V R
G
=6
Ω
t
d(OFF)
t
fall
Turn-Off Delay Time
Fall Time
—
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Source-Drain Diode Characteristics
T
c
=25
℃
unless otherwise specified
Symbol
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max.
Units
Test Conditions
I
S
—
—
—
—
120
480
A
A
T
C
=25
℃
Maximum Pulsed Current
(Body Diode)
I
SM
V
SD
t
rr
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
—
—
—
—
1.2
—
V
I
SD
=60A, V
GS
=0V
I
S
= 20A
72
ns
nC
di/dt=100A/us
Q
rr
126
—
Pulse width
≤
300
μ
s; duty cycle
≤
2%
Notes:
*1. Repetitive rating; pulse width limited by maximum junction temperature.
*2. L=0.5mH, I
D
=51A, Start T
J
=25
℃
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Characteristics Curve
：
Figure
1
Maximum Forward Bias Safe Operating Area
Figure
2
Maximum Power Dissipation vs Case
T
emperature
Figure 3
Maximum Continuous Drain Current vs Case
T
emperature
Figure 4
Typical Output Characteristics
Figure
5
Drain-to-Source On Resistance vs Drain Current
Figure
6
Typical Transfer Characteristics
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Figure
8
Typical Body Diode Transfer Characteristics
Figure
7
Typical Gate Charge vs Gate to Source Voltage
Figure 9
Typical Capacitance vs Drain to Source Voltage
Figure10 Typical
Drian to Source on Resistance
vs Junction
T
e
mperature
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Figure11 Typical Theshold Voltage vs Junction
T
emperature
Figure12 Typical Breakdown Voltage vs Junction
T
emperature
Figure 13 Maximum
Effective Transient Thermal Impedance, Junction-to-Case
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Test Circuits and Waveforms
Figure 14. Gate Charge Test Circuit
Figure 15. Gate Charge Waveforms
Figure 16. Resistive Switching Test Circuit
Figure 17. Resistive Switching Waveforms
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Figure 18. Diode Reverse Recovery Test Circuit
Figure 19. Diode Reverse Recovery Waveform
Figure20.Unclamped Inductive Switching Test Circuit
Figure21.Unclamped Inductive Switching Waveform
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Disclaimers:
InPower Semiconductor Co., Ltd (IPS) reserves the right to make changes without notice in order to
improve reliabilit
y
,
f
unction or design and to discontinue any product or service without notice. Customers
should obtain the latest relevant information before orders and should verify that such information is
current and complete. All products are sold subject to IPS
’
s terms and conditions supplied at the time of
order acknowledgement.
InPower Semiconductor Co., Ltd warrants performance of its hardware products to the specifications at
the time of sale,
T
e
sting reliability and quality control are used to the extent IPS deems necessary to
support this warrantee. Except where agreed upon by contractual agreement, testing of all parameters of
each product is not necessarily performed.
InPower Semiconductor Co., Ltd does not assume any liability arising from the use of any product or
circuit designs described herein. Customers are responsible for their products and applications using
IPS
’
s components.
T
o
m
inimize risk, customers must provide adequate design and operating safeguards.
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under its patent rights, nor the rights of others. Reproduction of information in IPS
’
s data sheets or data
books is permissible only if reproduction is without modification or alteration. Reproduction of this
information with any alteration is an unfair and deceptive business practice. InPower Semiconductor Co.,
Ltd is not responsible or liable for such altered documentation.
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’
s products with statements different from or beyond the parameters stated by InPower
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associated IPS
’
s product or service and is unfair and deceptive business practice. InPower
Semiconductor Co., Ltd is not responsible or liable for any such statements.
Life Support Policy:
InPower Semiconductor Co., Ltd
’
s products are not authorized for use as critical components in life
support devices or systems without the expressed written approval of InPower Semiconductor Co., Ltd.
As used herein:
1. Life
support devices or systems are devices or systems which:
a. are
intended for surgical implant into the human bod
y
,
b. support
or sustain life,
c. whose
failure to perform when properly used in accordance with instructions for used
provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system, or to affect its safety
or effectiveness.
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2016 InPower Semiconductor Co., Ltd.
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