JSMSEMI-JSM66302
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JSM66302
High performance multi-protocol NFC frontend
1.
General description
JSM66302, the high performance multi-protocol NFC frontend.
The JSM66302 multi-protocol NFC frontend IC supports the following operating modes
•
•
•
Read/write mode supporting ISO/IEC 14443A/MIFARE
Read/write mode supporting ISO/IEC 14443B
Read/write mode supporting JIS X 6319-4 (comparable with FeliCa
e
Section 20.5) scheme)
•
•
•
•
Passive initiator mode according to ISO/IEC 18092
Read/write mode supporting ISO/IEC 15693
Read/write mode supporting ICODE EPC UID/ EPC OTP
Read/write mode supporting ISO/IEC 18000-3 mo
3/ EPC Class-1 HF
The JSM66302’s internal transmitter is able to drive a reader/writer antenna designed
to communicate with ISO/IEC 14443A/MI
E cards and transponders without
additional active circuitry. The digital module manages the complete ISO/IEC 14443A
framing and error detection functionality (parity and CRC).
The JSM66302 supports MIFARE Classic 1K, MIFARE Classic 4K, MIFARE Ultralight,
MIFARE Ultralight C, MIFARE PLUS and MIFARE DESFire products. The JSM66302
supports MIFARE higher tra
sfer speeds of up to 848 kbit/s in both directions.
The JSM66302 supports layer 2 and 3 of the ISO/IEC 14443B reader/writer
communication scheme except anticollision. The anticollision needs to be implemented in
the firmware
e host controller as well as in the upper layers.
The JSM
02 is able to demodulate and decode FeliCa coded signals. The FeliCa
receiver part provides the demodulation and decoding circuitry for FeliCa coded signals.
The JSM66302 handles the FeliCa framing and error detection such as CRC. The
JSM66302 supports FeliCa higher transfer speeds of up to 424 kbit/s in both directions.
The JSM66302 is supporting the P2P passive initiator mode in accordance with
ISO/IEC 18092.
The JSM66302 supports the vicinity protocol according to ISO/IEC15693, EPC UID
and ISO/IEC 18000-3 mode 3/ EPC Class-1 HF.
The following host interfaces are supported:
第1页,共139页
JSM66302
High performance multi-protocol NFC frontend
•
•
•
Serial Peripheral Interface (SPI)
Serial UART (similar to RS232 with voltage levels dependent on pin voltag
e
s
upply)
I
2
C-bus interface (two versions are implemented: I2C and I2CL)
The JSM66302 supports the connection of a secure access module (SAM). A dedicated
separate I2C interface is implemented for a connection of the SAM. The SAM can be used
for high secure key storage and acts as a very performant crypto-coprocessor. A
dedicated SAM is available for connection to the JSM66302.
2.
Features and benefits
Includes JSM
ISO/IEC14443-A and Innovatron ISO/IEC14443-B intellectua
l
p
roperty
licensing rights
High performance multi-protocol NFC frontend for transfer speed up to 848 kbit/s
Supports ISO/IEC 14443 A/MIFARE, ISO/IEC 1444
B and FeliCa reader modes
P2P passive initiator mode in accordance with ISO
18092
Supports ISO/IEC15693, ICODE EPC UID and ISO/IEC 18000-3 mode 3
/
E
PC
Class-1 HF
Supports MIFARE Classic encryption by ha
dware in read/write mode
Allows reading MIFARE Ultralight, MIFARE Classic 1K, MIFARE Classic 4K, MIFARE
DESFire EV1, MIFARE DESfireEV2 and MIFARE Plus cards
Low-Power Card Detection
Compliance to EMV contactless protocol specification on RF level can be achieved
Supported host interface
:
SPI up to 10 Mbit/s
I
2
C-bus interfaces up to 400 kBd in Fast mode, up to 1000 kBd in Fast mod
e
p
lus
RS23
al UART up to 1228.8 kBd, with voltage levels dependent on pin
vo
e s
ply
Separa
e I
2
C-bus interface for connection of a secure access module (SAM)
F
FO buffer with size of 512 bytes for highest transaction performance
Flexible and efficient power-saving modes including hard power down, standby and
low-power card detection
Cost saving by integrated PLL to derive system clock from 27.12 MHz RF quartz
crystal
3.0 V to 5.5 V power supply
Up to 8 free programmable input/output pins
Typical operating distance in read/write mode for communication to a
ISO/IEC 14443A/MIFARE Card up to 12 cm, depending on the antenna size and
tuning
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JSM66302
High performance multi-protocol NFC frontend
3.
Quick reference data
Table 1.
Quick reference data
JSM66302
Symbol
V
DD
Parameter
Conditions
Min
3.0
3.0
3.0
–
Typ
5.0
5.0
5.0
8
Max
5.5
V
DD
5.5
40
Unit
V
supply voltage
[1]
[2]
PVDD supply voltage
TVDD supply voltage
power-down current
supply current
V
V
DD(PVDD)
V
DD(TVDD)
I
pd
V
PDOWN pin pulled HIGH
nA
mA
mA
C
–
17
20
I
DD
I
DD(TVDD)
T
amb
TVDD supply current
operating ambient temperature
storage temperature
–
100
+25
+25
250
+85
25
55
T
stg
no supply voltage applied
+125
C
[1]
VDD(PVDD) must always be the same or lower voltage than VDD.
[2]
I
pd
is the sum of all supply currents
第3页,共139页
JSM66302
High performance multi-protocol NFC frontend
4.
Block diagram
The analog interface handles the modulation and demodulation of the antenna signals for
the contactless interface.
The contactless UART manages the protocol dependency of the contactless interface
settings managed by the host.
The FIFO buffer ensures fast and convenient data transfer between host and the
contactless UART.
The register bank contains the settings for the analog and digital functio
ty.
REGISTER BANK
ANALOG
INTERFACE
CONTACTLESS
UART
ANTENNA
FIFO
BUFFE
SERIAL UART
SPI
HOST
2
I C-BUS
001aaj627
Fig 1.
Simplified block diagram of the
5.
Pinning information
terminal 1
index area
TDO/OUT0
TDI/OUT1
TMS/OUT2
TCK/OUT3
SIGIN/OUT7
SIGOUT
1
2
3
4
5
6
7
8
24 SDA
(1)
23 SCL
22 CLKOUT/OUT6
21 PDOWN
20 XTAL2
19 XTAL1
18 TVDD
17 TX1
heatsink
DVDD
VDD
001aam004
Transparent top view
(1) Pin 33 VSS – heat sink connection
Fig 2.
Pinning configuration HVQFN32
第4页,共139页
JSM66302
High performance multi-protocol NFC frontend
5
.1 Pin description
Table 4.
Pin description
Pin
1
Symbol
TDO / OUT0
TDI / OUT1
TMS / OUT2
TCK / OUT3
SIGIN /OUT7
SIGOUT
DVDD
Type
Description
O
test data output for boundary scan interface / general purpose output 0
test data input boundary scan interface / general purpose output 1
test mode select boundary scan interface / general purpose output 2
test clock boundary scan interface / general purpose output 3
Contactless communication interface output. / general purpose output 7
Contactless communication interface input.
2
I
3
I
4
I
5
I
6
O
7
PWR
8
VDD
PWR
power supply
9
AVDD
PWR
10
11
12
13
14
15
16
17
18
19
AUX1
O
auxiliary outputs: Pin is used for analog test signal
auxiliary outputs: Pin is used for analog tes
al
receiver input pin for the received RF signal.
receiver input pin for the received
signal.
AUX2
O
RXP
I
RXN
I
VMID
PWR
O
TX2
transmitter 2: delivers the modulated 13.56 MHz carrier
transmitter ground, supplies the output stage of TX1, TX2
transmitter 1: delivers the modulated 13.56 MHz carrier
transmitter volta
e supply
TVSS
PWR
O
TX1
TVDD
PWR
I
XTAL1
crystal oscillator input: Input to the inverting amplifier of the oscillator. This pin is
also the input
or an externally generated clock (fosc = 27.12 MHz)
20
21
22
23
24
25
26
27
28
XTAL2
O
crystal oscillator output: output of the inverting amplifier of the oscillator
wer Down (RESET)
PDOWN
CLKOUT / OUT6
SCL
I
O
k output / general purpose output 6
Serial Clock line
O
SDA
I/O
Serial Data Line
PVDD
PWR
pad power supply
IFSEL0 / OUT4
IFSEL1 / OUT5
IF0
I
host interface selection 0 / general purpose output 4
host interface selection 1 / general purpose output 5
I
I/O
interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, I
2
C,
I
2
C-L
29
30
IF1
IF2
I/O
I/O
interface pin, multifunction pin: Can be assigned to host interface SPI, I
2
C, I
2
C-L
interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, I
2
C,
I
2
C-L
31
IF3
I/O
interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, I
2
C,
I
2
C-L
32
33
IRQ
O
interrupt request: output to signal an interrupt event
ground and heat sink connection
VSS
PWR
[1] This pin is used for connection of a buffer capacitor. Connection of a supply voltage might damage the device.
第5页,共139页
JSM66302
High performance multi-protocol NFC frontend
6
. Functional
description
Fig 3.
Detailed block diagram of the
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JSM66302
High performance multi-protocol NFC frontend
6.1
Interrupt controller
The interrupt controller handles the enabling/disabling of interrupt requests. All of the
interrupts can be configured by firmware. Additionally, the firmware has possibilities to
trigger interrupts or clear pending interrupt requests. Two 8-bit interrupt registers IRQ0
and IRQ1 are implemented, accompanied by two 8-bit interrupt enable registers IRQ0En
and IRQ1En. A dedicated functionality of bit 7 to set and clear bits 0 to 6 in this interrupt
controller register is implemented.
The JSM66302 indicates certain events by setting bit IRQ in the register Sta
us1Reg and
additionally, if activated, by pin IRQ. The signal on pin IRQ may be used
interrupt the
host using its interrupt handling capabilities. This allows the implementa
of efficient
host software.
Table 4. shows the available interrupt bits, the corresponding source and the condition for
its activation. The interrupt bits Timer0IRQ, Timer1IRQ, Timer2IRQ, Timer3OIRQ, in
register IRQ1 indicate an interrupt set by the timer unit. The setting is done if the timer
underflows.
The TxIRQ bit in register IRQ0 indicates that the t
ansmission is finished. If the state
changes from sending data to transmitting th
d of the frame pattern, the transmitter
unit sets the interrupt bit automatically.
The bit RxIRQ in register IRQ0 indicates an interrupt when the end of the received data is
detected.
The bit IdleIRQ in register IRQ0 is set if a command finishes and the content of the
command register changes
id
e.
The register WaterLevel defines both – minimum and maximum warning levels – counting
from top and from bottom of the FIFO by a single value.
The bit HiAlert
n register IRQ0 is set to logic 1 if the HiAlert bit is set to logic 1, that
means t
IFO data number has reached the top level as configured by the register
WaterLevel and bit WaterLevelExtBit.
The bit LoAlertIRQ in register IRQ0 is set to logic 1 if the LoAlert bit is set to logic 1, that
means the FIFO data number has reached the bottom level as configured by the register
WaterLevel.
The bit ErrIRQ in register IRQ0 indicates an error detected by the contactless UART
during receive. This is indicated by any bit set to logic 1 in register Error.
The bit LPCDIRQ in register IRQ0 indicates a card detected.
The bit RxSOFIRQ in register IRQ0 indicates a detection of a SOF or a subcarrier by the
contactless UART during receiving.
The bit GlobalIRQ in register IRQ1 indicates an interrupt occurring at any other interrupt
source when enabled.
第7页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 5.
Interrupt sources
Interrupt bit
Timer0IRQ
Timer1IRQ
Timer2IRQ
Timer3IRQ
TxIRQ
Interrupt source
Timer Unit
Is set automatically, when
the timer register T0 CounterVal underflows
the timer register T1 CounterVal underflows
the timer register T2 CounterVal underflows
the timer register T3 CounterVal underflows
a transmitted data stream ends
Timer Unit
Timer Unit
Timer Unit
Transmitter
RxIRQ
Receiver
a received data stream ends
IdleIRQ
Command Register
FIFO-buffer pointer
a command execution finishes
HiAlertIRQ
the FIFO data number has reached the top level as
configured by the register WaterLevel
LoAlertIRQ
FIFO-buffer pointer
the FIFO data number has reached the bottom level as
configured by the register WaterLevel
ErrIRQ
contactless UART
LPCD
a communication error had been detected
LPCDIRQ
a card was detecte
en in low-power card detection
mode
RxSOFIRQ
GlobalIRQ
Receiver
detection of a SOF or a subcarrier
all interrupt sources
will be se
other interrupt request source is set
6.2
Timer module
Timer module overview
The JSM66302 implements
e timers. Four timers -Timer0 to Timer3 – have an input clock
that can be configured by register T(x)Control to be 13.56 MHz, 212 kHz, (derived from
the 27.12 MHz quartz) or to be the underflow event of the fifth Timer (Timer4). Each timer
implements a counter register which is 16 bit wide. A reload value for the counter is
defined in a r
of 0000h to FFFFh in the registers TxReloadHi and TxReloadLo. The
fifth timer
me
intended to be used as a wake-up timer and is connected to the
internal L
O (Low Frequency Oscillator) as input clock source.
The TCon
rol register allows the global start and stop of each of the four timers Timer0 to
Timer3. Additionally, this register indicates if one of the timers is running or stopped. Each
of the five timers implements an individual configuration register set defining timer reload
value (e.g. T0ReloadHi,T0ReloadLo), the timer value (e.g. T0CounterValHi,
T0CounterValLo) and the conditions which define start, stop and clockfrequency(e.g.
T0Control).
The external host may use these timers to manage timing relevant tasks. The timer unit
may be used in one of the following configurations:
•
•
•
•
•
Time-out counter
Watch-dog counter
Stop watch
Programmable one-shot timer
Periodical trigger
第8页,共139页
JSM66302
High performance multi-protocol NFC frontend
The timer unit can be used to measure the time interval between two events or to indicate
that a specific event has occurred after an elapsed time. The timer register content is
modified by the timer unit, which can be used to generate an interrupt to allow a host to
react on this event.
The counter value of the timer is available in the registers T(x)CounterValHi,
T(x)CounterValLo. The content of these registers is decremented at each timer clock.
If the counter value has reached a value of 0000h and the interrupts are enabled for this
specific timer, an interrupt will be generated as soon as the next clock is received.
If enabled, the timer event can be indicated on the pin IRQ (interrupt re
t). The bit
Timer(x)IRQ can be set and reset by the host controller. Depending on the configuration,
the timer will stop counting at 0000h or restart with the value loaded from registers
T(x)ReloadHi, T(x)ReloadLo.
The counting of the timer is indicated by bit TControl.T(x)Running.
The timer can be started by setting bits TControl.T(x)R
ing and
TControl.T(x)StartStopNow or stopped by setting
he bits TControl.T(x)StartStopNow and
clearing TControl.T(x)Running.
Another possibility to start the timer is to set the bit T(x)Mode.T(x)Start. This can be useful
if dedicated protocol requirements need to be fulfilled.
6.2.1
Timer modes
6.2.1.1
Time-Out- and Watch-Dog
Counter
Having configured the timer by setting
register T(x)ReloadValue
and starting the counting
of Timer(x) by setting bit TControl.T(x)StartStop and TControl.T(x)Running, the timer unit
decrements t
T(x)CounterValue
Register beginning with the configured start event. If
the configure
event occurs before the Timer(x) underflows (e.g. a bit is received
from the
d), the timer unit stops (no interrupt is generated).
If no stop event occurs, the timer unit continues to decrement the counter registers until
the content is zero and generates a timer interrupt request at the next clock cycle. This
allows indicating to a host that the event did not occur during the configured time interval.
6.2.1.2
Wake-up timer
The wake-up Timer4 allows to wake-up the system from standby after a predefined time.
The system can be configured in such a way that it is entering the standby mode again in
case no card had been detected.
This functionality can be used to implement a low-power card detection (LPCD). For the
low-power card detection, it is recommended to set T4Control.T4AutoWakeUp and
T4Control.T4AutoRestart, to activate the Timer4 and automatically set the system in
standby. The internal low frequency oscillator (LFO) is then used as input clock for this
Timer4. If a card is detected, the host-communication can be started. If bit
T4Control.T4AutoWakeUp is not set, the JSM66302 will not enter the standby mode
again in case no card is detected but stays fully powered.
第9页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.2.1.3
Stop watch
The elapsed time between a configured start- and stop event may be measured by the
JSM66302 timer unit. By setting the registers
T(x)ReloadValueHi, T(x)reloadValueLo
the
timer starts to decrement as soon as activated. If the configured stop event occurs, the
timer stops decrementing. The elapsed time between start and stop event can then be
calculated by the host dependent on the timer interval TTimer:
T
Treload
value
Timer
value
*
T
Timer
(1)
If an underflow occurred which can be identified by evaluating the corre
nding IRQ bit,
the performed time measurement according to the formula above is not correct.
6.2.1.4
Programmable one-shot timer
The host configures the interrupt and the timer, starts the timer and waits for the interrupt
event on pin IRQ. After the configured time, the interrup
request will be raised.
6.2.1.5
Periodical trigger
If the bit
T(x)Control.T(x)AutoRestart is set an
e interrupt is activated
, an interrupt
request will be indicated periodically after ever
lapsed timer period
.
6.3
Contactless interface unit
The contactless interface unit of the JSM66302 supports the following read/write
operating modes:
•
•
•
•
•
•
ISO/IEC14443A/MIFARE
ISO/IEC14443B
FeliCa
ISO/
15
ICODE
ICODE EPC UID
ISO/IEC 18000-3 mode 3/ EPC Class-1 HF
BATTERY/POWER SUPPLY
READER IC
ISO/IEC 14443 A CARD
MICROCONTROLLER
reader/writer
001aal996
Fig 4.
Read/write mode
A typical system using the JSM66302 is using a microcontroller to implement the higher
levels of the contactless communication protocol and a power supply (battery or external
supply).
第10页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.3.1
ISO/IEC14443A/MIFARE functionality
(1)
ISO/IEC 14443 A
ISO/IEC 14443 A CARD
READER
(2)
001aam268
(1)
Reader to Card 100 % ASK, Miller Coded, Transfer speed 106 kbit/s to 848 kbit/s
(2)
Card to Reader, Subcarrier Load Modulation Manchester Coded or BPSK, tr
speed
106 kbit/s to 848 kbit/s
Fig 5.
ISO/IEC 14443 A/MIFARE read/write mode communication diagram
Table 6.
Communication overview for ISO/IEC 14443 A/MIFARE reader/writer
Communication
direction
Signal type
Transfer speed
106 kbit/s
212 kbit/s
424 kbit/s
848 kbit/s
Reader to card (send
reader side
100 % ASK
100% ASK
100% ASK
100% ASK
data from the JSM66302 modulation
to a card)
fc = 13.56 MHz
bit encoding
modified Miller
encoding
modified Miller
encoding
modified Miller
encoding
modified Miller
encoding
bit rate [kbit/s]
fc / 128
fc / 64
fc / 32
fc / 16
Card to reader
(JSM66302
card side
modulation
subcarrier lo
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
receives data from
a card)
subcarrier
frequency
fc / 16
fc / 16
fc / 16
fc / 16
bit encoding
Manchester
coding
BPSK
BPSK
BPSK
The JSM6
302 connection to a host is required to manage the complete
according to ISO/IEC 14443A /MIFARE.
第11页,共139页
JSM66302
High performance multi-protocol NFC frontend
ISO/IEC 14443 A framing at 106 kBd
start
8-bit data
8-bit data
8-bit data
odd
odd
odd
parity
parity
parity
start bit is 1
ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd
start
even
parity
8-bit data
8-bit data
8-bi
odd
odd
start bit is 0
burst of 32
subcarrier clocks
parity
parity
even parity at the
end of the frame
001aak585
Fig 6.
Data coding and framing according to ISO/IEC 1444
3
A
The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A
part 3 and handles parity generation internally
cording to the transfer speed.
第12页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.3.2
ISO/IEC14443B functionality
(1)
ISO/IEC 14443 B
ISO/IEC 14443 B CARD
READER
(2)
001aal997
(1)
Reader to Card NRZ, Miller coded, transfer speed 106 kbit/s to 848 kbit/s
(2)
Card to reader, Subcarrier Load Modulation Manchester Coded or BPSK, tran
peed 106 kbit/s
to 848 kbit/s
Fig 7.
ISO/IEC 14443 A/MIFARE read/write mode communication diagram
Table 7.
Communication overview for ISO/IEC 14443 B reader/writer
Communication
direction
Signal type
Transfer speed
106 kbit/s
212 kbit/s
424 kbit/s
848 kbit/s
Reader to card (send
reader side
10 % ASK
10 % ASK
10 % ASK
10 % ASK
data from the JSM66302 modulation
to a card)
bit encoding
NRZ
NRZ
NRZ
NRZ
fc = 13.56 MHz
bit rate [kbit/s]
128 / fc
64 / fc
32 / fc
16 / fc
Card to reader
(JSM66302
card side
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
receives data from
a card)
subcarrier
frequency
fc / 1
fc/ 16
fc / 16
fc / 16
bit encoding
BPSK
BPSK
BPSK
BPSK
The JSM6630
nected to a host is required to manage the complete ISO/IEC 14443
the ISO/IEC 14443B SOF and EOF.
UNMODULATED (SUB)
”0” ”0” ”0” ”0” ”0” ”0” ”0” ”0” ”0” ”0”
”1” ”1”
DATA
CARRIER
UNMODULATED (SUB)
CARRIER
LAST CHARACTER
”0” ”0” ”0” ”0” ”0” ”0” ”0” ”0” ”0” ”0”
001aam270
Fig 8.
SOF and EOF according to ISO/IEC 14443 B
第13页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.3.3
FeliCa functionality
The FeliCa mode is the general reader/writer to card communication scheme according to
1.
PCD to PICC 8-30 % ASK
FeliCa CARD
(PICC)
Manchester Coded,
baudrate 212 to 424 kbaud
FeliCa READER
(PCD)
2.
PICC to PCD, >12 % Loadmodulation
Manchester Coded,
baudrate 212 to 424 kbaud
00
1
Fig 9.
FeliCa read/write communication diagram
Table 8.
Communication overview for FeliCa reader/wr
ter
Communication
direction
Signal type
Transfer spe
FeliCa FeliCa
higher transfer
speeds
212
it/s
424 kbit/s
Reader to card (send
reader side
8 %
30 % ASK
8 % to 30 % ASK
data from the JSM66302
modulation
to a card)
bit encoding
Manchester encoding
fc/64
Manchester encoding
fc/32
fc = 13.56 MHz
bit rate
Card to reader
(JSM66302 receives
data from a card)
card side load
mo
ula
ion
Load modulation
Load modulation
bit encoding
Manchester encoding
Manchester encoding
The JSM66302 needs to be connected to a dedicated host to be able to support the
complete Fe
protocol.
6.3.3.1
FeliCa fr
ng and coding
Table 9.
FeliCa framing and coding
Preamble (Hex.)
Sync
Len n-Data
CRC
(Hex.)
00
00
00
00
00
00
B2
4D
To enable the FeliCa communication a 6 byte preamble (00h, 00h, 00h, 00h, 00h, 00h)
and 2 bytes sync bytes (B2h, 4Dh) are sent to synchronize the receiver.
The following Len byte indicates the length of the sent data bytes plus the LEN byte itself.
The CRC calculation is done according to the FeliCa definitions with the MSB first.
To transmit data on the RF interface, the host controller has to send the Len- and data-
bytes to the JSM66302’s FIFO-buffer. The preamble and the sync bytes are generated by
the JSM66302 automatically and must not be written to the FIFO by the host controller.
The JSM66302 performs internally the CRC calculation and adds the result to the data
frame.
第14页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.3.4
ISO/IEC15693 functionality
Table 10.
Communication overview for ISO/IEC 15693 reader/writer reader to label
Communication
direction
Signal type
Transfer speed
fc / 8192 kbit/s
fc / 512 kbit/s
Reader to label (send
reader side
10 % to 30 % ASK or
100 % ASK
10 % to 30 % ASK 90 %
to 100 % ASK
data from the
modulation
bit encoding
data rate
JSM66302 to a card)
1/256
1/4
1.66 kbit/s
26.48
s
Table 11.
Communication overview for ISO/IEC 15693 reader/writer label to reader
Communication Signal
type Transfer
speed
direction
6.62 (6.67) kbit/s
13.24
26.48
(26.69) kbit/s
52.96 kbit/s
Label to reader
(JSM66302
card side
modulation
not supported
not supported
single (dual)
single
subcarrier
load
modulation
ASK
subcarrier
load
receives data
from a card)
modulation
ASK
fc = 13.56 MHz
bit length
(
s)
–
–
–
–
–
–
37.76 (37.46)
18.88
bit encoding
Manchester
coding
Manchester
coding
subcarrier
frequency
[MHz]
fc / 32
fc / 32
(fc / 28)
[1] Fast inve
ory
read command only (ICODE proprietary command).
pulse
modulated
~9.44
s
~18.88
s
carrier
0 1 2 3 4
.
.
.
2
2
5
.
.
.
.
.
.
.
.
.
.
. . .
. . . . . . . 2
2 2 2
5 5 5
2 3 4
5
5
~4,833 ms
001aam272
Fig 10.
Data coding according to ISO/IEC 15693. standard mode reader to label
第15页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.3.5
EPC-UID/UID-OTP functionality
Table 12.
Communication overview for EPC/UID
Communication
direction
Signal type
Transfer speed
26.48 kbit/s
52.96 kbit/s
Reader to card (send
data from the
JSM66302 to a card)
reader side modulation
10 % to 30 % ASK
bit encoding
RTZ
bit length
37.76
s
Card to reader
(JSM66302 receives
data from a card)
card side modulation
sing
bcarrier load
modulation
bit length
18.88
s
bit encoding
Manchester coding
Data coding and framing according to EPC global 13.5
MHz ISM (industrial, scientific
and medical) Band Class 1 Radio Frequency Identific
Tag Interface Specification
(Candidate Recommendation, Version 1.0.0).
6.3.6
ISO/IEC 18000-3 mode 3/ EPC Class-1
unctionality
The ISO/IEC 18000-3 mode 3/ EPC Class-1 HF is not described in this document. For a
detailed explanation of the protocol, refer to the ISO/IEC 18000-3 mode 3/ EPC Class-1
HF standard.
6.3.6.1
Data encoding ICODE
The ICODE protocols have mainly three different methods of data encoding:
•
•
•
“1” out of “4” coding scheme
“1” out of
” coding scheme
“Ret
o Zero” (RZ) coding scheme
Data encoding for all three coding schemes is done by the ICODE generator.
The supported EPC Class-1 HF modes are:
•
•
•
•
2 pulse for 424 kbit subcarrier
4 pulse for 424 kbit subcarrier
2 pulse for 848 kbit subcarrier
4 pulse for 848 kbit subcarrier
6.3.7
ISO/IEC 18092 mode
The JSM66302 supports Passive Initiator Communication mode at the transfer speeds
106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the ISO/IEC 18092 standard.
•
•
Passive communication mode means that the target answers to an initiator command
in a load modulation scheme. The initiator is active in terms of generating the RF field.
Initiator: generates RF field at 13.56 MHz and starts the ISO/IE
C
1
8092
communication.
第16页,共139页
JSM66302
High performance multi-protocol NFC frontend
•
Target: responds to initiator command either in a load modulation scheme in Passive
communication mode or using a self-generated and self-modulated RF field for Active
Communication mode.
6.3.7.1
Passive communication mode
Passive communication mode means that the target answers to an initiator command in a
load modulation scheme. The initiator is active meaning generating the RF field.
1. initiator starts communication
at selected transfer speed
host
host
NFC TARGET
powered for
NFC INITIATOR
2. targets answers using
load modulated data
at the
sa
transfer speed
powered to
digital processing
generate RF field
001aan217
Fig 11. Passive communication mode
Table 13.
Communication overview for Passive communication mode
Communication
direction
106 kbit/s
212 kbit/s
424 kbit/s
Initiator
target
Target
iat
According to
According to FeliCa, 8 % to 30 % ASK
Manchester Coded
ISO/IEC 14443A
100 % ASK, Modified
Miller Coded
According to
According to FeliCa, > 12 % ASK
Manchester Coded
ISO/IEC 14443A subcarrier
load modulation,
Manchester Coded
The contactless UART of JSM66302 and a dedicated host controller are required to handle
the ISO/IEC 18092 passive initiator protocol.
第17页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.3.7.2
ISO/IEC 18092 framing and coding
The ISO/IEC 18092 framing and coding in Passive communication mode is defined in the
ISO/IEC 18092 standard.
Table 14.
Framing and coding overview
106 kbit/s
212 kbit/s
424 kbit/s
According to the ISO/IEC 14443A/MIFARE scheme
According to the FeliCa scheme
According to the FeliCa scheme
6.3.7.3
ISO/IEC 18092 protocol support
The ISO/IEC 18092 protocol is not described in this document. For a detailed explanation
of the protocol, refer to the ISO/IEC 18092 standard.
6.4
Host interfaces
6.4.1
Host interface configuration
The JSM66302 supports direct interfacing of
us hosts as the SPI, I
2
C, I
2
CL and
serial UART interface type. The JSM66302 resets its interface and checks the current
host interface type automatically having performed a power-up or resuming from power
down. The JSM66302 identifies the host interface by the means of the logic levels on the
control pins after the Cold Reset Phase. This is done by a combination of fixed pin
connections.The following table shows the possible configurations defined by
IFSEL1,IFSEL0:
Table 15.
Connection scheme for detecting the different interface types
28
29
30
31
26
27
RX
MOSI
SCK
ADR1
SCL
ADR1
IF1
n.c.
SCL
IF2
TX
MISO
NSS
ADR2
SDA
SDA
IF3
PAD_VDD
VSS
VSS
ADR2
IFSEL0
IFSEL1
VSS
PAD_VDD
VSS
PAD_VDD
PAD_VDD
PAD_VDD
6.4.2
SPI interface
6.4.2.1
General
READER IC
SCK
IF1
IF0
IF2
IF3
MOSI
MISO
NSS
001aal998
Fig 12. Connection to host with SPI
第18页,共139页
JSM66302
High performance multi-protocol NFC frontend
The JSM66302 acts as a slave during the SPI communication. The SPI clock SCK has
to be generated by the master. Data communication from the master to the slave uses
the Line MOSI. Line MISO is used to send data back from the JSM66302 to the master.
A serial peripheral interface (SPI compatible) is supported to enable high-speed
communication to a host. The implemented SPI compatible interface is according to a
standard SPI interface. The SPI compatible interface can handle data speed of up to 10
Mbit/s. In the communication with a host, JSM66302 acts as a slave receiving data from
the external host for register settings and to send and receive data relevant for the
communication on the RF interface.
NSS (Not Slave Select) enables or disables the SPI interface. When NS
s logical high,
the interface is disabled and reset. Between every SPI command, the N
must go to
logical high to be able to start the next command read or write.
On both data lines (MOSI, MISO) each data byte is sent by MSB fi
st. Data on MOSI line
shall be stable on rising edge of the clock line (SCK) and is allowed to change on falling
edge. The same is valid for the MISO line. Data is provided by the JSM66302 on the falling
edge and is stable on the rising edge.The polarity of t
ock is low at SPI idle.
6.4.2.2
Read data
To read out data from the JSM66302 by using
SPI compatible interface, the following
byte order has to be used.
The first byte that is sent defines the mode (LSB bit) and the address.
Table 16.
Byte Order for MOSI and MISO
byte 0
byte 1
byte 2
byte 3 to n-1
byte n
byte n+1
00h
MOSI address
0
address 1
data 0
address 2
data 1
……..
……..
address n
data n
1
MISO
X
data n
Remark:
The
Significant Bit (MSB) has to be sent first.
6.4.2.3
Write data
To write d
ta to the JSM66302 using the SPI interface, the following byte order has to be
used. It is possible to write more than one byte by sending a single address byte
(see.8.5.2.4).
The first send byte defines both, the mode itself and the address byte.
Table 17.
Byte Order for MOSI and MISO
byte 0
address 0
X
byte 1
data 0
X
byte 2
data 1
X
3 to n-1
……..
byte n
data n
1
X
byte n + 1
data n
X
MOSI
MISO
……..
Remark:
The Most Significant Bit (MSB) has to be sent first.
6.4.2.4
Address byte
The address byte has to fulfill the following format:
The LSB bit of the first byte defines the used mode. To read data from the JSM66302,
the LSB bit is set to logic 1. To write data to the JSM66302, the LSB bit has to be cleared.
The bits 6 to 0 define the address byte.
第19页,共139页
JSM66302
High performance multi-protocol NFC frontend
NOTE: When writing the sequence [address byte][data0][data1][data2]…, [data0] is written
to address [address byte], [data1] is written to address [address byte + 1] and [data2] is
written to [address byte + 2].
Exception: This auto increment of the address byte is not performed if data is written to
the FIFO address
Table 18.
Address byte 0 register; address MOSI
7
6
5
4
3
2
1
0
address 6
address 5
address 4
address 3
address 2
address 1
address 0
1 (read)
0 (write)
MSB
LSB
6.4.2.5
Timing Specification SPI
The timing condition for SPI interface is as follows:
Table 19.
Timing conditions SPI
Symbol
t
SCKL
Parameter
Min
50
50
25
25
–
Typ
Max
Unit
SCK LOW time
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
t
SCKH
SCK HIGH time
–
t
h(SCKH-D)
t
su(D-SCKH)
t
h(SCKL-Q)
t
(SCKL-NSSH)
t
NSSH
SCK HIGH to data input hold t
me
data input to SCK HIGH set-up time
SCK LOW to data output hold time
SCK LOW t
NSS HIGH time
NSS HIGH time
–
–
25
–
0
50
–
t
t
t
SCKL
NSSH
SCKH
SCK
t
h(SCKL-Q)
t
su(D-SCKH)
t
h(SCKH-D)
MOSI
MISO
MSB
LSB
MSB
LSB
t
(SCKL-NSSH)
NSS
aaa-016093
Fig 13. Connection to host with SPI
Remark:
To send more bytes in one data stream, the NSS signal must be LOW during
the send process. To send more than one data stream, the NSS signal must be HIGH
between each data stream.
第20页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.4.3
RS232 interface
6.4.3.1
Selection of the transfer speeds
The internal UART interface is compatible to an RS232 serial interface. The levels
supplied to the pins are between VSS and PVDD. To achieve full compatibility of the
voltage levels to the RS232 specification, an RS232 level shifter is required.
Table 21 “Selectable transfer speeds”
describes examples for different transfer speeds
and relevant register settings. The resulting transfer speed error is less than 1.5 % for all
described transfer speeds. The default transfer speed is 115.2 kbit/s.
To change the transfer speed, the host controller has to write a value fo
e new transfer
speed to the register SerialSpeedReg. The bits BR_T0 and BR_T1 define factors to set
the transfer speed in the SerialSpeedReg.
Table 20 “Settings of BR_T0 and BR_T1”
describes the settings of BR_T0 and BR_T1.
Table 20.
Settings of BR_T0 and BR_T1
BR_T0
0
1
1
1
2
2
3
4
4
8
5
6
7
factor BR_T0
16
32
64
range BR_T1
1 to 32
33 to 64
33 to 64
33 t
64 33
to 64
33 to 64
33 to 64
33 to 64
Table 21.
Selectable transfer speeds
7.2
FA
EB
DA
CB
AB
9A
7A
74
0.25
0.32
9.6
14.4
19.2
38.4
57.6
115.2
128
0.25
0.32
0.32
0.25
0.25
0.06
0.25
0.25
1.45
230.4
460.8
921.6
1228.8
5A
3A
1C
15
0.32
The selectable transfer speeds as shown are calculated according to the following
formulas:
if BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1)
if BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33)/2
(BR_T0
1)
Remark:
Transfer speeds above 1228.8 kBits/s are not supported.
第21页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.4.3.2
Framing
Table 22. UART framing
Bit
Length
1 bit
Value
0
Start bit (Sa)
Data bits
Stop bit (So)
8 bit
Data
1
1 bit
Remark:
For data and address bytes, the LSB bit has to be sent first. No par
ty bit is used
during transmission.
Read data:
To read out data using the UART interface, the flow described below has to be
used. The first send byte defines both the mode itself and the address. The Trigger on pin
IF3 has to be set, otherwise no read of data is possible.
Table 23.
Byte Order to Read Data
Mode
RX
byte 0
address
–
e 1
–
TX
data 0
ADDRESS
RX
Sa
A0
A1
A2
A3
A4
A5
A6 RD/ So
NWR
DATA
TX
Sa
D0
D1
D2
D3
D4
D5
D6
D7
So
001aam298
Fig 14. Example for UART Read
Write data:
T
o
w
rite data to the JSM66302 using the UART interface, the following sequence has to
be used.
The first send byte defines both, the mode itself and the address.
Table 24.
Byte Order to Write Data
Mode
RX
byte 0
byte 1
address 0
data 0
TX
address 0
第22页,共139页
JSM66302
High performance multi-protocol NFC frontend
ADDRESS
DATA
RX
Sa A0 A1 A2 A3 A4
A5 A6 RD/ So
NWR
Sa D0 D1 D2 D3 D4 D5 D6 D7 So
ADDRESS
TX
Sa A0 A1 A2 A3 A4 A5 A6 RD/ So
NWR
001aam299
Fig 15. Example diagram for a UART write
Remark:
Data can be sent before address is received.
6.4.4
I
2
C-bus interface
6.4.4.1
General
An Inter IC (I
2
C) bus interface is supported to
able a low cost, low pin count serial bus
interface to the host. The implemented I
2
C interface is mainly implemented according to
I
2
C interface specification. The JSM66302 can act as a slave receiver or slave
transmitter in standard mode, fast mode and fast
mode plus.
2
:
The following features define
I C interface specification
•
•
The JSM66302 I2C interface does not stretch the clock
The JSM
02 I2C interface does not support the general call. This means that
the JSM6
does not support a software reset
•
•
The J
M66302 does not support the I2C device ID
The implemented interface can only act in slave mode. Therefore no clock generation
and access arbitration is implemented in the JSM66302.
•
High-speed mode is not supported by the JSM66302
PULL-UP
NETWORK
PULL-UP
NETWORK
READER IC
MICROCONTROLLER
SDA
SCL
001aam000
Fig 16. I
2
C-bus interface
The voltage level on the I2C pins is not allowed to be higher than PVDD.
SDA is a bidirectional line, connected to a positive supply voltage via a pull-up resistor.
Both lines SDA and SCL are set to HIGH level if no data is transmitted. Data on the
I
2
C-bus can be transferred at data rates of up to 400 kbit/s in fast mode, up to 1 Mbit/s in
the fast mode+.
第23页,共139页
JSM66302
High performance multi-protocol NFC frontend
If the I
2
C interface is selected, a spike suppression according to the I
2
C interface
specification on SCL and SDA is automatically activated.
6.4.4.2
I
2
C Data validity
Data on the SDA line shall be stable during the HIGH period of the clock. The HIGH state
or LOW state of the data line shall only change when the clock signal on SCL is LOW.
SDA
SCL
change
data line stable;
data valid
of data
allowed
001aam300
Fig 17. Bit transfer on the I
2
C-bus
6.4.4.3
I
2
C START and STOP conditions
To handle the data transfer on the I
2
C-bus, unique START (S) and STOP (P) conditions
are defined.
A START condition is define
ith a HIGH-to-LOW transition on the SDA line while SCL is
HIGH.
A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while SCL is
HIGH.
The mas
alw
generates the START and STOP conditions. The bus is considered to
be busy a
er the START condition. The bus is considered to be free again a certain time
after the STOP condition.
The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In
this respect, the START (S) and repeated START (Sr) conditions are functionally identical.
Therefore, the S symbol will be used as a generic term to represent both the START and
repeated START (Sr) conditions.
SDA
SCL
SDA
SCL
S
P
START condition
STOP condition
001aam301
Fig 18. START and STOP conditions
第24页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.4.4.4
I
2
C byte format
Each byte has to be followed by an acknowledge bit. Data is transferred with the MSB
during one data transfer is unrestricted but shall fulfill the read/write cycle format.
6.4.4.5
I
2
C Acknowledge
An acknowledge at the end of one data byte is mandatory. The acknowledge-related clock
pulse is generated by the master. The transmitter of data, either master or slave, releases
the SDA line (HIGH) during the acknowledge clock pulse. The receiver shall pull down the
SDA line during the acknowledge clock pulse so that it remains stable L
W during the
HIGH period of this clock pulse.
The master can then generate either a STOP (P) condition to stop the transfer, or a
repeated START (Sr) condition to start a new transfer.
A master-receiver shall indicate the end of data to the slave- transmitter by not generating
an acknowledge on the last byte that was clocked out
he slave. The slave-transmitter
shall release the data line to allow the master to generate a STOP (P) or repeated START
(Sr) condition.
DAT
A
O
UTPUT
BY TRANSMITTER
not acknowledge
DAT
A
O
UTPUT
BY RECEIVERER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
001aam302
Fig 19. A
knowledge on the I
2
C- bus
P
MSB
acknowledgement
signal from slave
acknowledgement
signal from receiver
r
byte complete,
interrupt within slave
clock line held low while
interrupts are serviced
S
or
Sr
Sr
or
P
1
2
7
8
9
1
2
3 – 8
9
ACK
ACK
001aam303
Fig 20. Data transfer on the I
2
C- bus
第25页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.4.4.6
I
2
C 7-bit addressing
During the I
2
C-bus addressing procedure, the first byte after the START condition is used
to determine which slave will be selected by the master.
Alternatively the I
2
C address can be configured in the EEPROM. Several address
numbers are reserved for this purpose. During device configuration, the designer has to
ensure, that no collision with these reserved addresses in the system is possible. Check
the corresponding I
2
C specification for a complete list of reserved addresses.
For all JSM66302 devices, the upper 5 bits of the device bus address are reserved by JSM
and set to 01010(bin). The remaining 2 bits (ADR_2, ADR_1) of the slav
dress can be
freely configured by the customer in order to prevent collisions with othe
C devices by
MSB
LSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
t 0
R/W
slave address
001aam304
Fig 21. First byte following the START procedu
6.4.4.7
I
2
C-register write access
To write data from the host controller via I
2
C to a specific register of the JSM66302, the
following frame format shall be used.
The read/write bit sha
l be set to logic 0.
The first byte of a frame indicates the device address according to the I
2
C rules. The
second byte
cates the register address followed by up to n-data bytes. In case the
address indic
he FIFO, in one frame all n-data bytes are written to the FIFO register
address
s enables for example a fast FIFO access.
6.4.4.8
I
2
C-register read access
T
o
r
ead out data from a specific register address of the JSM66302, the host controller
shall use the procedure:
First a write access to the specific register address has to be performed as indicated in the
following frame:
The first byte of a frame indicates the device address according to the I
2
C rules. The
second byte indicates the register address. No data bytes are added.
The read/write bit shall be logic 0.
Having performed this write access, the read access starts. The host sends the device
address of the JSM66302. As an answer to this device address, the JSM66302 responds
with the content of the addressed register. In one frame n-data bytes could be read using
the same register address. The address pointing to the register is incremented
automatically (exception: FIFO register address is not incremented automatically). This
enables a fast transfer of register content. The address pointer is incremented
automatically and data is read from the locations [address], [address+1], [address+2]…
[address+(n-1)]
第26页,共139页
JSM66302
High performance multi-protocol NFC frontend
In order to support a fast FIFO data transfer, the address pointer is not incremented
automatically in case the address is pointing to the FIFO.
The read/write bit shall be set to logic 1.
Write Cycle
0
(
W
)
I2C slave address
A7-A0
Frontend IC register
address A6-A0
DATA
[7..0]
SA
Ack
0
Ack
[0..n]
Ack
S
Read Cycle
0
I2C slave address
A7-A0
Frontend IC register
address A6-A0
Ack
0
Ac
(
)
SA
SO
W
Optional, if the previous access was on the same register add
0..n
1
(
R
)
I2C slave address
A7-A0
TA
[7..0]
SA
Ack
[0..n]
Ack
sent by master
sent by slave
DATA
[7..0]
Nack
SO
001aam305
Fig 22. Register read and write access
6.4.4.9
I
2
CL-bus inte
ace
The JSM6630
vides an additional interface option for connection of a SAM. This
logical in
ace fulfills the I
2
C specification, but the rise/fall timings will not be compliant to
the I
2
C standard. The I
2
CL interface uses standard I/O pads, and the communication
speed is limited to 5 MBaud. The protocol itself is equivalent to the fast mode protocol of
I
2
C. The SCL levels are generated by the host in push/pull mode. The RC663 does not
stretch the clock. During the high period of SCL, the status of the line is maintained by a
bus keeper.
The address is 01010xxb, where the last two bits of the address can be defined by the
application. The definition of these bits can be done by two options. With a pin, where the
higher bit is fixed to 0 or the configuration can be defined via EEPROM. Refer to the
Table 25.
Timing parameter I
2
CL
f
SCL
0
5
–
MHz
ns
80
100
100
80
0
t
HD;STA
t
LOW
–
ns
t
HIGH
–
ns
–
ns
t
SU;SDA
t
HD;DAT
50
ns
第27页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 25.
Timing parameter I
2
CL
t
SU;DAT
t
SU;STO
t
BUF
0
20
–
ns
ns
ns
80
200
–
The pull-up resistor is not required for the I
2
CL interface. Instead, a on chip buskeeper is
implemented in the JSM66302 for SDA of the I
2
CL interface. This protocol is intended to be
used for a point-to-point connection of devices over a short distance and doe
not support
a bus capability.The driver of the pin must force the line to the desired lo
c voltage. To
avoid that two drivers are pushing, the line at the same time following reg
tions must be
fulfilled:
SCL: As there is no clock stretching, the SCL is always under cont
ol of the Master.
SDA: The SDA line is shared between master and slave. Therefore the master and the
slave must have the control over the own driver enabl
e of the SDA pin. The following
rules must be followed:
•
•
In the idle phase, the SDA line is driven h
by the master
In the time between start and stop condition, the SDA line is driven by master or slave
when SCL is low. If SCL is high, the SDA line is not driven by any device
•
T
o
k
eep the value on the SDA line a on chip, buskeeper structure is implemented for
the line
6.4.5
SAM interface
6.4.5.1
SAM functionality
The JSM663
mplements a dedicated I2C or SPI interface to integrate a MIFARE SAM
(Secure Acces
dule) in a very convenient way into applications (e.g. a proximity
reader).
The SAM can be connected to the microcontroller to operate like a cryptographic
coprocessor. For any cryptographic task, the microcontroller requests an operation from
the SAM, receives the answer and sends it over a host interface (e.g. I2C, SPI) interface
to the connected reader IC.
The MIFARE SAM supports an optimized method to integrate the SAM in a very efficient
way to reduce the protocol overhead. In this system configuration, the SAM is integrated
between the microprocessor and the reader IC, connected by one interface to the reader
IC and by another interface to the microcontroller. In this application, the microcontroller
accesses the SAM using the T=1 protocol and the SAM accesses the reader IC using an
I2C interface. The I2C SAM address is always defined by EEPROM register. Default value
is 0101100. As the SAM is directly communicating with reader IC, the communication
overhead is reduced. In this configuration, a performance boost of up to 40 % can be
achieved for a transaction time.
The MIFARE SAM supports applications using MIFARE cards. For multi-application
purposes, an architecture connecting the microcontroller additionally directly to the reader
IC is recommended. This is possible by connecting the JSM66302 on one interface (SAM
Interface SDA, SCL) with the MIFARE SAM AV2.6 (P5DF081XX/T1AR1070) and by
connecting the microcontroller to the S2C or SPI interface.
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T=1
I2C
I2C
Reader
aa-002963
Fig 23. I2C interface enables convenient MIFARE SAM integration
6.4.5.2
SAM connection
The JSM66302 provides an interface to connect a SAM dedicated to the JSM66302. Both
interface options of the JSM66302, I
2
C, I
2
CL or SPI can be used for this purpose. The
interface option of the SAM itself is configured by a host command sent from the host to
the SAM.
The I
2
CL interface is intended to be used as connection between two ICs over a short
distance. The protocol fulfills the I
2
C specification, but does support a single device
connected to the bus only.
The SPI block for SAM connection is identical with the SPI host interface block.
Table 26.
SPI SAM connecti
MISO
SCL
SDA2
SCL2
MOSI
NSS
IFSEL1
IFSEL0
6.4.6
Boundary scan interface
The JSM66302 provides a boundary scan interface according to the IEEE 1149.1. This
interface allows testing interconnections without using physical test probes. This is done
by test cells, assigned to each pin, which override the functionality of this pin.
To be able to program the test cells, the following commands are supported:
Table 27.
Boundary scan command
0
1
1
2
3
4
5
bypass
–
–
preload
data (24)
–
sample
–
–
–
–
–
data (24)
ID code (default)
USER code
Clamp
data (32)
data (32)
–
–
HIGH Z
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High performance multi-protocol NFC frontend
Table 27.
Boundary scan command
7
extest
data (24)
data (24)
8
interface on/off
register access read
register access write
interface (1)
–
9
address (7)
data (8)
–
10
address (7) – data (8)
The Standard IEEE 1149.1 describes the four basic blocks necessary to use this interface:
Test Access Port (TAP), TAP controller, TAP instruction register, TAP da
egister;
6.4.6.1
Interface signals
The boundary scan interface implements a four line interface between the chip and the
environment. There are three Inputs: Test Clock (TCK); Test Mode Select (TMS); Test
Data Input (TDI) and one output Test Data Output (TDO). TCK and TMS are broadcast
signals, TDI to TDO generate a serial line called Scan
h.
Advantage of this technique is that independent o
the numbers of boundary scan devices
the complete path can be handled with four si
l lines.
The signals TCK, TMS are directly connected with the boundary scan controller. Because
these signals are responsible for the mode of the chip, all boundary scan devices in one
scan path will be in the same boundary scan mode.
6.4.6.2
Test Clock (TCK)
The TCK pin is the input clock for the module. If this clock is provided, the test logic is able
to operate independent of any other system clocks. In addition, it ensures that multiple
boundary scan controllers that are daisy-chained together can synchronously
communicate
ial test data between components. During normal operation, TCK is
driven by a fre
ning clock. When necessary, TCK can be stopped at 0 or 1 for
extende
riods of time. While TCK is stopped at 0 or 1, the state of the boundary scan
cont
oller does not change and data in the Instruction and Data Registers is no
t
l
ost.
The internal pull-up resistor on the TCK pin is enabled. This assures that no clocking
occurs if the pin is not driven from an external source.
6.4.6.3
Test Mode Select (TMS)
The TMS pin selects the next state of the boundary scan controller. TMS is sampled on
the rising edge of TCK. Depending on the current boundary scan state and the sampled
value of TMS, the next state is entered. Because the TMS pin is sampled on the rising
edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the
falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the boundary scan controller
state machine to the Test-Logic-Reset state. When the boundary scan controller enters
the Test-Logic-Reset state, the Instruction Register (IR) resets to the default instruction,
IDCODE. Therefore, this sequence can be used as a reset mechanism.
The internal pull-up resistor on the TMS pin is enabled.
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6.4.6.4
Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI
is sampled on the rising edge of TCK and, depending on the current TAP state and the
current instruction, presents this data to the proper shift register chain. Because the TDI
pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on
TDI to change on the falling edge of TCK.
The internal pull-up resistor on the TDI pin is enabled.
6.4.6.5
Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR
ain or the DR
chains. The value of TDO depends on the current TAP state, the current instruction, and
the data in the chain being accessed. In order to save power when the port is not being
used, the TDO pin is placed in an inactive drive state when not act
vely shifting out data.
Because TDO can be connected to the TDI of another controller in a daisy-chain
configuration, the IEEE Standard 1149.1 expects the v
ue on TDO to change on the
falling edge of TCK.
6.4.6.6
Data register
According to the IEEE1149.1 standard, there
two types of data register defined:
bypass and boundary scan
The bypass register enable the possibility to bypass a device when part of the scan
path.Serial data is allowed to be t
ansferred through a device from the TDI pin to the TDO
pin without affecting the operation of the device.
The boundary scan register is the scan-chain of the boundary cells. The size of this
register is dependent on the command.
6.4.6.7
Boundary s
ell
The bou
y sc
n cell opens the possibility to control a hardware pin independent of its
normal us
case. Basically the cell can only do one of the following: control, output and
input.
IC1
IC2
Boundary scan cell
TDI
TDO
TDI
TDO
TAP
TAP
TCK
TMS
TCK
TMS
001aam306
Fig 24. Boundary scan cell path structure
6.4.6.8
Boundary scan path
This chapter shows the boundary scan path of the JSM66302.
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Table 28.
Boundary scan path of the JSM66302
Number (decimal)
Cell
Port
Function
Control
Bidir
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
BC_1
BC_8
BC_1
BC_8
BC_1
BC_8
BC_1
BC_8
BC_1
BC_8
BC_1
BC_8
BC_1
BC_8
BC_1
BC_8
BC_1
BC_4
BC_1
BC_8
BC_1
BC_8
BC_1
BC_8
–
CLKOUT
–
Control
Bidir
SCL2
–
Control
Bidir
SDA2
–
Con
Bidir
IFSEL0
–
Control
Bidir
IFSEL1
–
Control
Bidir
IF0
–
Control
Bidir
IF1
Control
Bidir
8
IF2
7
IF2
Output2
Bidir
6
IF3
5
–
Control
Bidir
4
IRQ
3
–
Control
Bidir
2
SIGIN
–
1
Control
Bidir
0
SIGOUT
Refer to th
JSM66302 BSDL file.
6.4.6.9
Boundary Scan Description Language (BSDL)
All of the boundary scan devices have a unique boundary structure which is necessary to
know for operating the device. Important components of this language are:
•
•
•
•
•
available test bus signal
compliance pins
command register
data register
boundary scan structure (number and types of the cells, their function and the
connection to the pins.)
The JSM66302 is using the cell BC_8 for the IO-Lines. The I
2
C Pin is using a BC_4 cell.
For all pad enable lines, the cell BC1 is used.
The manufacturer’s identification is 02Bh.
•
attribute IDCODEISTER of JSM66302: entity is “0001” and — version
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High performance multi-protocol NFC frontend
•
•
•
“0011110010000010b” and — part number (3C82h)
“00000010101b” and — manufacturer (02Bh)
“1b”; —
mandatory
The user code data is coded as followed:
•
•
product ID (3 bytes)
version
These four bytes are stored as the first four bytes in the EEPROM.
6.4.6.10
Non-IEEE1149.1 commands
Interface on/off:
With this command, the host/SAM interface can be deactivated and the
Read and Write command of the boundary scan interface is activated. (Data = 1). With
Update-DR, the value is taken over.
Register Access Read:
At Capture-DR, the actual ad
s is read and stored in the DR.
Shifting the DR is shifting in a new address. With Update-DR, this address is taken over
into the actual address.
Register Access Write:
At the Capture-DR, the address and the data is taken over from
the DR. The data is copied into the internal register at the given address.
6.5 Buffer
6.5.1
Overview
A 512
8-bit
O buffer is implemented in the JSM66302. It buffers the input and output
data stream b
en the host and the internal state machine of the JSM66302. Thus, it is
possible
andle data streams with lengths of up to 512 bytes without taking timing
constraints into account. The FIFO can also be limited to a size of 255 bytes. In this case
all the parameters (FIFO length, Watermark…) require a single byte only for definition. In
case of a 512 byte FIFO length, the definition of this value requires 2 bytes.
6.5.2
Accessing the FIFO buffer
When the
-Controller starts a command, the JSM66302 may, while the command is in
progress, access the FIFO-buffer according to that command. Physically only one
FIFO-buffer is implemented, which can be used in input and output direction. Therefore
the
-Controller has to take care, not to access the FIFO buffer in a way that corrupts the
FIFO data.
6.5.3
Controlling the FIFO buffer
Besides writing to and reading from the FIFO buffer, the FIFO-buffer pointers might be
reset by setting the bit FIFOFlush in FIFOControl to 1. Consequently, the FIFOLevel bits
are set to logic 0, the actually stored bytes are not accessible any more and the FIFO
buffer can be filled with another 512 bytes (or 255 bytes if the bit FIFOSize is set to 1)
again.
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6.5.4
Status Information about the FIFO buffer
The host may obtain the following data about the FIFO-buffers status:
•
•
•
•
Number of bytes already stored in the FIFO-buffer. Writing increments, reading
decrements the FIFO level: FIFOLength inregister FIFOLength (and FIFOControl
Register in 512 byte mode)
Warning, that the FIFO-buffer is almost full: HiAlert in register FIFOControl according
to the value of the water level in register WaterLevel (Register 02h bit [2], Register
03h bit[7:0])
Warning, that the FIFO-buffer is almost empty: LoAlert in register F
Control
according to the value of the water level in register WaterLevel (Regi
er 02h bit [2],
Register 03h bit[7:0])
FIFOOvl bit indicates, that bytes were written to the FIFO buffer although i
t
w
as
already full: ErrIRQ in register IRQ0.
WaterLevel is one single value defining both HiAlert (c
ting from the FIFO top) and
LoAlert (counting from the FIFO bottom). The JSM6630
can generate an interrupt
signal if:
•
•
LoAlertIRQEn in register IRQ0En is set to
ic 1 it will activate pin IRQ when LoAlert
in the register FIFOControl changes
o 1.
HiAlertIRQEN in register IRQ0En is set to logic 1 it will activate pin IRQ when HiAlert
in the register FIFOControl changes to 1.
The bit HiAlert is set to logic 1
maximum water level bytes (as set in register WaterLevel)
or less can be stored
n the
IFO-buffer. It is generated according to the following
equation:
HiAlert
=
F
Size
–
FiFoLength
WaterLevel
(2)
The bit L
ert is set to logic 1 if water level bytes (as set in register WaterLevel) or less
are actually stored in the FIFO-buffer. It is generated according to the following equation:
LoAlert
=
FIFOLength
WaterLevel
(3)
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6.6 Analog interface and contactless UART
6.6.1
General
The integrated contactless UART supports the external host online with framing and error
checking of the protocol requirements up to 848 kbit/s. An external circuit can be
connected to the communication interface pins SIGIN and SIGOUT to modulate and
demodulate the data.
The contactless UART handles the protocol requirements for the communication schemes
in co-operation with the host. The protocol handling itself generates bit- and byte-oriented
framing and handles error detection like Parity and CRC according to the different
contactless communication schemes.
The size, the tuning of the antenna, and the supply voltage of the output drivers have an
impact on the achievable field strength. The operating distance between reader and card
depends additionally on the type of card used.
6.6.2
TX transmitter
The signal delivered on pin TX1 and pin TX2 is the 13.56 MHz carrier modulated by an
envelope signal for energy and data transmissi
n. It can be used to drive an antenna
“Application information”
. The signal on TX1 and TX2 can be configured by the register
The modulation index can be set by the TxAmp.
Following figure shows the
neral relations during modulation
influenced by set_clk_mode
envelope
TX A
K100
(1)
TX ASK10
(2)
time
1: Defined by set_cw_amplitude.
2: Defined by set_residual_carrier.
001aan355
Fig 25. General dependences of modulation
Note: When changing the continuous carrier amplitude, the residual carrier amplitude also
changes, while the modulation index remains the same.
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High performance multi-protocol NFC frontend
transmission and the setting of the antenna driver to support the requirements at the
different specified modes and transfer speeds.
Table 29.
Settings for TX1 and TX2
TxClkMode
(binary)
Tx1 and TX2 output
Remarks
000
001
010
110
High impedance
–
0
output pulled to 0 in any case
output pulled to 1 in any case
1
RF high side push
open-drain, only high side (pu
MOS supplied
with clock, clock parity defined by invtx; low side
MOS is off
101
111
RF low side pull
open-drain, only low side (pull) MOS supplied
with clock, clock p
rity defined by invtx; high
side MOS
off
13.56 MHz clock derived
from 27.12 MHz quartz
divided by 2
push/pull
ration, clock polarity defined by
invtx
setting for 10 % modulation
Register TXamp and the bits for set_residual_
rrier define the modulation index:
Table 30.
Setting residual carrier and modulation index b
y
T
Xamp.set_residual_carrier
set_residual_carrier (decimal)
residual carrier [%]
modulation index [%]
0
99
98
96
94
91
89
87
86
85
84
83
82
81
80
79
78
77
76
75
74
72
70
68
0.5
1
1.0
2
2.0
3
3.1
4
4.7
5
5.8
6
7.0
7
7.5
8
8.1
9
8.7
10
11
12
13
14
15
16
17
18
19
20
21
22
9.3
9.9
10.5
11.1
11.7
12.4
13.0
13.6
14.3
14.9
16.3
17.6
19.0
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High performance multi-protocol NFC frontend
Table 30.
Setting residual carrier
…continued
and modulation index by
set_residual_carrier (decimal)
residual carrier [%]
modulation index [%]
23
24
25
26
27
28
29
30
31
65
60
55
50
45
40
35
30
25
21.2
25.0
29.0
33.3
37.9
42.9
48.1
53.8
60.0
Note: At VDD(TVDD) <5 V and residual carrier settings <50 %, the accuracy of the
modulation index may be low in dependency of the antenna tuning impedance
6.6.2.1
Overshoot protection
The JSM66302 provides an overshoot protection for 100 % ASK to avoid overshoots
during a PCD communication. Therefore two
rs overshoot_t1 and overshoot_t2 can
be used.
During the timer overshoot_t1 runs an amplitude defined by set_cw_amplitude bits is
provided to the output driver. Followed by an amplitude denoted by set_residual_carrier
bits with the duration of overshoot_t2.
7.0
(V)
5.0
3.0
1.0
-1.0
2.50
3.03
3.56
4.10
time (μs)
001aan356
Fig 26. Example 1: overshoot_t1 = 2d; overhoot_t2 = 5d.
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High performance multi-protocol NFC frontend
7.0
5.0
3.0
1.0
(V)
-1.0
0
1
2
3
4
5
time (μs)
001aan357
Fig 27. Example 2: overshoot_t1 = 0d; overhoot_t2 = 5d
6.6.2.2
Bit generator
The default coding of a data stream is done by using the Bit-Generator. It is activated
when the value of TxFrameCon.DCodeType is set to 0000 (bin). The Bit-Generator
encodes the data stream byte-wise and can apply the following encoding steps to each
data byte.
1.
Add a start-bit of specifi
d type at beginning of every byte
2.
Add a stop-bit and EGT bits of a specified type. The maximum number of EGT bit is 6,
only full bits are supported
3.
Add a pa
t of a specified type
4.
TxF
its (skips a given number of bits at the beginning of the first byte in
a
f
rame)
5.
TxLastBits (skips a given number of bits at the end of the last byte in a frame)
6.
Encrypt data-bit (MIFARE encryption)
TxFirstBits and TxLastBits can be used at the same time. If only a single data byte is sent,
t must be ensured that the range of TxFirstBits and TxLastBits do not overlap. It is not
possible to skip more than 8 bit of a single byte! ( (8 – TxFirstBits) + (8 – TxLastBits) )
<
8
By default, data bytes are always treated LSB first. To make use of an MSB first coding,
the TxMSBFirst in the register CLCON1 needs to be set.
6.6.3
Receiver circuitry
6.6.3.1
General
The JSM66302 features a versatile quadrature receiver architecture with fully
differential signal input at RXP and RXN. It can be configured to achieve optimum
performance for reception of various 13.56 MHz based protocols.
For all processing units various adjustments can be made to obtain optimum
performance.
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High performance multi-protocol NFC frontend
6.6.3.2
Block diagram
Figure 28
shows the block diagram of the receiver circuitry. The receiving process
includes several steps. First the quadrature demodulation of the carrier signal of
13.56 MHz is done. Several tuning steps in this circuit are possible.
fully/quasi-differential
rcv_hpcf<1:0>
rcv_gain<1:0>
rx_p
rx_n
mix_out_i_p
out_i_p
out_i_n
mixer
DATA
mix_out_i_n
2-stage BBA
clk_27 MHz
2-stage B
I-clks
rx_p
rx_n
13.56 MHz
I/O CLOCK
GENERATION
IMING
GENERATION
ADC
clk_27 MHz
Adc_data_ready
DATA
Q-clks
rx_p
rx_n
mix_out_q_p
mix_out_q_n
_q_p
out_q_n
mixer
rcv_gain<1:0>
rcv_hpcf<1:0>
fully/quasi-differential
001aan358
Fig 28. Block diagram of receiver circuitry
The receiver can also be operated in a single ended mode. In this case, the
Rcv_RX_single bit has to be
et. In the single ended mode, the two receiver pins RXP and
RXN need to be connected together and will provide a single ended signal to the receiver
circuitry.
When using
ceiver in a single ended mode, the receiver sensitivity is decreased and
the achie
ble
ing distance might be reduced, compared to the fully differential mode.
Table 31. Configuration for single or differential receiver
Mode
rcv_rx_single
pins RXP and RXN
Fully differential
0
provide differential signal from
differential antenna by separate
rx-coupling branches
Quasi differential
1
connect RXP and RXN together
and provide single ended signal
from antenna by a single
rx-coupling branch
The quadrature-demodulator uses two different clocks, Q-clock and I-clock, with a phase
shift of 90
between them. Both resulting baseband signals are amplified, filtered, digitized
and forwarded to a correlation circuitry.
The typical application is intended to implement the Fully differential mode and will deliver
maximum reader/writer distance. The Quasi differential mode can be used together with
dedicated antenna topologies that allow a reduction of matching components at the cost
of overall reading performance.
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High performance multi-protocol NFC frontend
During low-power card detection the DC levels at the I- and Q-channel mixer outputs are
evaluated. This requires that mixers are directly connected to the ADC. This can be
configured by setting the bit Rx_ADCmode in register Rcv (38h).
6.6.4
Active antenna concept
Two main blocks are implemented in the JSM66302. A digital circuitry, comprising state
machines, coder and decoder logic and an analog circuitry with the modulator and
antenna drivers, receiver and amplification circuitry. For example, the interface between
these two blocks can be configured in the way, that the interfacing signals may be routed
to the pins SIGIN and SIGOUT. The most important use of this topology is the active
antenna concept where the digital and the analog blocks are separated
s opens the
possibility to connect e.g. an additional digital block of another JSM66302 device with a
single analog antenna frontend.
SIGIN
SIGOUT
SIGIN
READER IC
(DIGITAL)
EADER IC
NTENNA)
SIGOUT
001aam307
Fig 29. Block diagram of the active Antenna c
pt
active antenna concept.
Table 32.
Register configuration of JSM66302 active antenna concep
t
(
DIGITAL)
Register
Valu
(b
nary)
Description
SigOut.SigOutSel
Rcv.SigInSel
010
TxEnvelope
10
11
Receive over SigIn (ISO/IEC14443A)
Receive over SigIn (Generic Code)
DrvCon.T
el
00
Low (idle)
Tabl
33. Register
configuration of JSM66302 active antenna concept (Antenna)
Register
Value (binary)
Description
SigOut.SigOutSel
0110
0111
Generic Code (Manchester)
Manchester with Subcarrier (ISO/IEC14443A)
Rcv.SigInSel
01
10
1
Internal
DrvCon.TxSel
RxCtrl.RxMultiple
External (SigIn)
RxMultiple on
The interface between these two blocks can be configured in the way, that the interfacing
This topology supports, that some parts of the analog part of the JSM66302 may be
connected to the digital part of another device.
The switch SigOutSel in registerSigOut can be used to measure signals. This is especially
important during the design-in phase or for test purposes to check the transmitted and
received data.
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High performance multi-protocol NFC frontend
However, the most important use of SIGIN/SIGOUT pins is the active antenna concept.
An external active antenna circuit can be connected to the digital circuit of the JSM66302.
SigOutSel has to be configured in that way that the signal of the internal Miller Coder is
sent to SIGOUT pin (SigOutSel = 4). SigInSel has to be configured to receive Manchester
signal with subcarrier from SIGIN pin (SigInSel = 1).
It is possible, to connect a passive antenna to pins TX1, TX2 and RX (via the appropriate
filter and matching circuit) and at the same time an active antenna to the pins SIGOUT
and SIGIN. In this configuration, two RF-parts may be driven (one after another) by a
single host processor.
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High performance multi-protocol NFC frontend
6.6.5
Symbol generator
The symbol generator is used to create various protocol symbols. These can be e.g. SOF
or EOF symbols as they are used by the ISO14443 protocols or proprietary protocol
symbols like the CS symbol as used by the ICODE EPC protocol.
Symbols are defined by means of the symbol definition registers and the mode registers.
Four different symbols can be used. Two of them, Symbol0 and Symbol1 have a
maximum pattern length of 16 bit and feature a burst length of up to 256 bits of either logic
“0” or logic “1”. The Symbol2 and Symbol3 are limited to 8-bit pattern length and do not
support a burst.
The definition of symbol patterns is done by writing the bit sequence of the pattern to the
appropriate register. The last bit of the pattern to be sent is located at the LSB of the
register. By setting the symbol length in the symbol-length register (TxSym10Len and
TxSym32Len), the definition of the symbol pattern is completed. All other bits at
bit-position higher than the symbol length in the definition register are ignored. (Example:
length of Symbol2 = 5, bit7 and bit6 are ignored, bit5 t
0 define the symbol pattern, bit5
is sent first)
Which symbol-pattern is sent can be configure
n the TxFrameCon register. Symbol0,
Symbol1 and Symbol2 can be sent before data
ckets, Symbol1, Symbol2 and Symbol3
can be sent after data packets. Each symbol
s defined by a set of registers. Symbols are
configured by a pair of registers. Symbol0 and Symbol1 share the same configuration and
Symbol2 and Symbol3 share the same configuration. The configuration includes setting of
bit-clock- and subcarrier-frequency, as well as selection of the pulse type/length and the
envelope type.
6.7 Memory
6.7.1
Memory ov
ew
The JSM
02 implements three different memories: EEPROM, FIFO and Registers.
At startup, the initialization of the registers which define the behavior of the IC is
performed by an automatic copy of an EEPROM area (read/write EEPROM section1 and
section2, register reset) into the registers. The behavior of the JSM66302 can be
changed by executing the command LoadProtocol, which copies a selected default
protocol from the EEPROM (read-only EEPROM section4, register Set Protocol area) into
the registers.
The read/write EEPROM section2 can be used to store any user data or predefined
register settings. These predefined settings can be copied with the command
“LoadRegister” into the internal registers.
The FIFO is used as Input/Out buffer and is able to improve the performance of a system
with limited interface speed.
第43页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.7.2
EEPROM memory organization
The JSM66302 has implemented a EEPROM non-volatile memory with a size of 8
kB.The EEPROM is organized in pages of 64 bytes. One page of 64 bytes can be
programmed at a time. Defined purposes had been assigned to specific memory areas
of the EEPROM, which are called Sections. Five sections 0..4 with different purpose do
exist.
Table 34.
EEPROM memory organization
Section
Page
Byte
addresses
Access Memory
content
rights
0
0
00 to 31
r
product information and
nfiguration
32 to 63
r/w
r/w
r/w
w
product confi
uration
register reset
1
2
3
4
1 to 2
64 to 191
3 to 95
192 to 6143
6144 to 7167
7168 to 8191
free
96 to 111
112 to 128
MIF
key
r
Register Set Protocol (RSP)
The following figure shows the structure of the EEPROM:
Section 0:
Sec
on 1:
Production and config
Register reset
Section 2:
Free
Section 3:
MIFARE key area (MKA)
RSP-Area for TX
Section 4_TX:
Section 4_RX:
RSP-Area for RX
001aan359
Fig 31. Sector arrangement of the EEPROM
第44页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.7.2.1
Product information and configuration – Page 0
The first EEPROM page includes production data as well as configuration information.
Table 35.
Production area (Page 0)
Address
(Hex.)
0
1
2
3
4
5
6
7
00
08
ProductID
Version
Unique Identifier
Unique Identifier
Manufacturer
Data
10
18
ManufacturerData
ManufacturerData
ProductID: Identifier for this JSM66302 product or derivative, only address 01h shall be
evaluated for identifying the Product JSM66302, address 00h and 02h shall be ignored
by software.
Please note, that the silicon version JSM66302, and d
atives can be identified on
register address 7Fh, it is not coded in the EEPROM production area.
Table 36.
Product ID overview of JSM66302 family
Address 01h
JSM66302
MFRC631
MFRC630
SLRC610
Product ID
01h
C0h
80h
20h
Version: This register indicates the version of the EEPROM initialization data during
production.
Unique I
tifier: Unique serial number code for this device
Manufacturer Data: This data is programmed during production. The content is not
intended to be used by any application and might not be constant for different devices.
Therefore the content needs to be considered to be undefined.
Table 37.
Co
figuration area (Page 0)
Address
(Hex.)
0
1
2
3
4
5
6
7
20
28
30
38
I
2
C_Address
Interface I
2
C SAM_Address
DefaultProtRx DefaultProtTx
–
–
TxCRCPreset
RxCRCPreset
–
–
–
–
–
–
–
I
2
C-Address:
Two possibilities exist to define the address of the I
2
C interface. This can be
done either by configuring the pins IF0, IF2 (address is then 10101xx, xx is defined by the
interface pins IF0, IF2) or by writing value into the I
2
C address area. The selection, which
of this 2-information pin configuration or EEPROM content – is used as I
2
C-address is
done at EEPROM address 21h (Interface, bit4)
Interface:
This section describes the interface byte configuration
第45页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 38.
Interface byte
Bit
7
6
5
4
3
2
1
0
I
2
C_HSP
r/w
–
–
I2C_Address
r/w
Boundary Scan
r/w
Host
–
access rights
RFU
RFU
–
–
Table 39.
Interface bits
Bit
Symbol
Description
7
I
2
C_HSP
when cleared, the high-speed mode is used
when set, the high speed+ mode is use
d
(
default)
6, 5
4
RFU
–
I
2
C_Address
when cleared, the pins are used (default)
when set, the EEPROM is used
3
Boundary
Scan
when cleared, the boundary scan interface is ON (default)
when set, the boundary scan is OFF
2 to 0
Host
000b – RS232
001b – I
2
C
010b – SPI
011b – I
2
CL
1xxb – pin selection
I
2
C_SAM_Address:
The I
2
C SAM Address is always defined by the EEPROM content.
The Register Set Protocol (RSP) Area contains settings for the TX registers (16 bytes)
and for the RX registers (8 b
es).
Table 40.
Tx and Rx arrangements in the register set protocol area
Section
Section 4 TX
Section 4
Section 4 Rx
Section 4 Rx
0
RX0
RX8
Tx1
TX2
Tx3
Tx5
TX6
TX7
RX6
RX14
RX1
RX9
RX2
RX10
RX3
RX4
RX12
RX5
RX7
RX11
RX13
RX15
TxCrcPreset:
The data bits are sent by the analog module and are automatically
extended by a CRC.
第46页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.7.3
EEPROM initialization content LoadProtocol
The JSM66302 EEPROM is initialized at production with values which are used to reset
certain registers of the JSM66302 to default settings by copying the EEPROM content to
the registers. Only registers or bits with “read/write” or “dynamic” access rights are
initialized with this default values copied from the EEPROM.
Note that the addresses used for copying reset values from EEPROM to registers are
dependent on the configured protocol and can be changed by the user.
Table 41.
Register reset values (Hex.) (Page0)
Address 0
(8)
1 (9)
2 (A)
3 (B)
Version
XX
4 (C)
5 (D)
6 (E)
7 (F)
Function Product
ID
Unique Identifier
00
Function Unique
Identifier
08 XX
XX
Factory trim values
XX
see table 34
XX
XX
XX
XX
XX
Factory trim
value
XX
XX
XX
XX
XX
XX
XX
XX
XX
X
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
Function TrimLFO
10 XX
XX
XX
XX
XX
Function Factory
trim values
18….
….38
XX
XX
Factory trim values
XX XX
The register reset values are configuration parameters used after startup of the IC. They
can be changed to modify the default behavior of the device. In addition to these register
reset values, i
the possibility to load settings for various users implemented
protocols.The
protocol command is used for this purpose.
Table 42.
Register reset values (
ex.)(Page1 and page 2)
Address 0
(8)
Command
40
1 (9)
2 (A)
3 (B)
4 (C)
5 (D)
6 (E)
IRQ0
00
7 (F)
IRQ1
00
HostCtrl
00
FiFoControl WaterLevel
FiFoLength FiFoData
40
80
05
00
00
IRQ0En
10
IRQ1En
00
Error
00
Status
00
RxBitCtrl
00
RxColl
00
TControl
00
T0Control
00
48
T0ReloadHi T0ReloadLo
T0Counter
ValHi
T0Counter
ValLo
T1Control
00
T1ReloadHi T1ReloadLo
T1Counter
ValHi
50
58
60
00
80
00
00
00
80
00
T1Counter
ValLo
T2Control
T2ReloadHi T2ReloadLo
T2Counter
ValHi
T2Counter
ValLo
T3Control
T3ReloadHi
00
00
00
80
00
00
00
00
T3ReloadLo T3Counter
ValHi
T3Counter
ValHi
T4Control
T4ReloadHi T4ReloadLo
T4Counter
ValHi
T4Counter
ValLo
80
00
00
00
00
80
00
00
第47页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 42.
Register reset values (Hex.)(Page1 and page 2)
…continued
Address 0
(8)
DrvMode
1 (9)
2 (A)
3 (B)
4 (C)
5 (D)
6 (E)
7 (F)
TxAmp
DrvCon
Txl
TxCRC
Preset
RxCRC
Preset
TxDataNum TxModWith
68
70
78
86
15
11
06
18
18
08
27
TxSym10
BurstLen
TxWaitCtrl
TxWaitLo
FrameCon
RxSofD
RxCtrl
RxWait
RxThres
hold
00
C0
12
CF
00
04
90
3F
Rcv
RxAna
RFU
SerialSpeed LFO_trimm
PLL_Ctrl
PLL_Di
LPCD_QMi
n
12
0A
00
7A
80
04
20
48
LPCD_
QMax
LPCD_IMin LPCD
_result_I
00
LPCD
_result_Q
PadEn
PadOut
PadIn
SigOut
80
88
12
88
00
00
00
00
00
TxBitMod
20
RFU
xx
TxDataCon TxDataMod TxSymFreq TxSym0H
TySym0L
00
TxSym1H
00
04
50
40
00
TxSym1L
0x00
TxSym2
0x00
TxSym3
TxSym10Le TxSym3
e TxSym32Bu TxSym10M
TxSym32M
ngth
n
th
rstCtrl
od
od
90
98
0x00
0x00
0x00
0x00
0x00
0x50
RxBitMod
0x02
RxEOFSym RxSyncValH
RxSyncValL RxSyncMod RxMod
0x00 0x00 0x
0x00 0x08
RXCorr
0x08
FabCal
0xB2
第48页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.8 Clock
generation
6.8.1
Crystal oscillator
The clock applied to the JSM66302 acts as time basis for generation of the carrier sent
out at TX and for the quadrature mixer I and Q clock generation as well as for the coder
and decoder of the synchronous system. Therefore stability of the clock frequency is an
important factor for proper performance. To obtain highest performance, clock jitter has to
be as small as possible. This is best achieved by using the internal oscillator buffer with
the recommended circuitry.
READER IC
XTAL1 XTAL2
27.12 MHz
001aam308
Fig 32. Crystal connection
Table 43.
Crystal requirements recommendations
Symbol
f
xtal
Parameter
Conditions
Min
–
Typ
27.12
–
max
–
Unit
MHz
ppm
crystal frequency
f
xtal
/f
xtal
relative crysta
250
+250
freque
cy variation
ESR
equivalent ser
es
resistance
–
50
100
C
L
d capacitance
–
–
10
50
–
pF
P
xtal
tal power
dissipation
100
W
6.8.2
IntegerN PLL clock line
The JSM66302 is able to provide a clock with configurable frequency at CLKOUT from
1 MHz to 24 MHz (PLL_Ctrl and PLL_DIV). There it can serve as a clock source to a
microcontroller which avoids the need of a second crystal oscillator in the reade
r
s
ystem.
Clock source for the IntegerN-PLL is the 27.12 MHz crystal oscillator.
Two dividers are determining the output frequency. First a feedback integer-N divider
configures the VCO frequency to be N
fin/2 (control signal pll_set_divfb). As supported
Feedback Divider Ratios are 23, 27 and 28, VCO frequencies can be
23
fin / 2 (312 MHz), 27
fin / 2 (366 MHz) and 28
fin / 2 (380 MHz).
The VCO frequency is divided by a factor which is defined by the output divider
shows the accuracy achieved for various frequencies (integer multiples of 1 MHz and
some typical RS232 frequencies) and the divider ratios to be used. The register bit
ClkOutEn enables the clock at CLKOUT pin.
The following formula can be used to calculate the output frequency:
第49页,共139页
JSM66302
High performance multi-protocol NFC frontend
f
out
= 13.56 MHz
PLLDiv_FB /PLLDiv_Out
Table 44.
Divider values for selected frequencies using the integerN PLL
Frequency [MHz]
PLLDiv_FB
4
6
8
10
28
38
12
23
26
20
28
19
24
23
16
1.8432 3.6864
23
78
27
61
23
39
28
28
PLLDiv_Out
206
103
0.01
accuracy [%]
0.04 0.03 0.04 0.08 0.04 0.08 0.04 0.01
6.8.3
Low Frequency Oscillator (LFO)
The Low-Frequency (LFO) is implemented to drive a wake-up counter (WUC). This wakes
up the system in regular time intervals and eases the design of a reader that is regularly
polling for card presence or implements a low-power card detection.
The LFO is trimmed during production to run at 16 kHz. Unless a high accuracy of the
LFO is required by the application and the device is o
ted in an environment with
changing ambient temperatures, trimming of the LFO is not required. For a typical
application making use of the LFO for wake-up from power down, the trim value set during
production can be used. Optional trimming to
ieve a higher accuracy of the 16 kHz
LFO clock is supported by a digital state machine which compares LFO-clock to a
reference clock. As reference clockfrequency the 13.56 MHz crystal clock is available.
第50页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.9 Power
management
6.9.1
Supply concept
The JSM66302 is supplied by V
DD
(Supply Voltage), PVDD (Pad Supply) and TVDD
(Transmitter Power Supply). These three voltages are independent from each other.
T
o
c
onnect the JSM66302 to a Microcontroller supplied by 3.3 V, PVDD and V
DD
shall be
at a level of 3.3 V, TVDD can be in a range from 3.3 V to 5.0 V. A higher supply voltage
at TVDD results in a higher field strength.
Independent of the voltage it is recommended to buffer these supplies
blocking
capacitances close to the terminals of the package. V
DD
and PVDD are recommended to
be blocked with a capacitor of 100 nF min, TVDD is recommended to be blocked with 2
capacitors, 100 nF parallel to 1.0
F
AVDD and DVDD are not supplied input pins. They are output pins and shall be
connected to blocking capacitors 470 nF each.
6.9.2
Power reduction mode
6.9.2.1
Power-down
A hard power-down is enabled with HIGH level on pin PDOWN. This turns off the internal
1.8 V voltage regulators for the analog and digital core supply as well as the oscillator. All
digital input buffers are separated from the input pads and clamped internally (except pin
PDOWN itself). The output pins are switched to high impedance. HardPowerDown is
performing a reset of the IC
ll registers will be reset, the Fifo will be cleared.
To leave the power-down mode the level at the pin PDOWN as to be set to LOW. This
starts the internal start-up sequence.
6.9.2.2
Standby mod
The stand
y mode is entered immediately after setting the bit PowerDown in the register
Command. All internal current sinks are switched off. Voltage references and voltage
regulators are set into standby mode.
In opposition to the power-down mode, the digital input buffers are not separated by the
nput pads and keep their functionality. The digital output pins do not change their state.
During standby mode, all registers values, the FIFO’s content and the configuration itself
keeps its current content.
To leave
the standby mode, the bit PowerDown in the register Command is cleared. This
triggers the internal start-up sequence. The reader IC is in full operation mode again when
the internal start-up sequence is finalized.
A value of 55h must be sent to the JSM66302 using the RS232 interface to leave the
standby mode. This is must at RS232, but cannot be used for the I
2
C/SPI interface. Then
read accesses shall be performed at address 00h until the device returns the content of
this address. The return of the content of address 00h indicates that the device is ready to
receive further commands and the internal start-up sequence is finalized.
第51页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.9.2.3
Modem off mode
When the ModemOff bit in the register Control is set the antenna transmitter and the
receiver are switched off.
To leave the modem off mode, clears the ModemOff bit in the register Control.
6.9.3
Low-Power Card Detection (LPCD)
The low-power card detection is an energy saving mode in which the JSM66302 is not fully
powered permanently.
The LPCD works in two phases. First the standby phase is controlled b
wake-up
counter (WUC), which defines the duration of the standby of the JSM66302. Second phase
is the detection-phase. In this phase, the values of the I and Q channel are detected and
stored in the register map. (LPCD_I_Result, LPCD_Q_Result).This time period can be
handled with Timer3. The value is compared with the min/max values in the registers
(LPCD_IMin, LPCD_IMax; LPCD_QMin, LPCD_QMax)
If it exceeds the limits, an
LPCDIRQ is raised.
After the command LPCD the standby of the JSM66302 is activated, if selected. The
wake-up Timer4 can activate the system afte
iven time. For the LPCD, it is
recommended to set T4AutoWakeUp and T4AutoRestart, to start the timer and then go to
standby. If a card is detected, the communication can be started. If T4AutoWakeUp is not
set, the IC will not enter Standby mode in case no card is detected.
6.9.4
Reset and start-up time
A 10
s constant high level
the PDOWN pin starts the internal reset procedure.
The following figure shows the internal voltage regulator:
V
DD
PVDD
AVDD
DVDD
1.8 V
GLITCH
FILTER
INTERNAL VOLTAGE
REGULATOR
PDown
1.8 V
V
SS
V
SS
001aan360
Fig 33. Internal PDown to voltage regulator logic
When the JSM66302 has finished, the reset phase and the oscillator has entered a stable
working condition the IC is ready to be used.
第52页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.10 Command set
6.10.1
General
The behavior is determined by a state machine capable to perform a certain set of
commands. By writing a command-code to the command register, the command is
executed.
Arguments and/or data necessary to process a command, are exchanged via the FIFO
buffer.
•
•
Each command that needs a certain number of arguments will star
cessin
g
o
nly
when it has received the correct number of arguments via the FIFO buffer.
The FIFO buffer is not cleared automatically at command start. It is recommended to
write the command arguments and/or the data bytes into the FIFO buffer and start the
command afterwards.
•
Each command may be stopped by the host by wr
g a new command code into the
command register e.g.: the Idle-Command.
6.10.2
Command set overview
Table 45.
Command set
Command
Idle
No.
00h
01h
02h
Parameter (bytes)
Short description
–
–
no action, cancels current command execution
low-power card detection
LPCD
LoadKey
(keybyte1),(keybyte2), (keyby
3),
(keybyte4), (keybyte5)
(keybyte6);
reads a MIFARE key (size of 6 bytes) from FIFO buffer
ant puts it into Key buffer
MFAuthent
AckReq
03h
60h or 61h, (block address), (card
serial number byte0),(card serial
number byte
rd serial number
byte2),(c
se
umber byte3);
performs the MIFARE standard authentication
04h
–
performs a query, an Ack and a Req-Rn for ISO/IEC
18000-3 mode 3/ EPC Class-1 HF
Receive
05h
06h
07
–
activates the receive circuit
Transmit
Transceive
bytes to send: byte1, byte2,….
bytes to send: byte1, byte2,….
transmits data from the FIFO buffer
transmits data from the FIFO buffer and automatically
activates the receiver after transmission finished
WriteE2
08h
09h
0Ah
0Ch
addressH, addressL, data;
gets one byte from FIFO buffer and writes it to the
internal EEPROM
WriteE2Page
ReadE2
(page Address), data0, [data1
..data63];
gets up to 64 bytes (one EEPROM page) from the FIFO
buffer and writes it to the EEPROM
addressH, address L, length;
reads data from the EEPROM and copies it into the
FIFO buffer
LoadReg
(EEPROM addressH), (EEPROM
addressL), RegAdr, (number of
Register to be copied);
reads data from the internal EEPROM and initializes the
JSM66302 registers. EEPROM address needs to be
within EEPROM sector 2
LoadProtocol
LoadKeyE2
0Dh
0Eh
(Protocol number RX), (Protocol
number TX);
reads data from the internal EEPROM and initializes the
JSM66302 registers needed for a Protocol change
KeyNr;
copies a key from the EEPROM into the key buffer
第53页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 45.
Command set
…continued
Command
No.
Parameter (bytes)
Short description
StoreKeyE2
0Fh
KeyNr, byte1,byte2, byte3, byte4,
byte5,byte6;
stores a MIFARE key (size of 6 bytes) into the EEPROM
ReadRNR
Soft Reset
1Ch
1Fh
–
Copies bytes from the Random Number generator into
the FIFO until the FiFo is full
–
resets the JSM66302
6.10.3
Command functionality
6.10.3.1
Idle command
Command (00h);
This command indicates that the JSM66302 is in idle mode. This command is also used
to terminate the actual command.
6.10.3.2
LPCD command
Command (01h);
This command performs a low-power card detection and/or an automatic trimming of the
LFO. After wake-up from standby, the values
e sampled I and Q channels are
compared with the min/max threshold va
ues in the registers. If it exceeds the limits, an
LPCD_IRQ will be raised. After the LPCD command the standby is activated, if selected.
6.10.3.3
Load key command
Command (02h), Parameter
key byte1),…, Parameter6 (key byte6);
Loads a MIFARE Key (6 by
es) for Authentication from the FIFO into the crypto-unit.
Abort condition: Less than 6 bytes written to the FIFO.
6.10.3.4
MFAuthe
co
and
Command (03h), Parameter1 (Authentication command code 60h or 61h), Parameter2
(block address), Parameter3 (card serial number byte0), Parameter4 (card serial number
byte1), Parameter5 (card serial number byte2), Parameter6 (card serial number byte3);
This command handles the MIFARE authentication in Reader/Writer mode to ensure a
secure communication to any MIFARE classic card.
When the MFAuthent command is active, any FIFO access is blocked. Anyhow if there is
access to the FIFO, the bit WrErr in the Error register is set.
This command terminates automatically when the MIFARE card is authenticated and the
bit MFCrypto1On is set to logic 1.
This command does not terminate automatically, when the card does not answer,
therefore the timer should be initialized to automatic mode. In this case, beside the bit
IdleIRQ the bit TimerIRQ can be used as termination criteria. During authentication
processing the bits RxIRQ and TxIRQ are blocked. The Crypto1On shows if the
authentication was successful. The Crypto1On is always valid.
In case, there is an error during authentication, the bit ProtocolErr in the Error register is
set to logic 1 and the bit Crypto 1 On in register Statu.
第54页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.10.3.5
AckReq command
Command (04h);
Performs a Query (Full command must be written into the FIFO); an Ack and a ReqRn
command. All answers to the command will be written into the FIFO. The error flag is
copied after the answer into the FIFO.
This command terminates automatically and the then active state is idle.
6.10.3.6
Receive command
Command (05h);
The JSM66302 activates the receiver path and waits for any data stream to be received,
according to its register settings. The registers must be set before
tarting this command
according to the used protocol and antenna configuration. The correct settings have to be
chosen before starting the command.
This command terminates automatically when the received data stream ends. This is
indicated either by the end of frame pattern or by the length byte depending on the
selected framing and speed.
Remark:
If the bit RxMultiple in the RxM
deReg register is set to logic 1, the Receive
command does not terminate automatically. It has to be terminated by activating any other
6.10.3.7
Transmit command
Command (06h); data to transmit
The content of the FIFO is transmitted immediately after starting the command. Before
transmitting t
IFO, all relevant registers have to be set to transmit data.
This com
nd terminates automatically when the FIFO gets empty. It can be terminated
by any oth
r command written to the command register.
6.10.3.8
Transceive command
Command (07h); data to transmit
This command transmits data from FIFO buffer and automatically activates the receiver
after a transmission is finished.
Each transmission process starts by writing the command into CommandReg.
Remark:
If the bit RxMultiple in register RxModeReg is set to logic 1, this command will
never leave the receiving state, because the receiving will not be cancelled automatically.
6.10.3.9
WriteE2 command
Command (08h), Parameter1 (addressH), Parameter2 (addressL), Parameter3 (data);
This command writes one byte into the EEPROM. If the FIFO contains no data, the
command will wait until the data is available.
Abort condition: Address-parameter outside of allowed range 0x00 – 0x7F.
第55页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.10.3.10
WriteE2PAGE command
Command (09h), Parameter1 (page address), Parameter2..63 (data0, data1…data63);
This command writes up to 64 bytes into the EEPROM. The addresses are not allowed to
wrap over a page border. If this is the case, this additional data be ignored and stays in the
fifo. The programming starts after 64 bytes are read from the FIFO or the FIFO is empty.
Abort condition: Insufficient parameters in FIFO; Page address parameter outside of
range 0x00 – 0x7F.
6.10.3.11
ReadE2 command
Command (0Ah), Parameter1 (addressH), Parameter2 (addressL), Par
er3 (length);
Reads up to 256 bytes from the EEPROM to the FIFO. If a read operation exceeds the
address 1FFFh, the read operation continues from address 0000h.
Abort condition: Insufficient parameter in FIFO; Address parameter outside of range.
6.10.3.12
LoadReg command
Command (0Ch), Parameter1 (EEPROM addressH),Parameter2 (EEPROM addressL),
Parameter3 (RegAdr), Parameter4 (number);
Read a defined number of bytes from the EEPROM and copies the value into the Register
set, beginning at the given address RegAdr.
Abort condition: Insufficient parameter in FIFO; Address parameter outside of range.
6.10.3.13
LoadProtocol command
Command (0Dh), Parameter1 (Protocol number RX), Parameter2 (Protocol number TX);
Reads out th
PROM Register Set Protocol Area and overwrites the content of the Rx-
and Tx- r
ted
sters. These registers are important for a Protocol selection.
Abo
t condition: Insufficient parameter in FIFO
Table 46.
Predefined protocol overview RX
[1]
Protocol
Number
decimal)
Protocol
Receiver speed
[kbits/s]
Receiver Coding
00
01
02
03
04
05
06
07
08
09
10
11
ISO/IEC14443 A
ISO/IEC14443 A
ISO/IEC14443 A
ISO/IEC14443 A
ISO/IEC14443 B
ISO/IEC14443 B
ISO/IEC14443 B
ISO/IEC14443 B
FeliCa
106
212
424
848
106
212
424
848
212
424
26
Manchester SubC
BPSK
BPSK
BPSK
BPSK
BPSK
BPSK
BPSK
Manchester
Manchester
SSC
FeliCa
ISO/IEC15693
ISO/IEC15693
52
SSC
第56页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 46.
Predefined protocol overview RX
[1]
Protocol
Number
(decimal)
Protocol
Receiver speed
[kbits/s]
Receiver Coding
12
13
14
ISO/IEC15693
EPC/UID
26
DSC
SSC
2/424
26
ISO/IEC 18000-3 mode 3/
EPC Class-1 HF
212
15
16
17
18
ISO/IEC 18000-3 mode 3/
EPC Class-1 HF
106
424
212
–
4/424
2/848
4/848
–
ISO/IEC 18000-3 mode 3/
EPC Class-1 HF
ISO/IEC 18000-3 mode 3/
EPC Class-1 HF
Jewel
Protocol
Number
(decimal)
Protocol
Transmitter speed
Transmitter Coding
[kbits/s]
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
ISO/IEC14443 A
ISO/IEC14443 A
ISO/IEC14
43 A
ISO/IEC14443 A
ISO/IEC14443 B
ISO/IEC14443 B
SO/IEC14443 B
ISO/IEC14443 B
FeliCa
106
212
424
848
106
212
424
848
212
424
26
Miller
Miller
Miller
Miller
NRZ
NRZ
NRZ
NRZ
Manchester
Manchester
1/4
FeliCa
ISO/IEC15693
ISO/IEC15693
ISO/IEC15693
EPC/UID
26
1/4
1,66
53
1/256
Unitray
ISO/IEC 18000-3 mode 3/
EPC Class-1 HF
–
based on Tari value,
ASK, PIE
15
16
17
18
ISO/IEC 18000-3 mode 3/
EPC Class-1 HF
–
–
–
–
based on Tari value,
ASK, PIE
ISO/IEC 18000-3 mode 3/
EPC Class-1 HF
based on Tari value,
ASK, PIE
ISO/IEC 18000-3 mode 3/
EPC Class-1 HF
based on Tari value,
ASK, PIE
Jewel
–
第57页,共139页
JSM66302
High performance multi-protocol NFC frontend
6.10.3.14
LoadKeyE2 command
Command (0Eh), Parameter1 (key number);
Loads a MIFARE key for authentication from the EEPROM into the crypto 1 unit.
Abort condition: Insufficient parameter in FIFO; KeyNr is outside the MIFARE key area.
6.10.3.15
StoreKeyE2 command
Command (0Fh), Parameter1 (KeyNr), Parameter2(keybyte1), Parameter3(keybyte2),
Parameter4(keybyte3), Parameter5(keybyte4), Parameter6(keybyte5), P
rameter7
(keybyte6);
Stores MIFARE Keys into the EEPROM. The key number parameter indicates the first key
(n) in the MKA that will be written. If more than one MIFARE Key is available in the FIFO
then the next key (n+1) will be written until the FIFO is empty. If an incomplete key (less
than 6 bytes) is written into the FIFO, this key will be ig
ored and will remain in th
e
F
IFO.
Abort condition: Insufficient parameter in FIFO; KeyNr is outside the MKA;
6.10.3.16
GetRNR command
Command (1Ch);
This command is reading Random Numbers from the random number generator of the
JSM66302. The Random Numbe
s are copied to the FIFO until the FIFO is full.
6.10.3.17
SoftReset command
Command (1Fh);
This comman
s performing a soft reset. Triggered by this command all the default values
for the registe
ng will be read from the EEPROM and copied into the register set.
第58页,共139页
JSM66302
High performance multi-protocol NFC frontend
1.
JSM66302 registers
1.1
Register bit behavior
Depending on the functionality of a register, the access conditions to the register can vary.
In principle, bits with same behavior are grouped in common registers. The access
Table 48.
Behavior of register bits and their designation
Abbreviation Behavior
Description
r/w
dy
r
read and write
These bits can be written and read via the host
erface. Since
they are used only for control purposes, the co
t is not
influenced by the state machines but can be read by internal state
machines.
dynamic
These bits can be written and read v
a the host interface. They
can also be written automatically by internal state machines, for
example Command register changes its value automatically after
the execution of the comm
read only
These register bits indicate hold values which are determined by
internal states only.
w
write only
–
Reading these re
bits always returns zero.
RFU
These bits a
e reserved for future use and must not be changed.
In case of a required write access, it is recommended to write a
logic 0.
Table 49.
JSM66302 registers overview
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
Register name
Command
HostCtrl
Function
Starts
nd stops command execution
Host control register
FIFOControl
WaterLevel
FIFOLength
FIFOData
IRQ0
Control register of the FIFO
Level of the FIFO underflow and overflow warning
Length of the FIFO
Data In/Out exchange register of FIFO buffer
Interrupt register 0
IRQ
Interrupt register 1
RQ0En
Interrupt enable register 0
IRQ1En
Interrupt enable register 1
E
ror
Error bits showing the error status of the last command execution
Contains status of the communication
Control register for anticollision adjustments for bit oriented protocols
Collision position register
Status
RxBitCtrl
RxColl
TControl
Control of Timer 0..3
T0Control
T0ReloadHi
T0ReloadLo
T0CounterValHi
T0CounterValLo
Control of Timer0
High register of the reload value of Timer0
Low register of the reload value of Timer0
Counter value high register of Timer0
Counter value low register of Timer0
第59页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 49.
JSM66302 registers overview
…continued
Address
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
Register name
T1Control
Function
Control of Timer1
T1ReloadHi
T1ReloadLo
T1CounterValHi
T1CounterValLo
T2Control
High register of the reload value of Timer1
Low register of the reload value of Timer1
Counter value high register of Timer1
Counter value low register of Timer1
Control of Timer2
T2ReloadHi
T2ReloadLo
T2CounterValHi
T2CounterValLo
T3Control
High byte of the reload value of Timer2
Low byte of the reload value of Timer2
Counter value high byte of Timer2
Counter value low byte of Timer2
Control of Timer3
T3ReloadHi
T3ReloadLo
T3CounterValHi
T3CounterValLo
T4Control
High byte of the reload value of Timer3
Low byte of the reload value of Time
Counter value high byte of Timer3
Counter value low byte of T
er3
Control of Timer4
T4ReloadHi
T4ReloadLo
T4CounterValHi
T4CounterValLo
DrvMod
High byte of the reload value of Timer4
Low byte of the reload value of Timer4
Counter value high byte of Timer4
Counter
alue low byte of Timer4
Driver mode register
TxAmp
Transmitter amplifier register
Driver configuration register
Transmitter register
DrvCon
Txl
TxCrcPreset
RxCrcPreset
TxDataNum
TxModWidth
TxS
m10BurstLen
TXWaitCtrl
TxWaitLo
Transmitter CRC control register, preset value
Receiver CRC control register, preset value
Transmitter data number register
Transmitter modulation width register
Transmitter symbol 1 + symbol 0 burst length register
Transmitter wait control
Transmitter wait low
FrameCon
RxSofD
Transmitter frame control
Receiver start of frame detection
Receiver control register
RxCtrl
RxWait
Receiver wait register
RxThreshold
Rcv
Receiver threshold register
Receiver register
RxAna
Receiver analog register
RFU
No function implemented
3Bh
SerialSpeed
Serial speed register
第60页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 49.
JSM66302 registers overview
…continued
Address
3Ch
3Dh
3Eh
3Fh
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
7Fh
Register name
LFO_Trimm
PLL_Ctrl
Function
Low-power oscillator trimming register
IntegerN PLL control register, for microcontroller clock output adjustment
IntegerN PLL control register, for microcontroller clock output adjustment
Low-power card detection Q channel minimum threshold
Low-power card detection Q channel maximum threshold
Low-power card detection I channel minimum threshold
Low-power card detection I channel result register
Low-power card detection Q channel result register
PIN enable register
PLL_DivOut
LPCD_QMin
LPCD_QMax
LPCD_IMin
LPCD_I_Result
LPCD_Q_Result
PadEn
PadOut
PIN out register
PadIn
PIN in register
SigOut
Enables and controls the SIGOUT Pi
Transmitter bit mode register
TxBitMod
RFU
–
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
Transmitter data configura
egister
Transmitter data modulation register
Transmitter symbol frequency
Transmitter symbol 0 high register
Transmitter symbol 0 low register
TxSym1H
TxSym1L
Transm
er symbol 1 high register
Transmitter symbol 1 low register
TxSym2
Transmitter symbol 2 register
TxSym3
Transmitter symbol 3 register
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym
2Mod
RxBitMo
Transmitter symbol 1 + symbol 0 length register
Transmitter symbol 3 + symbol 2 length register
Transmitter symbol 1 + symbol 0 burst control register
Transmitter symbol 1 + symbol 0 modulation register
Transmitter symbol 3 + symbol 2 modulation register
Receiver bit modulation register
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
Receiver end of frame symbol register
Receiver synchronisation value high register
Receiver synchronisation value low register
Receiver synchronisation mode register
Receiver modulation register
RxCorr
Receiver correlation register
FabCal
Calibration register of the receiver, calibration performed at production
Version and subversion register
Version
第61页,共139页
JSM66302
High performance multi-protocol NFC frontend
1.2
Command configuration
1.2.1
Command
Starts and stops command execution.
Table 50.
Command register (address 00h)
Bit
7
6
5
4
3
2
1
0
Symbol Standby
Modem
Off
RFU
Command
Access
rights
dy
r/w
–
dy
Table 51.
Command bits
Bit
Symbol
Standby
ModemOff
RFU
Description
7
Set to 1, the IC is entering power-down mode.
6
Set to logic 1, the receiver and
ansmitter circuit is powering down.
5
–
4 to 0
Command
Defines the actual command for the JSM66302.
1.3
SAM configuration register
1.3.1
HostCtrl
Via the HostCtrl Register the interface access right can be controlled
Table 52.
HostCtrl register (address 01h);
Bit
7
RegEn
dy
6
5
4
RFU
–
3
SAMInterface
r/w
2
SAMInterface
r/w
1
RFU
–
0
RFU
–
Symbol
BusHost
r/w
BusSAM
r/w
Access
rights
Table 53.
HostCtrl bits
Bit
Symbol
Description
7
RegEn
If this bit is set to logic 1, the register HostCtrl_reg can be changed at
the next register access. The next write access clears this bit
automatically.
6
5
BusHost
BusSAM
RFU
Set to logic 1, the bus is controlled by the host. This bit cannot be set
together with the bit BusSAM. This bit can only be set if the bit RegEn
is previously set.
Set to logic 1, the bus is controlled by the SAM. This bit cannot be set
together with BusHost. This bit can only be set if the bit RegEn is
previously set.
4
–
3 to 2
SAMInterface 0h:SAM
Interface switched off
1h:SAM Interface SPI active
2h:SAM Interface I
2
CL active
3h:SAM Interface I
2
C active
1 to 0
RFU
–
第62页,共139页
JSM66302
High performance multi-protocol NFC frontend
1.4
FIFO configuration register
1.4.1
FIFOControl
FIFOControl defines the characteristics of the FIFO
Table 54.
FIFOControl register (address 02h);
Bit
7
6
5
4
3
2
1
0
Symbol
FIFOSize
HiAlert
LoAlert
FIFOFlush
RFU
WaterLevel
ExtBit
FIFOLengthExtBits
Access
rights
r/w
r
r
w
–
r/w
r
Table 55.
FIFOControl bits
Bit
Symbol
Description
7
FIFOSize
Set to logic 1, FIFO size is 25
bytes;
Set to logic 0, FIFO size is 5
ytes.
It is recommended to change the FIFO size only, when the FIFO
content had been cleared.
6
5
4
HiAlert
Set to logic 1, whe
number of bytes stored in the FIFO buffer
fulfils the following equation:
HiAlert = (FIFOSize – FIFOLength) <= WaterLevel
LoAlert
Set to logic 1, when the number of bytes stored in the FIFO buffer
fulfils
he following conditions:
Alert =1 if FIFOLength <= WaterLevel
FIFOFlush
Set to logic 1 clears the FIFO buffer. Reading this bit will always
return 0
3
2
RFU
–
Wate
lExtBit
Defines the bit 8 (MSB) for the waterlevel (extension of register
WaterLevel). This bit is only evaluated in the 512-byte FIFO mode.
Bits 7..0 are defined in register WaterLevel.
1 to 0
FIFOLengthExtBits Defines
the bit9 (MSB) and bit8 for the FIFO length (extension of
FIFOLength). These two bits are only evaluated in the 512-byte
FIFO mode. The bits 7..0 are defined in register FIFOLength.
1.4.2
WaterLevel
Defines the level for FIFO under- and overflow warning levels.This register is extended by
1 bit in FIFOControl in case the 512-byte FIFO mode is activated by setting bit
FIFOControl.FIFOSize.
Table 56.
WaterLevel register (address 03h);
Bit
7
6
5
4
3
2
1
0
Symbol
WaterLevelBits
r/w r/w
Access
rights
r/w
r/w
r/w
r/w
r/w
r/w
第63页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 57.
WaterLevel bits
Bit
Symbol
Description
7 to 0
WaterLevelBits
Sets a level to indicate a FIFO-buffer state which can be read from
bits HighAlert and LowAlert in the FifoControl. In 512-byte FIFO
mode, the register is extended by bit WaterLevelExtBit in the
FIFOControl. This functionality can be used to avoid a FIFO buffer
overflow or underflow:
The bit HiAlert bit in FIFO Control is read logic 1, if the number of
bytes in the FIFO-buffer is equal or less than the number defined by
the waterlevel configuration.
The bit LoAlert bit in FIFO control is read logic 1,
number of
bytes in the FIFO buffer is equal or less than the number defined by
the waterlevel configuration.
Note: For the calculation of HiAlert and
oAlert, see register
第64页,共139页
JSM66302
High performance multi-protocol NFC frontend
1.4.3
FIFOLength
Number of bytes in the FIFO buffer. In 512-byte mode, this register is extended by
FIFOControl.FifoLength.
Table 58.
FIFOLength register (address 04h); reset value: 00h
Bit
7
6
5
4
3
2
1
0
Symbol
FIFOLength
dy
Access
rights
Table 59.
FIFOLength bits
Bit
Symbol
Description
7 to 0
FIFOLength
Indicates the number of bytes in the FIFO buffer. In 512-byte mode this
register is extended by the bits FIFOLen
th in the FIFOControl
register. Writing to the FIFOData
egister increments, reading
decrements the number of avai
bytes in the FIFO.
1.4.4
FIFOData
In- and output of FIFO buffer. Contrary to any r
d/write access to other addresses,
reading or writing to the FIFO address does not increment the address pointer. Writing to
the FIFOData register increments, reading decrements the number of bytes present in the
FIFO.
Table 60.
FIFOData register (address 05h);
Bit
7
6
5
4
3
2
1
0
Symbol
FIFOData
Access
rights
dy
dy
dy
dy
dy
dy
dy
dy
Table 61.
FIFOData bits
Bit
Symbol
Description
7 to 0
FIFOData
1.5
Interrupt configuration registers
The Registers IRQ0 register and IRQ1 register implement a special functionality to avoid
the unintended modification of bits.
The mechanism of changing register contents requires the following consideration:
IRQ(x).Set indicates, if a set bit on position 0 to 6 shall be cleared or set. Depending on
the content of IRQ(x).Set, a write of a 1 to positions 0 to 6 either clears or sets the
corresponding bit. With this register, the application can modify the interrupt status which
is maintained by the JSM66302.
Bit 7 indicates, if the intended modification is a setting or clearance of a bit. Any 1 written
to a bit position 6…0 will trigger the setting or clearance of this bit as defined by bit 7.
Example: writing FFh sets all bits 6..0, writing 7Fh clears all bits 6..0 of the interrupt
request register
第65页,共139页
JSM66302
High performance multi-protocol NFC frontend
1.5.1
IRQ0 register
Interrupt request register 0.
Table 62.
IRQ0 register (address 06h); reset value: 00h
Bit
7
6
5
4
3
2
1
0
Symbol
Set
Hi AlertIRQ
Lo
AlertIRQ
IdleIRQ
TxIRQ
RxIRQ
ErrIRQ
RxSOF
IRQ
Access
rights
w
dy
dy
dy
dy
dy
dy
dy
Table 63.
IRQ0 bits
Bit
Symbol
Description
7
Set
1: writing a 1 to a bit position 6..0 sets the interrupt request
0: Writing a 1 to a bit position 6..0 clears the interrupt request
6
5
4
HiAlerIRQ Set,
when bit HiAlert in register Statu
eg is set. In opposition to HiAlert,
HiAlertIRQ stores this event.
LoAlertIRQ Set,
when bit LoAlert in register Status1 is set. In opposition to LoAlert,
LoAlertIRQ stores this event
IdleIRQ
Set, when a command terminates by itself e.g. when the Command changes
its value from any command to the Idle command. If an unknown command
is started, the Command changes its content to the idle state and the bit
IdleIRQ is set. Starting the Idle command by the Controller does not set bit
IdleIRQ.
3
2
TxIRQ
RxIRQ
Set, when
ata transmission is completed, which is immediately after the last
bit is sen
Set, when the receiver detects the end of a data stream.
Note: This flag is no indication that the received data stream is correct. The
error flags have to be evaluated to get the status of the reception.
1
0
E
IRQ
Set, when the one of the following errors is set:
FifoWrErr, FiFoOvl, ProtErr, NoDataErr, IntegErr.
RxSOFlrq Set,
when a SOF or a subcarrier is detected.
1.5.2
IRQ1 register
Interrupt request register 1.
Table 64.
IRQ1 register (address 07h)
Bit
7
Set
w
6
5
4
3
2
Timer2IRQ
dy
1
0
Symbol
GlobalIRQ LPCD_IRQ Timer4IRQ
Timer3IRQ
dy dy dy
dy
Timer1IRQ Timer0IRQ
Access
rights
dy
dy
第66页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 65.
IRQ1 bits
Bit
Symbol
Description
7
Set
1: writing a 1 to a bit position 5..0 sets the interrupt request
0: Writing a 1 to a bit position 5..0 clears the interrupt request
6
5
4
3
2
1
0
GlobalIRQ Set,
if an enabled IRQ occurs.
LPCD_IRQ Set
if a card is detected in Low-power card detection sequence.
Timer4IRQ Set
to logic 1 when Timer4 has an underflow.
Timer3IRQ Set
to logic 1 when Timer3 has an underflow.
Timer2IRQ Set
to logic 1 when Timer2 has an underflow.
Timer1IRQ Set
to logic 1 when Timer1 has an underflow.
Timer0IRQ Set
to logic 1 when Timer0 has an underflow.
1.5.3
IRQ0En register
Interrupt request enable register for IRQ0. This register
llows defining if an interrupt
request is processed by the JSM66302.
Table 66.
IRQ0En register (address 08h)
Bit
7
6
5
4
3
2
1
0
Symbol
IRQ_Inv Hi
AlertIRQEn LoAlertIRQEn
IdleIRQEn
TxIRQEn
RxIRQEn ErrIRQEn
RxSOFIRQE
n
Access
rights
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Table 67.
IRQ0En bit
Bit
7
Symbol
Description
IRQ_
Set to one the signal of the IRQ pin is inverted
6
Hi Aler
n Set
to logic 1, it allows the High Alert interrupt Request (indicated by the
bit HiAlertIRQ) to be propagated to the GlobalIRQ
5
4
3
2
1
0
Lo AlertIRQEn
Set to logic 1, it allows the Low Alert Interrupt Request (indicated by the
bit LoAlertIRQ) to be propagated to the GlobalIRQ
IdleIRQEn
TxIRQEn
RxIRQEn
ErrIRQEn
Set to logic 1, it allows the Idle interrupt request (indicated by the bit
IdleIRQ) to be propagated to the GlobalIRQ
Set to logic 1, it allows the transmitter interrupt request (indicated by the
bit TxtIRQ) to be propagated to the GlobalIRQ
Set to logic 1, it allows the receiver interrupt request (indicated by the bit
RxIRQ) to be propagated to the GlobalIRQ
Set to logic 1, it allows the Error interrupt request (indicated by the bit
ErrorIRQ) to be propagated to the GlobalIRQ
RxSOFIRQEn Set
to logic 1, it allows the RxSOF interrupt request (indicated by the bit
RxSOFIRQ) to be propagated to the GlobalIRQ
第67页,共139页
JSM66302
High performance multi-protocol NFC frontend
1.5.4
IRQ1En
Interrupt request enable register for IRQ1.
Table 68.
IRQ1EN register (address 09h);
Bit
Symbol IRQPushPull
IRQPinEn LPCD_IRQE
Timer4IRQE Timer3IRQE Timer2IRQE
Timer1IRQE Timer0IRQE
7
6
5
4
3
2
1
0
n
n
n
n
n
n
Access
rights
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Table 69.
IRQ1EN bits
Bit
Symbol
Description
7
IRQPushPull
Set to 1 the IRQ-pin acts as PushPull pin, otherwise it acts as
OpenDrain pin
6
5
4
3
2
1
0
IRQPinEN
Set to logic 1, it allows the global i
errupt request (indicated by the bit
GlobalIRQ) to be propagated to t
terrupt pin
LPCD_IRQEN
Timer4IRQEn
Timer3IRQEn
Timer2IRQEn
Timer1IRQEn
Timer0IRQEn
Set to logic 1, it allows the LPCDinterrupt request (indicated by the bit
LPCDIRQ) to be propag
ed to the GlobalIRQ
Set to logic 1, it allows t
imer4 interrupt request (indicated by the bit
Timer4IRQ) to be propagated to the GlobalIRQ
Set to logic 1, it allows the Timer3 interrupt request (indicated by the bit
Timer3IRQ) to be propagated to the GlobalIRQ
Set to logic 1, it allows the Timer2 interrupt request (indicated by the bit
Time
IRQ) to be propagated to the GlobalIRQ
Set to logic 1, it allows the Timer1 interrupt request (indicated by the bit
Timer1IRQ) to be propagated to the GlobalIRQ
Set to logic 1, it allows the Timer0 interrupt request (indicated by the bit
Timer0IRQ) to be propagated to the GlobalIRQ
第68页,共139页
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High performance multi-protocol NFC frontend
1.6
Contactless interface configuration registers
1.6.1
Error
Error register.
Table 70.
Error register (address 0Ah)
Bit
7
EE_Err
dy
6
FiFoWrErr
dy
5
FIFOOvl
dy
4
MinFrameErr
dy
3
NoDataErr
dy
2
1
0
IntegErr
dy
Symbol
CollDet
dy
ProtErr
dy
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Table 71.
Error bits
Bit
Symbol
Description
7
EE_Err
An error appeared during the last EEPROM command. For
details see the descriptions of the EEP
commands
6
FIFOWrErr Data
was written into the FIFO, during a transmission of a possible CRC,
during “RxWait”, “Wait for data” or “Receiving” state, or during an
authentication command. The
g is cleared when a new CL command is
started. If RxMultiple is active
flag is cleared after the error flags have
been written to the FIFO
5
4
FIFOOvl
Data is written into the FIFO when it is already full. The data that is already in
the FIFO remains untouched. All data that is written to the FIFO after this Flag
is set to 1 will be ignored.
Min
A valid SO
was received, but afterwards less than 4 bits of data were
FrameErr received.
Note: Frames with less than 4 bits of data are automatically discarded and the
RxDecoder stays enabled. Furthermore no RxIRQ is set. The same is valid for
less than 3 bytes, if the EMD suppression is activated
Note: MinFrameErr is automatically cleared at the start of a receive or
transceive command. In case of a transceive command, it is cleared at the
start of the receiving phase (“Wait for data” state)
3
NoDataErr Data
should be sent, but no data is in FIFO
第69页,共139页
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High performance multi-protocol NFC frontend
Table 71.
Error bits
Bit
Symbol
Description
2
CollDet
A collision has occurred. The position of the first collision is shown in the
register RxColl.
Note: CollDet is automatically cleared at the start of a receive or transceive
command. In case of a transceive command, it is cleared at the start of the
receiving phase (“Wait for data” state).
Note: If a collision is part of the defined EOF symbol, CollDet is not set to 1.
1
ProtErr
A protocol error has occurred. A protocol error can be a wrong stop bit, a
missing or wrong ISO/IEC14443B EOF or SOF or a wrong number of
received data bytes. When a protocol error is detected, dat
eception is
stopped.
Note: ProtErr is automatically cleared at start of a receive or transceive
command. In case of a transceive command, it is cleared at the start of the
receiving phase (“Wait for data” state).
Note: When a protocol error occurs the last received data byte is not written
into the FIFO.
0
IntegErr
A data integrity error has been detecte
ssible cause can be a wrong
parity or a wrong CRC. In case of a data integrity error the reception is
continued.
Note: IntegErr is automaticall
ared at start of a Receive or Transceive
command. In case of a Transceive command, it is cleared at the start of the
receiving phase (“Wait for data” state).
Note: If the NoColl bit is set, also a collision is setting the IntegErr.
1.6.2
Status
Status register.
Table 72.
Status register (address 0Bh)
Bit
7
–
6
–
5
pto1On
dy
4
–
3
–
2
1
0
Symbol
ComState
r
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RFU
Table 73.
Status bits
Bit
7 to 6
5
Symbol
Description
–
RFU
Crypto1On Indicates
if the MIFARE Crypto is on. Clearing this bit is switching the
MIFARE Crypto off. The bit can only be set by the MFAuthent command.
4 to3
–
RFU
2 to 0
ComState ComState
shows the status of the transmitter and receiver state machine:
000b … Idle
001b … TxWait
011b … Transmitting
101b … RxWait
110b … Wait for data
111b … Receiving
100b … not used
第70页,共139页
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High performance multi-protocol NFC frontend
1.6.3
RxBitCtrl
Receiver control register.
Table 74.
RxBitCtrl register (address 0Ch);
Bit
7
ValuesAfterColl
r/w
6
5
4
3
2
1
RxLastBits
w
0
Symbol
RxAlign
r/w
NoColl
r/w
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r/w
r/w
w
w
Table 75.
RxBitCtrl bits
Bit
Symbol
Description
7
ValuesAfter If
cleared, every received bit after a collision is replaced by a zero. This
Coll
function is needed for ISO/IEC14443 anticollision
6 to 4
RxAlign
Used for reception of bit oriented frames: R
Align defines the bit position
length for the first bit received to be
ored. Further received bits are
stored at the following bit positions
Example:
RxAlign = 0h – the LSB of
received bit is stored at bit 0, the second
received bit is stored at b
sition 1.
RxAlign = 1h – the LSB o
the received bit is stored at bit 1, the second
received bit is stored at bit position 2.
RxAlign = 7h – the LSB of the received bit is stored at bit 7, the second
received bit is stored in the following byte at position 0.
Note:
RxAlign = 0, data is received byte-oriented, otherwise
bit-ori
nted.
3
NoColl
If this bit is set, a collision will result in an IntegErr
2 to 0
RxLastBits
Defines the number of valid bits of the last data byte received in
bit-oriented communications. If zero the whole byte is valid.
Note: These bits are set by the RxDecoder in a bit-oriented
communication at the end of the communication. They are reset at start
of reception.
第71页,共139页
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High performance multi-protocol NFC frontend
1.6.4
RxColl
Receiver collision register.
Table 76.
RxColl register (address 0Dh);
Bit
7
6
5
4
3
2
1
0
Symbol
CollPosValid
r
CollPos
r
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Table 77.
RxColl bits
Bit
Symbol
Description
7
CollPos
Valid
If set to 1, the value of CollPos is valid. Otherwise no collision is detected or
the position of the collision is out of the range of bits CollPos.
6 to 0
CollPos
These bits show the bit position of the first detected collision in a received
frame (only data bits are interpreted).
llPos can only be displayed for the
first 8 bytes of a data stream.
Example:
00h indicates a bit collision i
e 1st bit
01h indicates a bit collision in the 2nd bit
08h indicates a bit collision in the 9th bit (1st bit of 2nd byte)
3Fh indicates a bit collision in the 64th bit (8th bit of the 8th byte)
These bits sha
l only be interpreted in Passive communication mode at 106
kbit/s or ISO/IEC 14443A/MIFARE reader /writer mode or
ISO/IEC
693/ICODE SLI read/write mode if bit CollPosValid is set.
Note: If RxBitCtrl.RxAlign is set to a value different to 0, this value is included
in the CollPos.
Example: RxAlign = 4h, a collision occurs in the 4th received bit (which is the
last bit of that UID byte). The CollPos = 7h in this case.
第72页,共139页
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High performance multi-protocol NFC frontend
1.7
Timer configuration registers
1.7.1
TControl
Control register of the timer section.
The TControl implements a special functionality to avoid the not intended modification of
bits.
Bit 3..0 indicates, which bits in the positions 7..4 are intended to be modified. Example:
writing FFh sets all bits 7..4, writing F0h does not change any of the bits
Table 78.
TControl register (address 0Eh)
Bit
7
6
5
4
3
2
1
0
Symbol
T3Running T2Running
T1Running T0Running
T3Start
art
T1Start
T0Start
StopNow
St
Now
StopNow
StopNow
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dy
dy
dy
dy
w
w
w
w
Table 79.
TControl bits
Bit
Symbol
Description
7
T3Running
Indicates Timer3 is running.If the bit T3startStopNow is set/reset, this
bit and the timer can be started/stopped
6
5
4
3
2
1
0
T2Running
T1Running
T0R
g
Ind
ates Timer2 is running. If the bit T2startStopNow is set/reset, this
bit and the timer can be started/stopped
Indicates tTmer1 is running. If the bit T1startStopNow is set/reset, this
bit and the timer can be started/stopped
Indicates Timer0 is running. If the bit T0startStopNow is set/reset, this
bit and the timer can be started/stopped
T3StartStop
Now
The bit 7 of TControl T3Running can be modified if set
The bit 6of TControl T2Running can be modified if set
The bit 5of TControl T1Running can be modified if set
The bit 4 of TControl T0Running can be modified if set
T2StartStop
Now
T1StartStop
Now
T0StartStop
Now
1.7.2
T0Control
Control register of the Timer0.
Table 80.
T0Control register (address 0Fh);
Bit
7
6
–
5
4
3
T0AutoRestart
r/w
2
–
1
0
Symbol
T0StopRx
r/w
T0Start
r/w
T0Clk
r/w
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High performance multi-protocol NFC frontend
Table 81.
T0Control bits
Bit
Symbol
Description
7
T0StopRx
If set, the timer stops immediately after receiving the first 4 bits. If
cleared the timer does not stop automatically.
Note: If LFO Trimming is selected by T0Start, this bit has no effect.
RFU
6
–
5 to 4
T0Start
00b: The timer is not started automatically
01b: The timer starts automatically at the end of the transmission
10b: Timer is used for LFO trimming without underflow (Start/Stop on
PosEdge)
11b: Timer is used for LFO trimming with underflow (Start/Stop on
PosEdge)
3
T0AutoRestart 1:
the timer automatically restarts its count-down from T0ReloadValue,
after the counter value has reached the value zero.
0: the timer decrements to zero a
d stops.
The bit Timer1IRQ is set to logic
hen the timer underflows.
2
–
RFU
1 to 0
T0Clk
00b: The timer input c
s 13.56 MHz.
01b: The timer input clock is 211,875 kHz.
10b: The timer input clock is an underflow of Timer2.
11b: The timer input clock is an underflow of Timer1.
1.7.2.1
T0ReloadHi
High byte reload value of the Timer0.
Table 82.
T0ReloadHi register (address 10h);
Bit
7
6
5
4
3
2
1
0
Symbol
T0Reload Hi
r/w
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Table 83.
T0ReloadHi bits
Bit
Symbol
Description
7 to 0
T0ReloadHi
Defines the high byte of the reload value of the timer. With the start
event, the timer loads the value of the registers T0ReloadValHi,
T0ReloadValLo. Changing this register affects the timer only at the
next start event.
1.7.2.2
T0ReloadLo
Low byte reload value of th
e
T
imer0.
Table 84.
T0ReloadLo register (address 11h);
Bit
7
6
5
4
3
2
1
0
Symbol
T0ReloadLo
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High performance multi-protocol NFC frontend
Table 85.
T0ReloadLo bits
Bit
Symbol
Description
7 to0
T0ReloadLo
Defines the low byte of the reload value of the timer. With the start
event, the timer loads the value of the T0ReloadValHi, T0ReloadValLo.
Changing this register affects the timer only at the next startevent.
1.7.2.3
T0CounterValHi
High byte of the counter value o
f
T
imer0.
Table 86.
T0CounterValHi register (address 12h)
Bit
7
6
5
4
3
2
1
0
0
0
Symbol
T0CounterValHi
dy
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Table 87.
T0CounterValHi bits
Bit
Symbol
Description
High byte value of the
er0.
This value shall not be
d out during reception.
7to0
T0Counter
ValHi
1.7.2.4
T0CounterValLo
Low byte of the counter value of Timer0.
Table 88.
T0CounterValLo register (address 13h)
Bit
7
6
5
4
3
2
1
Symbol
T0CounterValLo
dy
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Tabl
89. T0CounterValLo
bits
Bit
Symbol
Description
7 to 0
T0CounterValLo
Low byte value of the Timer0.
This value shall not be read out during reception.
1.7.2.5
T1Control
Control register of the Timer1.
Table 90.
T1Control register (address 14h);
Bit
7
6
–
5
4
3
T1AutoRestart
r/w
2
–
1
Symbol
T1StopRx
r/w
T1Start
r/w
T1Clk
r/w
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High performance multi-protocol NFC frontend
Table 91.
T1Control bits
Bit
Symbol
Description
7
T1StopRx
If set, the timer stops after receiving the first 4 bits. If cleared, the timer
is not stopped automatically.
Note: If LFO trimming is selected by T1start, this bit has no effect.
RFU
6
–
5 to 4
T1Start
00b: The timer is not started automatically
01b: The timer starts automatically at the end of the transmission
10b: Timer is used for LFO trimming without underflow (Start/Stop on
PosEdge)
11b: Timer is used for LFO trimming with underflow (Start/Stop on
PosEdge)
3
T1AutoRestart Set
to logic 1, the timer automatically restarts
ts countdown from
T1ReloadValue, after the counter value has reached the value zero.
Set to logic 0 the timer decremen
to zero and stops.
The bit Timer1IRQ is set to logic
hen the timer underflows.
2
–
RFU
1 to 0
T1Clk
00b: The timer input c
s 13.56 MHz
01b: The timer input clock is 211,875 kHz.
10b: The timer input clock is an underflow of Timer0
11b: The timer input clockis an underflow of Timer2
1.7.2.6
T1ReloadHi
High byte (MSB) reload valu
of the Timer1.
Table 92.
T0ReloadHi register (address 15h)
Bit
7
6
5
4
3
2
1
0
Symbol
T1ReloadHi
r/w
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Table 93.
T1ReloadHi bits
Bit
Symbol
Description
7 to 0
T1ReloadHi
Defines the high byte reload value of the Timer 1. With the start event,
the timer loads the value of the T1ReloadValHi and T1ReloadValLo.
Changing this register affects the Timer only at the next start event.
1.7.2.7
T1ReloadLo
Low byte (LSB) reload value of the Timer1.
Table 94.
T1ReloadLo register (address 16h)
Bit
7
6
5
4
3
2
1
0
Symbol
T1ReloadLo
r/w
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High performance multi-protocol NFC frontend
Table 95.
T1ReloadValLo bits
Bit
Symbol
Description
7 to 0
T1ReloadLo
Defines the low byte of the reload value of the Timer1. Changing this
register affects the timer only at the next start event.
1.7.2.8
T1CounterValHi
High byte (MSB) of the counter value of byte Timer1.
Table 96.
T1CounterValHi register (address 17h)
Bit
7
6
5
4
3
2
0
0
0
Symbol
T1CounterValHi
dy
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Table 97.
T1CounterValHi bits
Bit
Symbol
Description
7 to 0
T1Counter
ValHi
High byte of the current value of the Timer1.
This value shall not be
d out durin
g
r
eception.
1.7.2.9
T1CounterValLo
Low byte (LSB) of the counter value of byte Timer1.
Table 98.
T1CounterValLo register (address 18h)
Bit
7
6
5
4
3
2
1
Symbol
T1CounterValLo
dy
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Table 99.
1CounterValLo bits
Bit
Symbol
Description
7 to 0
T1Counter
ValLo
Low byte of the current value of the counter 1.
This value shall not be read out during reception.
1.7.2.10
T2Control
Control register of the Timer2.
Table 100. T2Control register (address 19h)
Bit
7
6
–
5
4
3
T2AutoRestart
r/w
2
–
1
Symbol
T2StopRx
r/w
T2Start
r/w
T2Clk
r/w
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High performance multi-protocol NFC frontend
Table 101. T2Control bits
Bit
Symbol
Description
7
T2StopRx
If set the timer stops immediately after receiving the first 4 bits. If
cleared indicates, that the timer is not stopped automatically.
Note: If LFO Trimming is selected by T2Start, this bit has no effect.
6
–
RFU
5 to 4
T2Start
00b: The timer is not started automatically.
01b: The timer starts automatically at the end of the transmission.
10b: Timer is used for LFO trimming without underflow (Start/Stop on
PosEdge).
11b: Timer is used for LFO trimming with und
flow (Start/Stop on
PosEdge).
3
T2AutoRestart Set
to logic 1, the timer automatically res
arts
ts countdown from
T2ReloadValue, after the counter value has reached the value zero.
Set to logic 0 the timer decrements to ze
o and stops. The bit
Timer2IRQ is set to logic 1 whe
e timer underflows
2
–
RFU
1 to 0
T2Clk
00b: The timer input clock is 13.56 MHz.
01b: The timer input c
s 212 kHz.
10b: The timer input c
ock is an underflow of Timer0
11b: The timer input clock is an underflow of Timer1
1.7.2.11
T2ReloadHi
High byte of the reload valu
f Timer2.
Table 102. T2ReloadHi register (address 1Ah)
Bit
7
6
5
4
3
2
1
0
Symbol
T2ReloadHi
r/w
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Table 103. T2Reload bits
Bit
Symbol
Description
7 to 0
T2ReloadHi
Defines the high byte of the reload value of the Timer2. With the start
event, the timer load the value of the T2ReloadValHi and
T2ReloadValLo. Changing this register affects the timer only at the
next start event.
1.7.2.12
T2ReloadLo
Low byte of the reload value of Timer2.
Table 104. T2ReloadLo register (address 1Bh)
Bit
7
6
5
4
3
2
1
0
Symbol
T2ReloadLo
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High performance multi-protocol NFC frontend
Table 105. T2ReloadLo bits
Bit
Symbol
Description
7 to 0
T2ReloadLo
Defines the low byte of the reload value of the Timer2. With the start
event, the timer load the value of the T2ReloadValHi and
T2RelaodVaLo. Changing this register affects the timer only at the next
start event.
1.7.2.13
T2CounterValHi
High byte of the counter register of Timer2.
Table 106. T2CounterValHi register (address 1Ch)
Bit
7
6
5
4
3
2
1
0
0
0
Symbol
T2CounterValHi
dy
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Table 107. T2CounterValHi bits
Bit
Symbol
Description
7 to 0
T2Counter
ValHi
High byte current count
value of Timer2.
This value shall not b
read out during reception.
1.7.2.14
T2CounterValLoReg
Low byte of the current value of Timer 2.
Table 108. T2CounterValLo register (address
Dh)
Bit
7
6
5
4
3
2
1
Symbol
T2CounterValLo
dy
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Table 109. T2CounterValLo bits
Bit
Symbol
Description
7 to0
T2Counter
ValLo
Low byte of the current counter value of Timer1Timer2.
This value shall not be read out during reception.
1.7.2.15
T3Control
Control register of the Timer 3.
Table 110. T3Control register (address 1Eh)
Bit
7
6
–
5
4
3
T3AutoRestart
r/w
2
–
1
Symbol
T3StopRx
r/w
T3Start
r/w
T3Clk
r/w
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High performance multi-protocol NFC frontend
Table 111. T3Control bits
Bit
Symbol
Description
7
T3StopRx
If set, the timer stops immediately after receiving the first 4 bits. If
cleared, indicates that the timer is not stopped automatically.
Note: If LFO Trimming is selected by T3Start, this bit has no effect.
RFU
6
–
5 to 4
T3Start
00b – timer is not started automatically
01b – timer starts automatically at the end of the transmission
10b – timer is used for LFO trimming without underflow (Start/Stop on
PosEdge)
11b – timer is used for LFO trimming with und
flow (Start/Stop on
PosEdge).
3
T3AutoRestart Set
to logic 1, the timer automatically res
arts
ts countdown from
T3ReloadValue, after the counter value has reached the value zero.
Set to logic 0 the timer decremen
s to zero and stops.
The bit Timer1IRQ is set to logi
hen the timer underflows.
2
–
RFU
1 to 0
T3Clk
00b – the timer input cl
is 13.56 MHz.
01b – the timer input clo
is 211,875 kHz.
10b – the timer input c
ock is an underflow of Timer0
11b – the timer input clock is an underflow o
f
T
imer1
1.7.2.16
T3ReloadHi
High byte of the reload valu
of Timer3.
Table 112. T3ReloadHi register (address 1Fh);
Bit
7
6
5
4
3
2
1
0
Symbol
T3ReloadHi
r/w
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Table 113. T3ReloadHi bits
Bit
Symbol
Description
7 to 0
T3ReloadHi
Defines the high byte of the reload value of the Timer3. With the start
event, the timer load the value of the T3ReloadValHi and
T3ReloadValLo. Changing this register affects the timer only at the
next start event.
1.7.2.17
T3ReloadLo
Low byte of the reload value of Timer3.
Table 114. T3ReloadLo register (address 20h)
Bit
7
6
5
4
3
2
1
0
Symbol
T3ReloadLo
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High performance multi-protocol NFC frontend
Table 115. T3ReloadLo bits
Bit
Symbol
Description
7 to 0
T3ReloadLo
Defines the low byte of the reload value of Timer3. With the start
event, the timer load the value of the T3ReloadValHi and
T3RelaodValLo. Changing this register affects the timer only at the
next start event.
1.7.2.18
T3CounterValHi
High byte of the current counter value the 16-bit Timer3.
Table 116. T3CounterValHi register (address 21h)
Bit
7
6
5
4
3
2
1
0
Symbol
T3CounterValHi
dy
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Table 117. T3CounterValHi bits
Bit
Symbol
Description
7 to 0
T3Counter
ValHi
High byte of the current
unter value of Timer3.
This value shall not b
read out during reception.
1.7.2.19
T3CounterValLo
Low byte of the current counter value the 16-bit Timer3.
Table 118. T3CounterValLo register (address
2h)
Bit
7
6
5
4
3
2
1
0
Symbol
T3CounterValLo
dy
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Table 119. T3CounterValLo bits
Bit
Symbol
Description
7 to 0
T3Counter
ValLo
Low byte current counter value of Timer3.
This value shall not be read out during reception.
1.7.2.20
T4Control
The wake-up timer T4 activates the system after a given time. If enabled, it can start the
low-power card detection function.
Table 120. T4Control register (address 23h)
Bit
7
6
5
4
3
2
1
0
Symbol
T4Running
T4Start
StopNow
T4Auto
Trimm
T4Auto
LPCD
T4Auto
Restart
T4AutoWakeUp
T4Clk
r/w
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w
r/w
r/w
r/w
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第81页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 121. T4Control bits
Bit
Symbol
Description
7
T4Running
Shows if the timer T4 is running. If the bit T4StartStopNow is set, this
bit and the timer T4 can be started/stopped.
6
5
T4Start
StopNow
if set, the bit T4Running can be changed.
T4AutoTrimm
If set to one, the timer activates an LFO trimming procedure when it
underflows. For the T4AutoTrimm function, at least one timer (T0 to
T3) has to be configured properly for trimming (T3 is not allowed if
T4AutoLPCD is set in parallel).
4
T4AutoLPCD
If set to one, the timer activates a low-power card
ction
sequence. If a card is detected an interrupt request is raised and the
system remains active if enabled. If no card is detected the JSM66302
enters the Power down mode if enabled. The timer is automatically
restarted (no gap). Timer 3 is used to specify the time where the RF
field is enabled to check if a card is present. Therefore you may not
use Timer 3 for T4AutoTrimm
arallel.
3
2
T4AutoRestart
Set to logic 1, the timer automatically restarts its countdown from
T4ReloadValue, after the counter value has reached the value zero.
Set to logic 0 the tim
ecrements to zero and stops. The bit
Timer4IRQ is set to l
1 at timer underflow.
T4AutoWakeUp If
set, the JSM66302 wakes up automatically, when the timer T4 has
an underflow. This bit has to be set if the IC should enter the Power
down mode after T4AutoTrimm and/or T4AutoLPCD is finished and
no card has been detected. If the IC should stay active after one of
these procedures, this bit has to be set to 0.
1 to 0
T4Clk
0
b –
he timer input clock is the LFO clock
01b – the timer input clock is the LFO clock/8
10b – the timer input clock is the LFO clock/16
11b – the timer input clock is the LFO clock/32
8.7.2.21
T4Reload
i
High byte
f the reload value of the 16-bit timer 4.
Table 122. T4ReloadHi register (address 24h)
Bit
7
6
5
4
3
2
1
0
Symbol
T4ReloadHi
r/w
Access
rights
Table 123. T4ReloadHi bits
Bit
Symbol
Description
7 to 0
T4ReloadHi
Defines high byte for the reload value of timer 4. With the start event,
the timer 4 loads the T4ReloadVal. Changing this register affects the
timer only at the next start event.
8.7.2.22
T4ReloadLo
Low byte of the reload value of the 16-bit timer 4.
第82页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 124. T4ReloadLo register (address 25h)
Bit
7
6
5
4
3
2
1
0
Symbol
T4ReloadLo
r/w
Access
rights
Table 125. T4ReloadLo bits
Bit
Symbol
Description
7 to 0
T4ReloadLo
Defines the low byte of the reload value of the timer
With the start
event, the timer loads the value of the T4ReloadVa
anging this
register affects the timer only at the next start
vent.
8.7.2.23
T4CounterValHi
High byte of the counter value of the 16-bit timer 4.
Table 126. T4CounterValHi register (address 26h)
Bit
7
6
5
4
3
2
1
0
Symbol
T4CounterValH
dy
Access
rights
Table 127. T4CounterValHi bits
Bit
Symbol
D
scription
High byte of the current counter value of timer 4.
7 to 0
T4CounterValHi
8.7.2.24
T4CounterValLo
Low byte of t
unter value of the 16-bit timer 4.
Table 128. T4CounterValLo regis
(address 27h)
Bit
7
6
5
4
3
2
1
0
Symbol
T4CounterValLo
dy
Access
rights
Table 129. T4CounterValLo bits
Bit
Symbol
Description
Low byte of the current counter value of the timer 4.
7 to 0
T4CounterValLo
第83页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.8
Transmitter configuration registers
8.8.1
TxMode
Table 130. DrvMode register (address 28h)
Bit
7
6
5
–
4
–
3
2
1
TxClk Mode
r/w
0
Symbol
Tx2Inv
r/w
Tx1Inv
r/w
TxEn
r/w
Access
rights
RFU
RFU
Table 131. DrvMode bits
Bit
Symbol
Tx2Inv
Tx1Inv
Description
7
Inverts transmitter 2 at TX2 pin
6
Inverts transmitter 1 at TX1 pin
5
RFU
RFU
4
–
3
TxEn
If set to 1 both transmitter pins are enabled
2 to 0
TxClkMode
Transmitter clock settings (see 8.6.2. Table 27). Codes 011b and
0b110 are not suppor
his register defines, if the output is
operated in open-drain, push-pull, at high impedance or pulled to a fix
high or low level.
8.8.2
TxAmp
With the set_cw_amplitude register, output power can be traded off against power supply
rejection. Spending more he
droom leads to better power supply rejection ration and
better accuracy of the modulation degree.
With CwMax set, the voltage of TX1 will be pulled to the maximum possible. This register
overrides the
ngs made by set_cw_amplitude.
Table 132. TxAmp register (addre
29h)
Bit
7
6
5
–
4
3
2
set_residual_carrier
r/w
1
0
Symbol
set_cw_amplitude
r/w
Access
rights
RFU
Table 133. TxAmp bits
Bit
Symbol
Description
7 to 6
set_cw_amplitude
Allows reducing the output amplitude of the transmitter by a fix
value.
Four different preset values that are subtracted from TVDD can
be selected:
0: TVDD -100 mV
1: TVDD -250 mV
2: TVDD -500 mV
3: T
VDD
-1000 mV
–
5
RFU
4 to 0
set residual
carrier Set
the residual carrier percentage
refer to Section 7 6 2
第84页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.8.3
TxCon
Table 134. TxCon register (address 2Ah)
Bit
7
6
5
OvershootT2
r/w
4
3
2
1
0
Symbol
CwMax
r/w
TxInv
r/w
TxSel
r/w
Access
rights
Table 135. TxCon bits
Bit
Symbol
Description
7 to 4
OvershootT2 Specifies
the length (number of carrier clocks
of the additional
3
Cwmax
Set amplitude of continuous wave carrier to the maximum.
If set, set_cw_amplitude in Register TxAmp has no influence on the
continuous amplitude.
2
TxInv
TxSel
If set, the resulting modulation signal defined by TxSel is inverted
1 to 0
Defines which signal is used as source for modulation
00b … no modulation
01b … TxEnvelope
10b … SigIn
11b … RFU
8.8.4
Txl
Table 136. Txl register (address 2Bh)
Bit
7
6
5
OvershootT1
4
3
2
1
0
Symbol
tx_set_iLoad
r/w
Access
rights
Table 137. Txl bits
Bit
Symbol
Description
7 to 4
3 to 0
tx_set_iLoad
Factory trim value, sets the expected Tx load current. This value is
used to control the modulation index in an optimized way dependent
on the expected TX load current.
第85页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.9
CRC configuration registers
8.9.1
TxCrcPreset
Table 138. TXCrcPreset register (address 2Ch)
Bit
7
RFU
–
6
5
4
3
2
1
TxCRCInvert
r/w
0
Symbol
TXPresetVal
r/w
TxCRCtype
r/w
TxCRCEn
r/w
Access
rights
Table 139. TxCrcPreset bits
Bit
Symbol
Description
7
RFU
–
6 to 4
3 to 2
TXPresetVal
TxCRCtype
Defines which type of CRC (CRC
CRC16/CRC5) is calculated:
•
•
•
•
00h — CRC5
01h — CRC8
02h — CRC16
03h — RFU
1
0
TxCRCInvert if
set, the resulting CRC is inverted and attached to the data frame
(ISO/IEC 3309)
TxCRCEn
if set, a CRC is appended to the data stream
Table 140. Transmitter CRC p
eset value configuration
TXPresetVal[6…4]
CRC
6
0000h
6363h
A671h
FFFEh
–
CRC8
CRC5
0h
1h
2h
3h
4h
5h
6h
7h
00h
00h
12h
12h
BFh
–
FDh
–
–
–
–
–
–
User defined
FFFFh
User defined
FFh
User defined
1Fh
Remark:
User-defined CRC preset values can be configured by EEPROM (see
第86页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.9.2
RxCrcCon
Table 141. RxCrcCon register (address 2Dh)
Bit
7
RxForceCRCWrite
r/w
6
5
4
3
2
1
RxCRCInvert
r/w
0
Symbol
RXPresetVal
r/w
RXCRCtype
r/w
RxCRCEn
r/w
Access
rights
Table 142. RxCrcCon bits
Bit
Symbol
Description
7
RxForceCrc
Write
If set, the received CRC byte(s) are copied to the FIFO.
If cleared CRC Bytes are only checked, but not copied to the FIFO.
This bit has to be always set in case of a not byte aligned CRC (e.g.
ISO/IEC 18000-3 mode 3/ EPC Class-1HF)
6 to 4
3 to 2
RxCRCtype
Defines which type of CRC (CR
RC16/CRC5) is calculated:
•
•
•
•
00h — CRC5
01h — CRC8
02h — CRC16
03h — RFU
1
0
RxCrcInvert
RxCrcEn
If set, the CRC check is done for the inverted CRC.
If set, the CRC is checked and in case of a wrong CRC an error flag is
set. Otherwise the CRC is calculated but the error flag is not modified.
Table 143. Receiver CRC preset value configuration
RXPresetVal[6…4]
CRC16
0000h
6363h
A671h
FFFEh
–
CRC8
CRC5
0h
1h
2h
3h
4h
5h
6h
7h
00h
00h
12h
12h
BFh
–
FDh
–
–
–
–
–
–
User defined
FFFFh
User defined
FFh
User defined
1Fh
第87页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.10
Transmitter configuration registers
8.10.1
TxDataNum
Table 144. TxDataNum register (address 2Eh)
Bit
7
6
5
4
KeepBitGrid
r/w
3
2
1
TxLastBits
r/w
0
Symbol
RFU
RFU-
RFU-
DataEn
r/w
Access
rights
Table 145. TxDataNum bits
Bit
7 to5
4
Symbol
RFU
Description
–
KeepBitGrid
If set, the time between consecutive transmissions starts is a multiple
of one ETU. If cleared, consecuti
e transmissions can even start
within one ETU
3
DataEn
If cleared – it is possible to send a single symbol pattern.
If set – data is sent.
2 to 0
TxLastBits
Defines how many bits
he last data byte to be sent. If set to 000b,
all bits of the last data byte are sent.
Note – bits are skipped at the end of the byte.
Example – Data byte B2h (sent LSB first).
TxLastBits = 011b (3h) => 010b (LSB first) is sent
Tx
stBits = 110b (6h) => 010011b (LSB first) is sent
8.10.2
TxDATAModWidth
Transmitter d
modulation width register
Table 146. TxDataModWidth reg
(ad
ess 2Fh)
Bit
7
6
5
4
3
2
1
0
Symbol
DModWidth
r/w
Access
rights
Table 147. TxDataModWidth bits
Bit
Symbol
Description
7 to 0
DModWidth
Specifies the length of a pulse for sending data with enabled pulse
modulation. The length is given by the number of carrier clocks + 1.
A pulse can never be longer than from the start of the pulse to the end
of the bit. The starting position of a pulse is given by the setting of
TxDataMod.DPulseType. Note: This register is only used if Miller
modulation (ISO/IEC 14443A PCD) is used. The settings are also
used for the modulation width of start and/or stop symbols.
第88页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.10.3
TxSym10BurstLen
If a protocol requires a burst (an unmodulated subcarrier) the length can be defined with
this TxSymBurstLen, the value high or low can be defined by TxSym10BurstCtrl.
Table 148. TxSym10BurstLen register (address 30h)
Bit
7
RFU
–
6
5
4
3
RFU
–
2
1
Sym0Burst Len
r/w
0
Symbol
Sym1Burst Len
r/w
Access
rights
Table 149. TxSym10BurstLen bits
Bit
7
Symbol
Description
RFU
–
6 to 4
Sym1BurstLen Specifies
the number of bits issued for symbol 1 burst. The 3 bits
encodes a range from 8 to 256 b
00h – 8bit
01h – 16bit
02h – 32bit
04h – 48bit
05h – 64bit
06h – 96bit
07h – 128bit
0
– 256bit
3
RFU
–
2 to 0
Sym0BurstLen Specifies
the number of bits issued for symbol 1 burst. The 3 bits
encodes a range from 8 to 256 bit:
00h – 8bit
01h – 16bit
02h – 32bit
03h – 48bit
04h – 64bit
05h – 96bit
06h – 128bit
07h – 256bit
第89页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.10.4
TxWaitCtrl
Table 150. TxWaitCtrl register (address 31h); reset value: C0h
Bit
7
TxWaitStart
r/w
6
5
4
TxWait High
r/w
3
2
1
TxStopBitLength
r/w
0
Symbol
TxWaitEtu
r/w
Access
rights
Table 151. TXWaitCtrl bits
Bit
Symbol
Description
7
TxWaitStart
If cleared, the TxWait time is starting at the End of the send data
(TX).
If set, the TxWait time is starting at the End of the received data
(RX).
6
TxWaitEtu
If cleared, the TxWait time is TxWait
16/13.56 MHz.
If set, the TxWait time is Tx
0.5 / DBFreq (DBFreq is the
frequency of the bit stream as defined by TxDataCon).
5 to 3
2 to 0
TxWait High
Bit extension of TxWaitLo. TxWaitCtrl bit 5 is MSB.
TxStopBitLength
Defines stop-bits a
GT (= stop-bit + extra guard time EGT) to
be sent:
0h: no stop-bit, no EGT
1h: 1 stop-bit, no EGT
2h: 1 stop-bit + 1 EGT
h: 1 stop-bit + 2 EGT
4h: 1 stop-bit + 3 EGT
5h: 1 stop-bit + 4 EGT
6h: 1 stop-bit + 5 EGT
7h: 1 stop-bit + 6 EGT
Note: This is only valid for ISO/IEC14443 Type B
第90页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.10.5
TxWaitLo
Table 152. TxWaitLo register (address 32h)
Bit
7
6
5
4
3
2
1
0
Symbol
TxWaitLo
r/w
Access
rights
Table 153. TxWaitLo bits
Bit
Symbol
Description
7 to 0
TxWaitLo
Defines the minimum time between receive a
d send or between two
send data streams
Note: TxWait is a 11bit register (additional 3 b
ts are in the TxWaitCtrl
register)!
See also TxWaitEtu and TxWaitS
art.
8.11
FrameCon
Table 154. FrameCon register (address 33h)
Bit
7
6
RxParityEn
r/w
5
–
4
–
3
2
1
0
Symbol
TxParityEn
r/w
StopSym
r/w
StartSym
r/w
Access
rights
RFU
RFU
Table 155. FrameCon bits
Bit
Symbol
Description
7
Tx
yEn
If set, a parity bit is calculated and appended to each byte
transmitted.
6
xParityEn
If set, the parity calculation is enabled. The parity is not transferred to
the FIFO.
5 to 4
3 to 2
–
RFU
StopSym
Defines which symbol is sent as stop-symbol:
•
•
•
•
0h: No symbol is sent
1h: Symbol0 is sent
2h symbol1 is sent
3h Symbol2 is sent
1 to 0
StartSym
Defines which symbol is sent as start-symbol:
•
•
•
•
0h: No Symbol is sent
1h: Symbol0 is sent
2h: Symbol1 is sent
3h: Symbol2 is sent
第91页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.12
Receiver configuration registers
8.12.1
RxSofD
Table 156. RxSofD register (address 34h)
Bit
7
6
5
4
SOFDetected
dy
3
RFU
–
2
1
SubC_Detected
dy
0
Symbol
RFU
–
SOF_En
r/w
SubC_En
r/w
SubC_Present
r
Access
rights
Table 157. RxSofD bits
Bit Symbol
7 to 6
RFU
Description
–
5
4
3
2
1
0
SOF_En
If set and a SOF is detected an RxSOF
RQ is raised.
SOF_Detected
RFU
Shows that a SOF is or was de
ted. Can be cleared by SW.
–
SubC_En
If set and a subcarrier is detected an RxSOFIRQ is raised.
Shows that a subcar
or was detected. Can be cleared by SW.
Shows that a subcarrier is currently detected.
SubC_Detected
SubC_Present
8.12.2
RxCtrl
Table 158. RxCtrl register (address 35h)
Bit
7
RxAllowBits
r/w
6
5
RxEOFT
pe
r/w
4
EGT_Check
r/w
3
2
1
0
Symbol
RxMultiple
r/w
EMD_Sup
r/w
Baudrate
r/w
Access
rights
Table 159
xCtrl bits
Bit
Symbol
Description
7
RxAllowBits
If set, data is written into FIFO even if CRC is enabled, and no
complete byte has been received.
6
5
RxMultiple
If set, RxMultiple is activated and the receiver will not terminate
If set to logic 1, at the end of a received data stream an error byte is
added to the FIFO. The error byte is a copy of the Error register.
0: EOF as defined in the RxEOFSymbolReg is expected.
1: ISO/IEC14443B EOF is expected.
RxEOFType
Note: Clearing this bit to 0 and clearing bit 0 and bit 1 in the
RxEOFSymbolReg disables the EOF check.
第92页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 159. RxCtrl bits
Bit
Symbol
Description
4
EGT_Check
If set to 1, the EGT is checked and if it is too long
a protocol error is set. (This is only valid for ISO/IEC14443 Type B).
3
EMD_Sup
Enables the EMD suppression according to ISO/IEC14443. If an error
occurs within the first three bytes, these three bytes are assumed to be
EMD, ignored and the FIFO is reset. A collision is treated as an error
as well If a valid SOF was received, the EMD_Sup is set and a frame
of less than 3 bytes had been received. RX_IRQ is not se
in this EMD
error cases. If RxForceCRCWrite is set, the FIFO should not be read
out before three bytes are written into.
2 to 0
Baudrate
Defines the baud rate of the receivin
g
s
ignal.
2h: 26 kBd
3h: 52 kBd
4h: 106 kBd
5h: 212 kBd
6h: 424 kBd
7h: 847 kBd
all remaining values a
FU
8.12.3
RxWait
Selects internal receiver settings.
Table 160. RxWait register (address 36h)
Bit
7
6
5
4
3
2
1
0
Symbol
RxWaitEtu
r/w
RxWait
r/w
Access
rights
Table 161
Wait bits
Bit
Symbol
Description
7
RXWaitEtu
If set to 0, the RxWait time is RxWait
16/13.56 MHz.
If set to 1, the RxWait time is RxWait
(0.5/DBFreq).
Defines the time after sending, where every input is ignored.
6 to 0
RxWait
第93页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.12.4
RxThreshold
Selects minimum threshold level for the bit decoder.
Table 162. RxThreshold register (address 37h)
Bit
7
6
5
4
3
2
1
0
Symbol
MinLevel
r/w
MinLevelP
r/w
Access
rights
Table 163. RxThreshold bits
Bit
Symbol
Description
Defines the MinLevel of the reception.
Note: The MinLevel should be higher than the noise level in the system.
MinLevelP Defines
the MinLevel of the phase shift detector unit.
7 to 4
MinLevel
3 to 0
8.12.5
Rcv
Table 164. Rcv register (address 38h)
Bit
7
Rcv_Rx_single
r/w
6
Rx_ADCmode
r/w
5
4
3
2
1
0
Symbol
SigInSel
r/w
RFU
–
CollLevel
r/w
Access
rights
Table 165. Rcv bits
Bit
Symbol
Description
7
Rcv_Rx_single
Single RXP Input Pin Mode;
0: Fully Differential
1: Quasi-Differential
6
x_ADCmode
SigInSel
Defines the operation mode of the Analog Digital Converter (ADC)
0: normal reception mode for ADC
1: LPCD mode for ADC
5 to 4
Defines input for the signal processing unit:
0h – idle
1h – internal analog block (RX)
2h – signal in over envelop
e
(
ISO/IEC14443A)
3h – signal in over s3c-generic
3 to 2
1 to 0
RFU
–
CollLevel
Defines the strength of a signal to be interpreted as a collision:
0h – Collision has at least 1/8 of signal strength
1h – Collision has at least 1/4 of signa
l
s
trength
2h – Collision has at least 1/2 of signa
l
s
trength
3h – Collision detection is switched off
第94页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.12.6
RxAna
This register allows setting the gain (rcv_gain) and high pass corner frequencies
(rcv_hpcf).
Table 166. RxAna register (address 39h)
Bit
7
6
5
4
3
2
1
0
Symbol
VMid_r_sel
r/w
RFU
–
rcv_hpcf
r/w
rcv_gain
r
w
Access
rights
Table 167. RxAna bits
Bit
Symbol
VMid_r_sel
RFU
Description
Factory trim value, needs to be 0.
7, 6
5, 4
3, 2
rcv_hpcf
The rcv_hpcf [1:0] signals allow
fferent settings of the base band
amplifier high pass cut-off freque
y from ~40 kHz to ~300 kHz.
1 to 0
rcv_gain
With rcv_gain[1:0] four different gain settings from 30 dB and 60 dB
can be configured (dif
tial output voltage/differential input voltage).
Table 168. Effect of gain and high-pass corner register settings
rcv_gain
(Hex.)
rcv_hpcf
(Hex.)
fl (kHz)
fU (MHz)
gain (dB20)
bandwidth
(MHz)
03
03
03
03
02
02
02
02
01
01
01
01
00
00
00
00
00
01
02
0
01
02
03
00
01
02
03
00
01
02
03
38
2.3
2.4
2.6
2.9
2.3
2.4
2.6
3.0
2.6
2.7
2.9
3.3
2.6
2.7
2.9
3.4
60
59
58
55
51
50
49
41
43
42
41
39
35
34
33
30
2.3
2.3
2.5
2.6
2.3
2.3
2.4
2.7
2.6
2.6
2.7
3.0
2.6
2.6
2.7
3.1
79
150
264
41
83
157
272
42
84
157
273
43
85
159
276
第95页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.13
Clock configuration
8.13.1
SerialSpeed
This register allows setting speed of the RS232 interface. The default speed is set to
9.6 kbit/s. The transmission speed of the interface can be changed by modifying the
entries for BR_T0 and BR_T1. The transfer speed can be calculated by using the
following formulas:
BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1)
BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33) / 2^(BR_T0
1
The framing is implemented with 1 start bit, 8 data bits and 1 stop bit. A parity bit is not
used. Transfer speeds above 1228.8 kbit/s are not supported.
Table 169. SerialSpeed register (address3Bh); reset value: 7Ah
Bit
7
6
5
4
3
2
BR_T1
r/w
1
0
Symbol
BR_T0
r/w
Access
rights
Table 170. SerialSpeed bits
Bit Symbol
Description
7 to 5
BR_T0 BR_T0
= 0: trans
er speed = 27.12 MHz / (BR_T1 + 1)
BR_T0 > 0: t
nsfer speed = 27.12 MHz / (BR_T1 + 33) / 2^(BR_T0
1)
4 to 0
BR_T1 BR_T0
= 0: transfer speed = 27.12 MHz / (BR_T1 + 1)
BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33) / 2^(BR_T0
1)
Table 171. RS
eed settings
Transfer
ed (kbit/s)
SerialSpeed register content (Hex.)
7.2
FA
EB
DA
CB
AB
9A
7A
74
9.6
14.4
19.2
38.4
57.6
115.2
128.0
230.4
460.8
921.6
1228.8
5A
3A
1C
15
第96页,共139页
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High performance multi-protocol NFC frontend
8.13.2
LFO_Trimm
Table 172. LFO_Trim register (address 3Ch)
Bit
7
6
5
4
3
2
1
0
Symbol
LFO_trimm
r/w
Access
rights
Table 173. LFO_Trim bits
Bit
Symbol
Description
7 to 0
LFO_trimm
Note: If the trimm value is increased, the frequency of the oscillator
decreases.
8.13.3
PLL_Ctrl Register
The PLL_Ctrl register implements the control register
he IntegerN PLL. Two stages
exist to create the ClkOut signal from the 27.12 MHz input. In the first stage, the
27.12 MHz input signal is multiplied by the value defined in PLLDiv_FB and divided by
two, and the second stage divides this freque
by the value defined by PLLDIV_Out.
Table 174. PLL_Ctrl register (address3Dh)
Bit
7
6
5
4
3
ClkOut_En
r/w
2
1
0
Symbol
ClkOutSel
r/w
PLL_PD
r/w
PLLDiv_FB
r/w
Access
rights
Table 175. PLL_Ctrl register bits
Bit
Sym
Description
7 to 4
kOutSel
•
•
•
•
•
•
•
•
•
•
•
•
•
0h – pin CLKOUT is used as I/O
1h – pin CLKOUT shows the output of the analog PLL
2h – pin CLKOUT is hold on 0
3h – pin CLKOUT is hold on 1
4h – pin CLKOUT shows 27.12 MHz from the crystal
5h – pin CLKOUT shows 13.56 MHz derived from the crystal
6h – pin CLKOUT shows 6.78 MHz derived from the crystal
7h – pin CLKOUT shows 3.39 MHz derived from the crystal
8h – pin CLKOUT is toggled by the Timer0 overflow
9h – pin CLKOUT is toggled by the Timer1 overflow
Ah – pin CLKOUT is toggled by the Timer
2
o
verflow
Bh – pin CLKOUT is toggled by the Timer
3
o
verflow
Ch…Fh – RFU
3
ClkOut_En
PLL_PD
Enables the clock at Pin CLKOUT
PLL power down
2
1-0
PLLDiv_FB
PLL feedback divider (see table 174)
第97页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 176. Setting of feedback divider PLLDiv_FB [1:0]
Bit 1
Bit 0
Division
0
0
1
1
0
1
0
1
23 (VCO frequency 312 MHz)
27 (VCO frequency 366 MHz)
28 (VCO frequency 380 Mhz)
23 (VCO frequency 312 Mhz)
8.13.4
PLLDiv_Out
Table 177. PLLDiv_Out register (address 3Eh)
Bit
7
6
5
4
3
2
1
0
Symbol
PLLDiv_Out
r/w
Access
rights
Table 178. PLLDiv_Out bits
Bit
Symbol
Description
7 to 0
PLLDiv_Out
Table 179. Setting for the output divider ratio PLLDiv_Out [7:0]
Value
Division
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
8
0
1
2
3
4
5
6
7
8
9
9
10
…
253
254
10
…
253
254
第98页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.14
Low-power card detection configuration registers
The LPCD registers contain the settings for the low-power card detection. The setting for
LPCD_IMax (6 bits) is done by the two highest bits (bit 7, bit 6) of the registers
LPCD_QMin, LPCD_QMax and LPCD_IMin each.
8.14.1
LPCD_QMin
Table 180. LPCD_QMin register (address 3Fh)
Bit
7
LPCD_IMax.5
r/w
6
LPCD_IMax.4
r/w
5
4
3
2
1
0
Symbol
LPCD_QMin
r/w
Access
rights
Table 181. LPCD_QMin bits
Bit
Symbol
Description
7, 6
LPCD_IMax
Defines the highest two bits of th
igher border for the LPCD. If the
measurement value of the
channel is higher than LPCD_IMax, an
LPCD interrupt request
s indicated by bit IRQ0.LPCDIRQ.
5 to 0
LPCD_QMin
Defines the lower bord
or the LPCD. If the measurement value of
the Q channel is higher than LPCD_QMin, an LPCDinterrupt request is
indicated by bit IRQ0.LPCDIRQ.
8.14.2
LPCD_QMax
Table 182. LPCD_QMax register (address 40h)
Bit
7
LPCD_IMax.3
r/w
6
LPCD_IMax.2
r
5
4
3
2
1
0
Symbol
LPCD_QMax
r/w
Access
rights
Table 183. LPCD_QMax bits
Bit
Symbol
Description
7
LPCD_IMax.3
Defines the bit 3 of the high border for the LPCD. If the measurement
value of the I channel is higher than LPCD IMax, an LPCD IRQ is
raised.
6
LPCD_IMax.2
LPCD_QMax
Defines the bit 2 of the high border for the LPCD. If the measurement
value of the I channel is higher than LPCD IMax, an LPCD IRQ is
raised.
5 to 0
Defines the high border for the LPCD. If the measurement value of
the Q channel is higher than LPCD QMax, an LPCD IRQ is raised.
8.14.3
LPCD_IMin
Table 184. LPCD_IMin register (address 41h)
Bit
7
LPCD_IMax.1
r/w
6
5
4
3
2
1
0
Symbol
LPCD_IMax.0 LPCD_IMin
r/w
Access
rights
r/w
第99页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 185. LPCD_IMin bits
Bit
Symbol
Description
7 to 6
LPCD_IMax
Defines lowest two bits of the higher border for the low-power card
detection (LPCD). If the measurement value of the I channel is higher
than LPCD IMax, an LPCD IRQ is raised.
5 to 0
LPCD_IMin
Defines the lower border for the low power card detection. If the
measurement value of the I channel is lower than LPCD IMin, an
LPCD IRQ is raised.
8.14.4
LPCD_Result_I
Table 186. LPCD_Result_I register (address 42h)
Bit
7
RFU-
–
6
RFU-
–
5
4
3
2
1
0
Symbol
LPCD_Result_I
r
Access
rights
Table 187. LPCD_I_Result bits
Bit
Symbol
Description
7 to 6
5 to 0
RFU
–
LPCD_Result_I Shows
the result of the last low-power card detection (I-Channel).
8.14.5
LPCD_Result_Q
Table 188. LPCD_Result_Q register (address
3h)
Bit
7
6
5
4
3
2
1
0
Symbol
RFU
LPCD_IRQ_C
lr
LPCD_Reslult_Q
Access
rights
–
r/w
r
Table 189. LPCD_Q_Result bits
Bit
7
Symbol
Description
RFU
–
6
LPCD_IRQ_Clr
If set no LPCD IRQ is raised any more until the next low-power
card detection procedure. Can be used by software to clear the
interrupt source.
5 to 0
LPCD_Result_Q
Shows the result of the last low power card detection (Q-Channel).
第100页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.15
Pin configuration
8.15.1
PinEn
Table 192. PinEn register (address 44h)
Bit
7
6
5
4
3
2
1
0
Symbol
SIGIN_EN CLKOUT_EN
/ IFSEL1_EN
/ IFSEL0_EN
TCK_EN
/OUT 3
TMS_EN /
TDI
/ TDO_EN
/
/ OUT7
OUT6
OUT5
/ OUT4
OUT2
O
OUT0
Access
rights
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Table 193. PinEn bits
Bit
Symbol
Description
7
SIGIN_EN / OUT7
Enables the output functionality on SIGIN (pin 5). The pin is
then used as outputoutput.
6
CLKOUT_EN / OUT6
Enables the o
functionality of the CLKOUT (pin 22)
.
T
he
pin is then used as output. The CLKOUT function i
s
s
witched
off.
5
4
3
IFSEL1_EN / OUT5
IFSEL0_EN / OUT4
TCK_EN / OUT3
Enables the output functionality of the IFSEL1 (pin 27). The
pin is then used as output.
Enables the output functionality of the IFSEL0 (pin 26). The
pin is then used as output.
Enables the output functionality of the TCK (pin 4) of the
boundary scan interface. The pin is then used as output. If the
boundary scan is activated in EEPROM, this bit has no
function.
第101页,共139页
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High performance multi-protocol NFC frontend
Table 193. PinEn bits
Bit
Symbol
Description
2
TMS_EN / OUT2
TDI_EN / OUT1
TDO_EN / OUT0
Enables the output functionality of the TMS (pin 2) of the
boundary scan interface. The pin is then used as output. If the
boundary scan is activated in EEPROM, this bit has no
function.
1
0
Enables the output functionality of the TDI (pin 1) of the
boundary scan interface. The pin is then used as output. If the
boundary scan is activated in EEPROM, this bit has no
function.
Enables the output functionality of the TDO(pin 3) of the
boundary scan interface. The pin is then u
s output. If the
boundary scan is activated in EEPROM, this bit has no
function.
8.15.2
PinOut
Table 194. PinOut register (address 45h)
Bit
7
6
5
4
3
2
1
0
Symbol SIGIN_OUT CLKOUT_OUT IFSEL1_OUT
IFSEL0_OUT TCK_OUT
TMS_OU TDI_OUT
TDO_OUT
T
Access
rights
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Table 195. PinOut bits
Bit
7
Symbol
D
cription
SIGIN_OUT
Output buffer of the SIGIN pin
6
CLKOUT_OUT Output
buffer of the CLKOUT pin
5
IFSEL1_OUT
IFS
OUT
K_OUT
TMS_OUT
TDI_OUT
Output buffer of the IFSEL1 pin
Output buffer of the IFSEL0 pin
Output buffer of the TCK pin
Output buffer of the TMS pin
Output buffer of the TDI pin
Output buffer of the TDO pin
4
3
2
1
0
TDO_OUT
8.15.3
PinIn
Table 196. PinIn register (address 46h)
Bit
7
6
5
4
3
2
1
0
Symbol
SIGIN_IN CLKOUT_IN IFSEL1_IN
IFSEL0_IN
TCK_IN
r
TMS_IN
r
TDI_IN
r
TDO_IN
r
Access
rights
r
r
r
r
Table 197. PinIn bits
Bit
7
Symbol
Description
SIGIN_IN
Input buffer of the SIGIN pin
6
CLKOUT_IN
IFSEL1 IN
Input buffer of the CLKOUT pin
5
I
t b
ff
f th
IFSEL1 i
第102页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 197. PinIn bits
Bit
4
Symbol
Description
IFSEL0_IN
TCK_IN
TMS_IN
TDI_IN
Input buffer of the IFSEL0 pin
Input buffer of the TCK pin
Input buffer of the TMS pin
Input buffer of the TDI pin
Input buffer of the TDO pin
3
2
1
0
TDO_IN
8.15.4
SigOut
Table 198. SigOut register (address 47h)
Bit
7
6
5
4
3
2
1
0
Symbol
Pad
RFU
SigOutSel
Speed
Access
rights
r/w
–
r/w
Table 199. SigOut bits
Bit
Symbol
Description
7
PadSpeed
If set, the I/O pins are supporting a fast switching mode.The fast mode
for the I/O’s will increase the peak current consumption of the device,
especially if multiple I/Os are switching at the same time. The power
supply needs to be designed to deliver this peak current.
6 to 4
3 to 0
RFU
–
SIGOutSel
0h, 1h – The pin SIGOUT i
s
3
-state
2h – The pin SIGOUT is 0
3h – The pin SIGOUT is 1
4h – The pin SIGOUT shows the TX-envelope
5h – The pin SIGOUT shows the TX-active signal
6h – The pin SIGOUT shows the S3C (generic) signal
7h – The pin SIGOUT shows the RX-envelope
(only valid for ISO/IEC 14443A, 106 kBd)
8h – The pin SIGOUT shows the RX-active signal
9h – The pin SIGOUT shows the RX-bit signal
第103页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.16
Protocol configuration registers
8.16.1
TxBitMod
Table 200. TxBitMod register (address 48h)
Bit
7
6
5
4
3
2
1
0
Symbol
TxMSBFirst
RFU
TxParity
Type
RFU
TxStopBitType
RFU
TxStartBitType
TxStartBitEn
Access
rights
r/w
–
r/w
–
r/w
–
r/w
r/w
Table 201. TxBitMod bits
Bit
Symbol
Description
7
TxMSBFirst
If set, data is interpreted MSB first for data transmission. If cleared,
data is interpreted LSB first.
6
5
RFU
–
TxParityType Defines
the type of the pari
y bit. If set to 1, odd parity is calculated,
otherwise even parity is calculated.
4
3
2
1
0
RFU
TxStopBitType Defines
the type of the stop-bit (0b: logic zero / 1b: logic one).
RFU
TxStartBitType Defines
the type of the start-bit (0b: logic zero / 1b: logic one).
TxStartBitEn If
set to 1, a start-bit will be sent.
–
–
8.16.2
TxDataCon
Table 202. TxDataCon (address 4Ah)
Bit
7
6
5
4
3
2
1
0
Symbol
deType
r/w
DSCFreq
r/w
DBFreq
r/w
Access
rights
第104页,共139页
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High performance multi-protocol NFC frontend
Table 203. TxDataCon bits
Bit
Symbol
Description
7 to 4
DCodeType
Specifies the type of encoding of data to be used:
0h – no special coding
1h – collider datastream is decoded
2h – RFU 3h – RFU
4h – return to zero code – pulse at first position
5h – return to zero code – pulse at 2n
d
p
osition
6h – return to zero code – pulse at 3rd position
7h – return to zero code – pulse at 4th position
8h – 1 out of 4 coding
9h – 1 out of 256 code (range 0 – 255) [ICODE SLI]
Ah – 1 out of 256 code (range 0 – 255; 00h is encoded with no
modulation, value 256 not used) [ICODE 1]
Bh – 1 out of 256 code (range 0 – 255; 00h is encoded with a pulse on
last position) [ICODE quite value]
Ch- Pulse internal encoded (PIE) [ISO/IEC 18000-3 mode 3/ EPC
Class-1HF]
Dh – RFU
Eh – RFU
Fh – RFU
3
DSCFreq
DBFreq
Specifies the subcarrier
equency of the used envelope.
0h – 424 kHz
1h – 848 kHz
Note: Th
s setting is only relevant, if an envelope is used which
involves a subcarrier, e.g. Manchester with subcarrier coding.
2 to 0
Sp
cifies the frequency of the bitstream:
0h – RFU
1h – RFU
2h – 26 kHz
3h – 53 kHz
4h – 106 kHz
5h – 212 kHz
6h – 424 kHz
7h – 848 kHz
8.16.3
TxDataMod
Table 204. TxDataMod register (address 4Bh)
Bit
7
F
ame step
r/w
6
5
4
3
2
1
0
Symbol
DMillerEn
r/w
DPulseType
DInvert
r/w
DEnvType
r/w
Access
rights
r/w
第105页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 205. TxDataMod bits
Bit
Symbol
Description
7
Framestep
If set to 1, at every start of transmission, each byte of data is sent in a
separate frame. SOF and EOF are appended to the data byte
according to the framing settings. After one byte is transmitted, the
TxEncoder waits for a new start trigger to continue with the next byte
(trigger is generated automatically). If set to 0, transmission is done in
the used way, where after a start trigger all data bytes are sent and the
framing is done for the complete data stream only once.
6
DMillerEn
If set, pulse modulation is applied according to modified miller code.
Note: This bit is intended to be set if DPulseType is
Specifies which type of pulse modulation is selected.
0h – no pulse modulation
5 to 4
DPulseType
1h – pulse starts at beginning of bit
2h – pulse starts at beginning of second bit half
3h – pulse starts at beginning o
bit quarter
Note: If DMillerEn is set, DPulseType must be set to 1h.
If set the envelope of data is inverted.
3
DInvert
2 to 0
DEnvType
Specifies the type of e
ope used for transmission of data packets.
The selected envelope type is applied to the pseudo bit stream.
0h – Direct output
1h – Manchester code
2h – Manchester code with subcarrier
3h
PSK
4h – RZ (pulse of half bit length at beginning of second half of bit)
5h – RZ (pulse of half bit length at beginning of bit)
6h – RFU
7h – RFU
8.16.4
TxSymF
q
Table 206. TxSymFreq (address 4Ch)
Bit
7
S32S
Freq
r/w
6
5
4
3
S10SCFreq
r/w
2
1
0
Symbol
S32BFreq
r/w
S10BFreq
r/w
Access
rights
第106页,共139页
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High performance multi-protocol NFC frontend
Table 207. TxSymFreq bits
Bit
Symbol
Description
7
S32SCFreq
Specifies the frequency of the subcarrier of symbol2 and symbol3:
0b … 424 kHz
1b … 848 kHz
6 to 4
S32BFreq
Specifies the frequency of the bit stream of symbol2 and symbol3:
000b … RFU
001b … RFU
010b … 26 kHz
011b … 53 kHz
100b … 106 kHz
101b … 212 kHz
110b … 424 kHz
111b … 848 kHz
3
S10SCFreq
S10BFreq
Specifies the frequency of the subcarrier of symbol0 and symbol1:
0b …424 kHz
1b …848 kHz
2 to 0
Specifies the frequency of the b
eam of symbol0 and symbol1:
000b … RFU
001b … RFU
010b … 26 kHz
011b … 53 kHz
100b … 106 kHz
101b … 212 kHz
110b … 424 kHz
111b … 848 kHz
8.16.5
TxSym0
The two Registers TxSym0H and TxSym0L create a 16-bit register that contains the
pattern for Symbol0.
Table 208. TxSym0H (address 4Dh)
Bit
7
6
5
4
3
2
1
0
Symbol
Symbol0_H
r/w
Access
rights
Table 209. TxSYM0H bits
Bit
Symbol
Description
Higher 8 bits of symbol definition for Symbol0.
7 to 0
Symbol0H
Table 210. TxSym0L (address 4Eh)
Bit
7
6
5
4
3
2
1
0
Symbol
Symbol0_L
r/w
Access
rights
Table 211. TxSYM0L bits
Bit
Symbol
Description
7 to 0
Symbol0 L
Lower 8 bits of symbol definition for Symbol0
第107页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.16.6
TxSym
The two Registers TxSym1H and TxSym1L create a 16 bit register that contains the
pattern for Symbol1.
Table 212. TxSym1H (address 4Fh)
Bit
7
6
5
4
3
2
1
0
Symbol
Symbol1_H
r/w
Access
rights
Table 213. TxSym1H bits
Bit
Symbol
Description
Higher 8 bits of symbol definition for Symbol1.
7 to 0
Symbol1_H
Table 214. TxSym1L (address 50h)
Bit
7
6
5
4
3
2
1
0
Symbol
Symbol1_L
r/w
Access
rights
Table 215. TxSym1L bits
Bit
Symbol
Descript
on
Lower 8 bits of symbol definition for Symbol1.
7 to 0
Symbol1_L
8.16.7
TxSym2
Table 216. TxSYM2 (address 51h)
Bit
7
6
5
4
3
2
1
0
Symbol
Symbol2
r/w
Access
rights
Table 217. TxSym2 bits
Bit
Symbol
Description
Symbol definition for Symbol2.
7 to 0
Symbol2
8.16.8
TxSym3
Table 218. TxSym3 (address 52h)
Bit
7
6
5
4
3
2
1
0
Symbol
Symbol3
r/w
Access
rights
Table 219. TxSym3 bits
Bit
Symbol
Description
7 to 0
Symbol3
Symbol definition for Symbol3.
第108页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.16.9
TxSym10Len
Table 220. TxSym10Len (address 53h)
Bit
7
6
5
4
3
2
1
0
Symbol
Sym1Len
r/w
Sym0Len
r/w
Access
rights
Table 221. TxSym10Len bits
Bit
Symbol
Description
7 to 4
Sym1Len
Specifies the number of valid bits of the symbol def
n of Symbol1.
The range is from 1 bit (0h) to 16 bits (Fh).
3 to 0
Sym0Len
Specifies the number of valid bits of the symbol definition of Symbol0.
The range is from 1 bit (0h) to 16 bits (Fh
.
8.16.10
TxSym32Len
Table 222. TxSym32Len (address 54h)
Bit
7
RFU
–
6
5
4
R
–
2
1
0
Symbol
Sym3Len
r/w
Sym2Len
r/w
Access
rights
r/w
r/w
r/w
r/w
Table 223. TxSym32Len bits
Bit
7
Symbol
RFU
De
cription
–
6 to 4
Sym3Len
Specifies the number of valid bits of the symbol definition of Symbol3.
The range is from 1 bit (0h) to 8 bits (7h).
3
RFU
–
2 to 0
ym2Len
Specifies the number of valid bits of the symbol definition of Symbol2.
The range is from 1 bit (0h) to 8 bits (7h).
8.16.11
TxSym10BurstCtrl
Table 224. TxSym10
u
stCtrl register (address 55h)
Bit
7
6
5
4
3
2
1
0
Symbol
RFU Sym1BurstType Sym1BurstOnly
Sym1BurstEn RFU Sym0Burst Sym0BurstO
Sym0Burst
Type
nly
En
Access
rights
–
r/w r/w
r/w
–
r/w
r/w
r/w
Table 225. TxSym10BurstCtrl bits
Bit
7
Symbol
Description
RFU
–
6
Sym1BurstType
Specifies the type of the burst of Symbol1 (logical zero / logical
one).
5
Sym1BurstOnly
If set to 1 Symbol1 consists only of a burst and no symbol
pattern.
第109页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 225. TxSym10BurstCtrl bits
…continued
Bit
Symbol
Description
4
Sym1BurstEn
Enables the burst of symbol 1 of the length defined in
TxSym10BurstLen.
3
2
RFU
–
Sym0BurstType
Specifies the type of the burst of symbol 0 (logical zero / logical
one).
1
0
Sym0BurstOnly
Sym0BurstEn
If set to 1, symbol 0 consists only of a burst and no symbol
pattern.
Enables the burst of symbol 0 of the length d
d in
TxSym10BurstLen.
8.16.12
TxSym10Mod Reg
Table 226. TxSym10Mod register (address 56h)
Bit
7
RFU
–
6
S10MillerEn
r/w
5
4
3
2
1
S10EnvType
r/w
0
Symbol
S10PulseType
r/w
S10Inv
r/w
Access
rights
Table 227. TxSym10Mod bits
Bit
7
Symbol
RFU
Description
–
6
S10MillerEn
If s
, pulse modulation is applied according to modified miller code.
Note: This bit shall be set only if S10PulseType is set to 1h.
5 to 4
S10PulseType Specifies
which type of pulse modulation is selected:
0h – no pulse modulation
1h – pulse starts at beginning of bit
2h – pulse starts at beginning of second bit half
3h – pulse starts at beginning of third bit quarter
3
S10Inv
If set. the output of Symbol0 and Symbol1 is inverted.
2 to 0
S10EnvType Specifies
the type of envelope used for transmission of Symbol0 and
Symbol1. The pseudo bit stream is logically combined with the
selected envelope type.
0h – Direct output
1h – Manchester code
2h – Manchester code with subcarrier
3h – BPKSK
4h – RZ return zero, pulse of half bit length at beginning of second half
of bit
5h – RZ return zero, pulse of half bit length at beginning of second half
of bit
6h – RFU
7h – RFU
第110页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.16.13
TxSym32Mod
Table 228. TxSym32Mod register (address 57h)
Bit
7
RFU
–
6
S32MillerEn
r/w
5
4
3
2
1
S32EnvType
r/w
0
Symbol
S32PulseType
r/w
S32Inv
r/w
Access
rights
Table 229. TxSym32Mod bits
Bit
7
Symbol
RFU
Description
–
6
S32MillerEn
If set, pulse modulation is applied according to modified miller code.
Note: This bit shall be set only if S32PulseType is set to 1h.
5 to 4
S32PulseType Specifies
which type of pulse modulation is selected:
0h – no pulse modulation
1h – pulse starts at beginning of bit
2h – pulse starts at beginning of second bit half
3h – pulse starts at be
ng of third bit quarter
3
S32Inv
If set. the output of Symbol2 and Symbol3 is inverted.
2 to 0
S32EnvType Specifies
the type of envelope used for transmission of symbol 0 and
symbol 1. The bit stream is logically combined with the selected
envelope type.
0h – Direct output
1h
Manchester code
2h – Manchester code with subcarrier
3h – BPSK
4h – RZ return zero, pulse of half bit length at beginning of second half
of bit)
5h – RZ return zero, pulse of half bit length at beginning of bit)
6h to 7h RFU
8.17
Receiver configuration
8.17.1
RxBitMod
Table 230. RxBitMod (address 58h)
Bit
7
RFU
–
6
5
4
3
RxMSBFirst
r/w
2
1
0
Symbol
RFU RxStopOnInvPar RxStopOnLength
r/w r/w
RxStopBitEn RxParityType
RFU
r/w r/w
Access
rights
–
–
第111页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 231. RxBitMod bits
Bit
Symbol
Description
7 to 6
RFU
–
5
4
RxStopOnInvPar
RxStopOnLength
If set to 1, inverse parity bit is a stop condition.
If set to 1, data reception stops when the number of received
bytes reach the defined frame length. The value for the frame
length is taken from the first data-byte received.
3
2
RxMSBFirst
RxStopBitEn
If set to 1, data bytes are interpreted MSB first for data
reception, which means data is converted at the CLCoPro
interface. If this bit is set to 0, data is inter
ed LSB first.
If set, a stop-bit is expected and will be checked and
extracted from data stream. Additionally on detection of a
stop-bit a reset signal for the demodulator is generator to
enable a resynchronization of the demodulator. If the
expected stop-bit is incorrect, a frame error flag is set and the
reception is aborted.
Note: A stop bit is alw
onsidered to be a logic 1
1
0
RxParityType
RFU
Defines which type of the parity-bit is calculated:
If cleared: Ev
parity
If set: Odd par
–
8.17.2
RxEofSym
Table 232. RxEofSym (address 59h)
Bit
7
6
5
4
3
2
1
0
Symbol
RxEOFSymbol
r/w
Access
rights
Table 233. RxEOFSym bits
Bit
Symbol
Description
7 to 0
RxEOF
Symbol
This value defines the pattern of the EOF symbol with a maximum
length of 4 bit. Every tuple of 2 bits of the RxEOFSymbol encodes one
bit of the EOF symbol. A 00 tuple closes the symbol. In this way
symbols with less than 4 bits can be defined, starting with the bit0 and
bit1. The leftmost active symbol pattern is processed first, which
means the pattern is expected first. If the bit0 and bit1 are both zero,
the EOF symbol is disabled. The following mapping is defined:
0h – no symbol bit
1h – zero value
2h – one value
3h – collision
Example:
1Dh: Zero-Collision-Zero
E8h: No symbol because two LSBits are zero
第112页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.17.3
RxSyncValH
Table 234. RxSyncValH register (address5Ah)
Bit
7
6
5
4
3
2
1
0
Symbol
RxSyncValH
r/w
Access
rights
Table 235. RxSyncValH bits
Bit
Symbol
Description
15 to 0
RxSyncValH
Defines the high byte of the Start Of Frame (SOF)
rn, which must
be in front of the receiving data.
8.17.4
RxSyncValL
Table 236. RxSyncValL register (address 5Bh)
Bit
7
6
5
4
3
2
1
0
Symbol
RxSyncValL
r/w
Access
rights
Table 237. RxSyncValL bits
Bit
Symbol
Descript
on
7 to 0
RxSyncValL
Defines the low byte of the Start Of Frame (SOF) Pattern, which must
be
n fr
nt of the receiving data.
8.17.5
RxSyncMod
Table 238. RxSyncMode register (add
5Ch)
Bit
7
6
4
3
SyncNegEdge
r/w
2
LastSyncHalf
r/w
1
0
Symbol
SyncLen
r/w
SyncType
r/w
Access
rights
able 239. RxSyncMod bits
Bit
Symbol
Description
7 to 4
SyncLen
Defines how many Bits of registers RxSyncValH and RxSyncValL are
valid. For ISO/IEC 14443B set to 0.
3
SyncNegEdge Is
used for SOF with no correlation peak. The first negative edge of the
correlation is used for defining the bit grid.
2
LastSyncHalf The
last Bit of the Sync mode has only half of the length compared to
all other bits. (ISO/IEC 18000-3 mode 3/ EPC Class-1HF).
1 to 0
SyncType
0: all 16 bits of SyncVal are interpreted as burst.
1: a nibble of bits is interpreted as one bit in following way:
{data, coll} data = zero or one; coll = 1 means a collision on this bit.
Note: if Coll = 1 the value of data is ignored.
2: the synchronization is done at every start bit of each byte (type B)
3: RFU
s.
第113页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.17.6
RxMod
Table 240. RxMod register (address 5Dh)
Bit
7
RFU
–
6
RFU
–
5
4
3
2
1
0
Symbol
PreFilter
r/w
RectFilter
r/w
SyncHigh CorrInv
r/w r/w
FSK
r/w
BPSK
r/w
Access
rights
Table 241. RxMod bits
Bit
Symbol
–
Description
7 to 6
RFU
5
4
3
PreFilter
RectFilter
SyncHigh
If set 4 samples are combined to one data. (average).
If set, the ADC-values are changed to a more rectangular wave shape.
Defines if the bit grid is fixed at maximum (1) or at minimum (0) value
of the correlation.
2
CorrInv
Defines a logical for Manchester
ding:
0: subcarrier / no subcarrie
.
1
0
FSK
If set to 1, the demod
n scheme is set to FSK.
If set to 1, the modulation scheme is BPSK.
BPSK
8.17.7
RxCorr
Table 242. RxCorr register (address 5Eh)
Bit
7
6
5
4
3
2
1
0
Symbol
CorrFreq
CorrSpeed
CorrLen
r/w
RFU
–
Access
rights
r/w
r/w
r/w
r/w
Table 243
xCorr bits
Bit
Symbol
Description
0h – 212 kHz
1h – 424 kHz
2h – 848 kHz
3h – 848 kHz
7, 6
CorrFreq
5, 4
CorrSpeed
Defines the number of clocks used for one correlation.
0h – ISO/IEC 14443
1h – ICODE 53 kBd, FeliCa 424 kBd
2h – ICODE 26 kBd, FeliCa 212 kBd
3h – RFU
3
CorrLen
RFU
Defines the length of the correlation data. (64 or 32 values).
If set the lengths of the correlation data is 32 values. (ISO/IEC 18000-3
mode 3/ EPC Class-1HF, 2 Pulse Manchester 848 kHz subcarrier).
2 to 0
–
第114页,共139页
JSM66302
High performance multi-protocol NFC frontend
8.17.8
FabCali
Table 244. FabCali register (address 5Fh)
Bit
7
6
5
4
3
2
1
0
Symbol
FabCali
r/w
Access
rights
Table 245. FabCali bits
Bit
Symbol
Description
7 to 0
FabCali
Fabrication calibration of the receiver.
NOTE: do not change boot value.
8.18
Version register
8.18.1
Version
Table 246. Version register (address 7Fh)
Bit
7
6
5
4
3
2
1
0
Symbol
Version
r
SubVersion
r
Access
rights
Table 247. Version bits
Bit
Symbol
Description
7 to 4
Version
Includes the version of the JSM66302 silicon.
JSM66302: 1
3 to 0
ubV
ion
Includes the subversion of the JSM66302 silicon.
JSM66302: 8 -No difference of the silicon between versions
第115页,共139页
JSM66302
High performance multi-protocol NFC frontend
9.
Limiting values
Table 248. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DD
Parameter
Conditions
JSM66302
per package
Min
0.5
0.5
0.5
–
Max
+ 6.0
+ 6.0
+ 6.0
250
Unit
V
supply voltage
V
DD(PVDD)
V
DD(TVDD)
I
DD(TVDD)
PVDD supply voltage
TVDD supply voltage
TVDD supply current
V
V
mA
V
i(RXP)
V
i(RXN)
P
tot
input voltage on pin RXP
input voltage on pin RXN
total power dissipation
0.5
0.5
–
+ 2.0
+ 2.0
1125
2000
V
V
mW
V
V
ESD
(HBM)
electrostatic discharge voltage
Human Body Model (HBM);
2000
1500
, 100 pF;
JESD22-A114-B
V
ESD
(CDM)
T
j(max)
electrostatic discharge voltage
Charge Device Model (CDM);
-500
–
500
125
V
maximum junction
temperature
°C
T
stg
storage temperature
no supply voltage applied
55
+150
°C
10.
Recommended operating conditions
Exposure of the device to other conditions than specified in the Recommended Operating
Conditions section for extended periods may affect device reliability.
Electrical par
ters (minimum, typical and maximum) of the device are guaranteed only
when it is
sed
in the recommended operating conditions.
Table 249. Operating condit
ons JSM66302
Symbol
Parameter
Conditions
Min
3.0
3.0
3.0
25
Typ
5.0
5.0
5.0
+25
Max Unit
V
DD
supply vo
tage
5.5
5.5
5.5
+85
V
V
DD(TVDD)
TVDD s
pply voltage
V
DD(PVDD)
PVDD supply voltage
V
V
T
amb
operating ambient
tem
erature
in still air with exposed pin soldered on a
4 layer JEDEC PCB
C
storage temperature
no supply voltage applied, relative humidity
45…75%
-40
+25
+125
C
T
stg
[1] V
DD(PVDD)
must always be the same or lower than V
DD
.
第116页,共139页
JSM66302
High performance multi-protocol NFC frontend
11.
Thermal characteristics
Table 251. Thermal characteristics
Symbol Parameter
Conditions
Package Typ
Unit
R
th(j-a)
thermal resistance from junction to
ambient
in still air with exposed pin soldered on a
4 layer JEDEC PCB
HVQFN32 40
K/W
12.
Characteristics
Table 252. Characteristics
Symbol Parameter
Current consumption
Conditions
Min
Typ
Max
Unit
supply current
I
DD
= A
VDD
+D
VDD;
modem
on (transmitter and
–
17
20
mA
I
DD
receiver are switched on)
I
DD
= A
VDD
+D
VDD
; modem
off (transmitter and receiver
are switched off)
–
0.45
0.5
mA
I
DD(PVDD)
PVDD supply current
I
DD(TVDD)
TVDD supply current
no load on digital pins,
leakage current only
–
0.5
5
A
JSM66302,
100
250
mA
I
pd
power-down current
All OUTx pins floating
ambient temp = +25 °C
–
–
40
400
2.1
nA
ambient temp =
-40°C…+85°C
1.5
A
I
stby
standby current
All OUTx pins floating
ambient temp = 25 °C,
I
VDD
+I
TVDD
+ I
PVDD
–
–
3
6
A
ambient temp =
5.25
26
-40°C…+105°C, I
stby
I
VDD
+I
TVDD
+ I
PVDD
=
第117页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 252. Characteristics
…continued
Symbol Parameter
Conditions
Min
Typ
Max
Unit
I
LPCD(sleep
LPCD sleep current
All OUTx pins floating
)
LFO active, no RF field on,
ambient temp = 25 °C
–
3.3
6.3
A
I
LPCD(aver
LPCD average current
All OUTx pins floating,
TxLoad = 50 ohms.
age)
LPCD_FILTER = 0; Rfon
duration = 10 us, RF-off
duration 300ms; V
TVDD
=
3.0V; T
amb
= 25°C; I
LPCD
I
VDD
+I
TVDD
+ I
PVDD
=
LPCD_TX_HIGH = 0,
LPCD_TX_HIGH = 1
–
–
–
12
23
10
–
–
–
A
s
t
RFON
RF-on time during LPCD
LPCD_TX_HIGH = 0;
TVDD=5.0 V
T=25C;
LPCD_TX_HIGH = 1;
TVDD=5.0 V; T=25C
–
50
–
s
Buffer capacitors on AVDD,DVDD
C
L
C
L
external buffer capacitor
AVDD
external buffer capacitor
DVDD
220
220
470
470
–
–
nF
nF
I/O pin characteristics SIGIN/OUT7, SIGOUT, CLKOUT/OUT6,
IFSEL0/OUT4, IFSEL1/OUT5, TCK/OUT3, TMS/OUT2,
TDI/OUT1, TDO/OUT0, IRQ, IF0, IF1, IF2, SCL2, SDA
I
LI
input leakage current
low-level input voltage
high-level input voltage
output disabled
0.0
50
–
500
nA
V
V
IL
V
IH
0.5
0.3 x V
DD(PVDD)
0.7 x
V
V
DD(PV
V
DD(PVDD)
+ 0.5
V
DD(PVDD)
DD)
V
OL
V
OH
low-level output voltage
0.0
0.0
0.4
V
V
high-level output voltage
If pins are used as output
OUTx, I
OH
= 4 mA driving
V
DD(PVDD)
-0.4
V
DD(PV
V
DD(PVDD)
DD)
current for each pin
C
i
input capacitance
0.0
2.5
4.5
0.4
pF
Pin characteristics PDOWN
low-level i
put voltage
high-
evel input voltage
0.0
0.0
V
V
V
IL
V
IH
0.6 x V
PVDD
V
DD(PV
V
DD(PVDD)
DD)
Pull-up resistance for TCK, TMS, TDI, IF2
R
pu
pull-up resistance
Pin characteristics AUX 1, AUX 2
50
72
120
K
V
o
C
L
output voltage
0.0
0.0
–
–
1.8
V
load capacitance
400
pF
Pin characteristics RXP, RXN
V
pp
C
i
input voltage
0
2
1.65
3.5
1.8
5
V
input capacitance
pF
第118页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 252. Characteristics
…continued
Symbol Parameter
Conditions
Min
Typ
Max
Unit
V
mod(pp)
modulation voltage
V
mod(pp)
= V
i(pp)(max)
V
i(pp)
–
2.5
–
mV
(min)
Pins TX1 and TX2
V
o
R
o
output voltage
V
ss(TVSS)
–
–
V
DD(TVDD)
–
V
output resistance
JSM66302:
1.5
T=25°C, V
DD(TVDD)
= 5.0V
Clock frequency Pin CLKOUT
f
clk
clock frequency
clock duty cycle
configured to 27.12 MHz
pin XTAL1
–
–
27.12
50
–
–
MHz
%
clk
Crystal connection XTAL1, XTAL2
V
o(p-p)
peak-to-peak output
voltage
–
1.0
–
V
V
i
C
i
input voltage
pin XTAL1
pin XTAL1
0.0
–
1.8
–
V
input capacitance
3
pF
Crystal requirements
f
xtal
crystal frequency
ISO/IEC14443 compliancy
27.12-14kHz 27.12
27.12+14kHz
MHz
ESR
equivalent series
resistance
–
50
100
C
L
load capacitance
–
–
10
50
–
pF
P
xtal
crystal power dissipation
100
W
Input characteristics I/O Pin Characteristics IF3-SDA in I
2
C configuration
I
LI
input leakage current
LOW-level input voltage
HIGH-level input volta
output disabled
–
2
–
100
nA
V
V
IL
V
IH
V
OL
I
OL
0.5
+0.3 V
DD(PVDD)
0.7 V
DD(PVDD)
–
V
DD(PVDD)
+ 0.5
V
LOW-level output voltage
I
OL
= 3 mA
–
–
0.3
–
V
LOW-level output curren
V
OL
= 0.4 V; Standard
mode, Fast mode
4
–
mA
V
OL
= 0.6 V; Standard
mode, Fast mode
6
–
–
–
–
mA
ns
t
f(o)
output fall
ime
Standard mode, Fast
mode, C
L
< 400 pF
250
Fast mode +; C
L
< 550 pF
–
–
–
120
50
ns
ns
t
SP
pulse width of spikes that
must be suppressed by
the input filter
0
C
i
input capacitance
–
3.5
5
pF
第119页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 252. Characteristics
…continued
Symbol Parameter
Conditions
Standard mode
Fast mode
Min
Typ
Max
400
550
–
Unit
pF
C
L
load capacitance
–
–
–
–
–
pF
t
EER
EEPROM data retention
T
amb
= +55
°
C
10
year
time
N
EEC
EEPROM endurance
under all operating
5 x 10
5
–
–
cycle
(number of programming
conditions
cycles)
[1]
I
pd
is the total current for all supplies.
[2]
I
DD(PVDD)
depends on the overall load at the digital pins.
V
mod
V
V
i(p-p)(min)
i(p-p)
VMID
13.56 MHz
carrier
0 V
001aak012
Fig 34. Pin RX input voltage
12.1
Timing ch
eristics
Table 253.
PI timing characteristics
Symbol
t
SCKL
Parameter
Conditions
Min Typ Max
Unit
SCK LOW time
SCK HIGH time
50
50
25
–
–
–
–
–
–
ns
ns
ns
t
SCKH
t
h(SCKH-D)
SCK HIGH to data input hold
SCK to changing MOSI
time
t
su(D-SCKH)
t
h(SCKL-Q)
data input to SCK HIGH
set-up time
changing MOSI to SCK
25
–
–
–
–
–
–
ns
ns
ns
ns
SCK LOW to data output
hold time
SCK to changing MISO
25
–
t
(SCKL-NSSH)
SCK LOW to NSS HIGH
time
0
t
NSSH
NSS HIGH time
before communication
50
–
Remark:
To send more bytes in one data stream, the NSS signal must be LOW during
the send process. To send more than one data stream, the NSS signal must be HIGH
between each data stream.
第120页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 254. I
2
C-bus timing in fast mode and fast mode plus
Symbol Parameter
Conditions
Fast mode
Fast mode
Unit
Plus
Min Max
Min Max
f
SCL
SCL clock frequency
0
400
–
0
1000 kHz
hold time (repeated) START
condition
after this period,
the first clock pulse
is generated
600
260
–
ns
t
HD;STA
t
SU;STA
set-up time for a repeated
START condition
600
–
260
–
ns
t
SU;STO
set-up time for STOP condition
600
1300
600
0
–
260
–
–
–
ns
ns
ns
t
LOW
LOW period of the SCL clock
HIGH period of the SCL clock
data hold time
–
500
t
HIGH
–
260
900
–
–
–
–
–
–
450 ns
–
ns
t
HD;DAT
t
SU;DAT
data set-up time
100
20
t
r
t
f
t
r
rise time
fall time
rise time
SCL signal
SCL signal
300
300
300
120 ns
120 ns
120 ns
20
SDA
SCL
signals
20
t
f
fall time
SDA and SCL
signals
20
300
–
–
120 ns
bus free time between a STOP
and START condition
1.3
0.5
–
s
t
BUF
SDA
SCL
t
t
SP
SU;DAT
t
r
t
t
t
t
f
LOW
HD;STA
BUF
t
t
SU;STO
t
r
HIGH
t
t
SU;STA
HD;STA
t
HD;DAT
S
Sr
P
S
001aaj635
Fig 35. Timing for fast and standard mode devices on the I
2
C-bus
第121页,共139页
JSM66302
High performance multi-protocol NFC frontend
13.
Application information
A typical application diagram using a complementary antenna connection to the JSM66302
The antenna tuning and RF part matching is described in the application note Ref. 1 and
Ref. 2.
VDD
PVDD
25
TVDD
18
8
C
C
RXN
AVDD
RXN
9
13
14
R1
VMID
vmid
R2
PDOWN
21
C1
C1
L0
Ra
C2
TX1
TVSS
TX2
host
interfac e
17
16
antenna
Lant
READER IC
C0
C0
MICRO-
PROCESSOR
28-31
C2
Ra
IRQ
32
L0
15
14
12
DVDD
7
RXP
R3
R4
33
VSS XTAL1
27.12 MHz
19
20
XTAL2
C
RXP
001aam269
Fig 36. Typical application antenna circuit diagram
13.1
Antenn
design description
The matching circuit for the antenna consists of an EMC low pass filter (L0 and C0), a
matching
ircuitry (C1 and C2), and a receiving circuits (R1 = R3, R2 = R4, C3 = C5 and
C4 = C6;), and the antenna itself. The receiving circuit component values need to be
designed for operation with the JSM66302. A re-use of dedicated antenna designs done
or other products without adaptation of component values will result in degraded
performance.
For a more detailed information about designing and tuning the antenna, refer to the
relevant application notes:
•
•
MICORE reader IC family; Directly Matched Antenna Design, Ref. 1 and
MIFARE (14443A) 13.56 MHz RFID Proximity Antennas, Ref. 2.
第122页,共139页
JSM66302
High performance multi-protocol NFC frontend
13.1.1
EMC low pass filter
The MIFARE system operates at a frequency of 13.56 MHz. This frequency is derived
from a quartz oscillator to clock the JSM66302 and is also the basis for driving the
antenna with the 13.56 MHz energy carrier. This will not only cause emitted power at
13.56 MHz but will also emit power at higher harmonics. The international EMC
regulations define the amplitude of the emitted power in a broad frequency range. Thus,
an appropriate filtering of the output signal is necessary to fulfill these regulations.
Remark:
The PCB layout has a major influence on the overall performance of the filter.
13.1.2
Antenna matching
Due to the impedance transformation of the given low pass filter, the antenna coil has to
be matched to a certain impedance. The matching elements C1 and C2 can be estimated
and have to be fine-tuned depending on the design of the antenna coil.
The correct impedance matching is important to provid
the optimum performance. The
overall quality factor has to be considered to guarante
proper ISO/IEC 14443
communication scheme. Environmental influences have to be considered as well as
common EMC design rules.
13.1.3
Receiving circuit
The internal receiving concept of the JSM66302 makes use both side-bands of the
subcarrier load modulation o
he card response via a differential receiving concept (RXP,
RXN). No external filtering is required.
It is recommended using the internally generated VMID potential as the input potential of
pin RX. This DC voltage level of VMID has to be coupled to the Rx-pins via R2 and R4. To
provide a sta
C reference voltage capacitances C4, C6 has to be connected between
Con
idering the (AC) voltage limits at the Rx-pins the AC voltage divider of R1 + C3 and
R2 as well as R3 + C5 and R4 has to be designed. Depending on the antenna coil design
and the impedance matching, the voltage at the antenna coil varies from antenna design
to antenna design. Therefore the recommended way to design the receiving circuit is to
use the given values for R1(= R3), R2 (= R4), and C3 (= C5) from the above mentioned
application note, and adjust the voltage at the RX-pins by varying R1(= R3) within the
given limits.
Remark:
R2 and R4 are AC-wise connected to ground (via C4 and C6).
第123页,共139页
JSM66302
High performance multi-protocol NFC frontend
13.1.4
Antenna coil
The precise calculation of the antenna coils’ inductance is not practicable but the
inductance can be
estimated
using the following formula. We recommend designing an
antenna either with a circular or rectangular shape.
I
1
1
8
L
1
=
2
I
1
ln
–
K N
1
(4)
•
•
•
I
1
– Length in cm of one turn of the conductor loop
D
1
– Diameter of the wire or width of the PCB conductor respectivel
K – Antenna shape factor (K = 1.07 for circular antennas and K = 1.47 fo
r
s
quare
antennas)
•
•
•
L
1
– Inductance in nH
N
1
– Number of turns
Ln: Natural logarithm function
The actual values of the
antenna inductance, resistance, and capacitance at
13.56
MHz
depend on various parameters su
s:
•
•
•
•
•
antenna construction (Type of PCB)
thickness of conductor
distance between the windings
shielding layer
metal or ferrite in the near environment
Therefore a measurement of those parameters under real life conditions, or at least a
rough measu
nt and a tuning procedure are highly recommended to guarantee a
reasonab
pe
ance. For details, refer to the above mentioned applicationnotes.
第124页,共139页
JSM66302
High performance multi-protocol NFC frontend
14.
Package outline
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
B
A
D
terminal 1
index area
A
A
1
E
c
detail X
C
e
1
y
C
1
y
e
1/2
e
b
v
M
M
C
C
A
B
w
9
16
L
17
8
e
e
E
h
2
1/2
e
1
24
terminal 1
index area
32
25
X
D
h
0
2.5
5 mm
scale
DIMENSION
(mm are the original dimensions)
(1)
A
max.
(1)
(1)
UNIT
A
c
D
E
e
y
b
E
e
e
2
D
L
v
w
y
1
1
h
1
h
0.05 0.30
0.00 0.18
5.1
4.9
3.25
2.95
5.1
4.9
3.25
2.95
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
3.5
3.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
第125页,共139页
JSM66302
High performance multi-protocol NFC frontend
15.
Handling information
Moisture Sensitivity Level (MSL) evaluation has been performed according to
SNW-FQ-225B rev.04/07/07 (JEDEC J-STD-020C)
. MSL for this package is level 2 which
means 260
C convection reflow temperature.
For MSL2:
•
•
Dry pack is required.
1 year out-of-pack floor life at maximum ambient temperature 30
C/ 85
%
R
H.
For MSL1:
•
•
No dry pack is required.
No out-of-pack floor live spec. required.
16.
Appendix
16.1
LoadProtocol command register initialization
The RF configuration is loaded with the comm
Load Protocol. The tables below show
the register configuration as performed by this command for each of th
e
p
rotocols.
Antenna specific configurations are not covered by this register settings.
The JSM66302 are not initialized for any antenna configuration. For this products the
antenna configuration need
to be done by firmware.
Table 255. IS
14443-A 106 / MIFARE
Value fo
ister
TxBi
Mod
Value (hex)
20
00
04
50
40
00
00
00
00
00
00
00
00
00
00
50
RFU
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
第126页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 255. ISO/IEC14443-A 106 / MIFARE
Value for register
RxBitMod
Value (hex)
02
00
00
01
00
08
80
B2
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
FabCal
Table 256.
ISO/IEC14443-A 212/ MIFARE
Value for register
TxBitMod
Value (hex)
20
RFU
00
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
05
50
00
TxSym0L
00
TxSym1H
00
TxSym1L
00
TxSym2
00
TxSym3
00
TxSym10Len
TxSym32
n
TxSym10
rstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
00
00
00
00
50
22
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
00
00
00
00
0D
80
RxCorr
FabCal
B2
Table 257.
ISO/IEC14443-A 424/ MIFARE
Value for register
TxBitMod
Value (hex)
20
00
06
RFU
TxDataCon
第127页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 257.
ISO/IEC14443-A 424/ MIFARE
Value for register
TxDataMod
TxSymFreq
TxSym0H
Value (hex)
50
60
00
00
00
00
00
00
00
00
00
00
50
22
00
00
00
0D
80
B2
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
FabCal
Table 258.
IS
C14443-A 848/ MIFARE
Value for
gis
TxBitMod
Value (hex)
20
00
07
50
70
00
00
00
00
00
00
00
00
00
00
50
22
RFU
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
第128页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 258. ISO/IEC14443-A 848/ MIFARE
Value for register
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
Value (hex)
00
00
00
00
0D
80
B2
RxCorr
FabCal
Table 259.
ISO/IEC14443-B 106
Value for register
TxBitMod
Value (hex)
09
00
04
08
00
03
00
01
00
00
AB
00
00
08
00
04
00
00
00
02
1D
RFU
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10
rst
TxSym10
od
TxSym32Mod
RxBitMod
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
FabCal
80
B2
Table 260.
ISO/IEC14443-B 212
Value for register
TxBitMod
Value (hex)
09
00
05
RFU
TxDataCon
第129页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 260.
ISO/IEC14443-B 212
Value for register
TxDataMod
TxSymFreq
TxSym0H
Value (hex)
08
05
00
03
00
01
00
00
AB
00
00
08
00
04
00
00
02
1D
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
FabCal
80
B2
Table 261.
ISO
4443-B 424
Value for
gister
TxBi
Mod
Value (hex)
09
00
06
08
06
00
03
00
01
00
00
AB
00
00
08
00
RFU
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
第130页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 261.
ISO/IEC14443-B 424
Value for register
RxBitMod
Value (hex)
04
00
00
00
02
1D
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
FabCal
80
B2
Table 262.
ISO/IEC14443-B 848
Value for register
TxBitMod
Value (he
09
00
08
07
00
03
00
01
00
00
AB
00
00
08
00
04
00
00
00
02
1D
RFU
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10
n
TxSym32
n
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
FabCal
80
B2
第131页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 263.
JIS X 6319-4 (FeliCa) 212
Value for register
TxBitMod
Value (hex)
80
RFU
00
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
05
01
05
B2
4D
00
TxSym0L
TxSym1H
TxSym1L
00
TxSym2
00
TxSym3
00
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
0F
00
01
00
18
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
00
B2
4D
F0
19
RxCorr
20
FabCal
B0
Tabl
264. JIS
X 6319-4 (FeliCa) 424
Value for register
TxBitMod
Value (hex)
80
00
06
01
06
B2
4D
00
00
00
00
0F
00
01
RFU
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
第132页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 264. JIS X 6319-4 (FeliCa) 424
Value for register
TxSym10Mod
TxSym32Mod
RxBitMod
Value (hex)
01
00
18
00
B2
4D
F0
19
50
B0
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
FabCal
Table 265. ISO/IEC15693 SLI 1/4 – SSC- 26
Value for register
TxBitMod
Value (hex
00
RFU
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
83
04
40
00
TxSym0L
00
TxSym1H
00
TxSym1L
00
TxSym2
84
TxSym3
02
TxSym10
n
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
00
37
00
00
00
00
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
1D
00
01
00
24
RxCorr
60
FabCal
F0
第133页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 266. ISO/IEC15693 SLI 1/4 – SSC- 53
Value for register
TxBitMod
Value (hex)
00
RFU
00
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
83
04
40
00
TxSym0L
00
TxSym1H
00
TxSym1L
00
TxSym2
84
TxSym3
02
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
00
37
00
00
00
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
1D
00
01
00
24
RxCorr
40
FabCal
F0
Table 267. SO/IEC15693 SLI 1/256 – DSC
Value for register
TxBitMod
Value (hex)
00
00
83
04
40
00
00
00
00
81
02
00
37
00
RFU
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
第134页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 267. SO/IEC15693 SLI 1/256 – DSC
Value for register
TxSym10Mod
TxSym32Mod
RxBitMod
Value (hex)
00
00
00
1D
00
01
00
26
60
F0
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
FabCal
Table 268. EPC/UID – SSC -26
Value for register
TxBitMod
Value (hex
80
RFU
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
44
00
44
08
TxSym0L
22
TxSym1H
08
TxSym1L
28
TxSym2
8A
02
TxSym3
TxSym10
n
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
BB
37
00
00
00
08
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
0B
00
00
08
04
RxCorr
50
FabCal
F0
第135页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 269.
Value for register
TxBitMod
Value (hex)
80
RFU
00
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
C5
00
05
68
TxSym0L
41
TxSym1H
01
TxSym1L
A1
00
TxSym2
TxSym3
00
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
8E
00
00
00
08
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
0B
00
01
04
0C
40
RxCorr
FabCal
F0
Table 270. EPC-V2 – 4/424
Value for register
TxBitMod
Value (hex)
80
00
C5
00
05
68
41
01
A1
00
00
8E
00
00
RFU
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
第136页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 270.
EPC-V2 – 4/424
Value for register
TxSym10Mod
TxSym32Mod
RxBitMod
Value (hex)
00
00
08
0B
00
01
04
0C
50
F0
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
FabCal
Table 271.
EPC-V2 – 2/848
Value for register
TxBitMod
Value (hex
80
RFU
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
C5
00
05
68
TxSym0L
41
TxSym1H
01
TxSym1L
A1
00
TxSym2
TxSym3
00
TxSym10
n
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
8E
00
00
00
00
08
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
0B
00
01
04
0C
88
RxCorr
FabCal
F0
第137页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 272. EPC-V2 – 4/848
Value for register
TxBitMod
Value (hex)
80
RFU
00
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
C5
00
05
68
TxSym0L
41
TxSym1H
01
TxSym1L
A1
00
TxSym2
TxSym3
00
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
8E
00
00
00
08
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
0B
00
01
04
0C
80
RxCorr
FabCal
F0
Table 273. Jewel
Value for register
TxBitMod
Value (hex)
00
00
04
D0
40
00
00
00
00
00
00
00
00
00
RFU
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
第138页,共139页
JSM66302
High performance multi-protocol NFC frontend
Table 273. Jewel
Value for register
TxSym10Mod
TxSym32Mod
RxBitMod
Value (hex)
00
50
02
00
00
01
00
08
80
F0
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
FabCal
第139页,共139页
