MATSUKI-ME50N75T

ME50N75T/ME50N75T-G  

N-Channel 75-V (D-S) MOSFET  

GENERAL DESCRIPTION  

FEATURES  

●

R

DS(ON)

≦

26m

Ω

@V

GS

=10V  

The ME50N75T is the N-Channel logic enhancement mode power  

field effect transistors are produced using high cell density, DMOS  

trench technology. This high density process is especially tailored to  

minimize on-state resistance.  

●

Super high density cell design for extremely low R

DS(ON)  

●

Exceptional on-resistance and maximum DC current  

capability  

APPLICATIONS  

●

Power Management  

●

DC/DC Converter  

●

Load Switch  

PIN CONFIGURATION  

(TO-220)  

T

o

p View  

e

Ordering Information

: ME50N75T (Pb-free)  

ME50N75T-G (Green product-Halogen free)  

Absolute Maximum Ratings

(T

C

=25

℃

Unless Otherwise Noted)  

Parameter  

Symbol  

V

DSS  

Limit  

75  

Unit  

V

Drain-Source Voltage  

Gate-Source Voltage  

V

GSS  

±25  

V

T

c

=25

℃

 

T

C

=70

℃  

50  

Continuous Drain Current  

Pulsed Drain Current  

I

D  

A

A

42  

I

DM  

P

D  

200  

T

C

=25

℃  

T

C

=70

℃  

150  

Maximum Power Dissipation  

W

℃

105  

Operating Junction and Storage

T

e

mperature Range  

T

J,

T

stg  

-55 to 175  

1

℃/W  

DCC  

R

θ

JC  

Thermal Resistance-Junction to Case

*  

* The device mounted on 1in

2

FR4 board with 2 oz copper.  

正式發行  

01  

Ma

y

, 2012-Ver1.1  

ME50N75T/ME50N75T-G  

N-Channel 75-V (D-S) MOSFET  

Electrical Characteristics

(T

A

=25

℃

Unless Otherwise Specified)  

Symbol  

STATIC  

BV

DSS  

V

GS(th)  

I

GSS  

Parameter  

Limit  

Min  

Typ  

Max  

Unit  

V

GS

=0

V

, I

D

=250

μ

A  

V

DS

=V

GS

, I

D

=250

μ

A  

V

DS

=0

V

, V

GS

=±20V  

V

DS

=75

V

,

V

GS

=0V  

V

GS

=10

V

, I

D

=30A  

I

S

=30A, V

GS

=0V  

Drain-Source Breakdown Voltage  

Gate Threshold Voltage  

75  

V

V

2.0  

4.0  

±100  

1

Gate-Body Leakage  

nA  

μ

A  

m

Ω  

V

I

DSS  

Zero Gate Voltage Drain Current  

Drain-Source On-Resistance*  

Diode Forward Voltage *  

R

DS(ON)  

V

SD  

22  

26  

0.9  

1.2  

DYNAMIC  

Qg  

T

o

tal Gate Charge  

T

o

tal Gate Charge  

Gate-Source Charge  

Gate-Drain Charge  

Gate Resistance  

V

DS

=48

V

,

V

GS

=10

V

, I

D

=50A  

V

DS

=48

V

,

V

GS

=4.5

V

,

I

D

=50A  

V

DS

=0

V

, V

GS

=0

V

, f=1MHz  

V

DS

=15

V

,

V

GS

=0

V

, f=1MHz  

38  

11  

13  

9

Qg  

nC  

Qgs  

Qgd  

Ω

Rg  

2

C

iss  

Input Capacitance  

Output Capacitance  

Reverse Transfer Capacitance  

Turn-On Delay Time  

Turn-On Rise Time  

Turn-Off Delay Time  

Turn-Off Fall Time  

2270  

189  

59  

28  

5

C

oss  

C

rss  

pF  

t

d(on)  

t

r  

V

DD

=30

V

,

R

L

=30

Ω

,  

V

GS

=10

V

,

R

G

=3.6

Ω  

ns  

51  

6

t

d(off)  

T

f  

Notes: a. pulse test: pulse width

≦

300us, duty cycle

≦

2%, Guaranteed by design, not subject to production testing.  

b. Matsuki Electric/ Force mos reserves the right to improve product design, functions and reliability without notice.  

DCC  

正式發行  

02  

Ma

y

, 2012-Ver1.1  

ME50N75T/ME50N75T-G  

N-Channel 75-V (D-S) MOSFET  

Typical Characteristics (T

J

=25

℃

Noted)  

DCC  

正式發行  

03  

Ma

y

, 2012-Ver1.1  

ME50N75T/ME50N75T-G  

N-Channel 75-V (D-S) MOSFET  

Typical Characteristics (T

J

=25

℃

Noted)  

DCC  

正式發行  

04  

Ma

y

, 2012-Ver1.1  

ME50N75T/ME50N75T-G  

N-Channel 75-V (D-S) MOSFET  

TO-220 Package Outline  

DCC  

正式發行  

05  

Ma

y

, 2012-Ver1.1