Microchip-Tech-2N6660
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2N6660
N-Channel, Enhancement-Mode,
V
e
rtical DMOS FET
Features
Description
• Free
from secondary breakdown
• Low
power drive requirement
• Ease
of paralleling
2N6660 is an enhancement-mode (normally-off) tran-
sistor that utilizes a vertical DMOS structure and a well-
proven silicon-gate manufacturing process. This com-
bination produces a device with the power-handling
capabilities of bipolar transistors, and the high input
impedance and positive temperature coefficient inher-
ent in MOS devices. Characteristic of all MOS struc-
tures, this device is free from thermal runaway and
thermally-induced secondary breakdown.
• Low
C
ISS
and fast switching speeds
• Excellent
thermal stability
• Integral
source-drain diode
• High
input impedance and high gain
Applications
Vertical DMOS FE
T
s
a
re ideally suited to a wide range
of switching and amplifying applications where very-
low threshold voltage, high breakdown voltage, high-
input impedance, low-input capacitance, and fast
switching speeds are desired.
• Motor
controls
• Converters
• Amplifiers
• Switches
• Power
supply circuits
• Drivers:
relays, hammers, solenoids, lamps,
memories, displays, bipolar transistors, etc.
Package Types
GATE
SOURCE
DRAIN
TO-39
Case: Drain
See
T
a
ble 2-1
for pin information
2016 Microchip Technology Inc.
DS20005509A-page 1
2N6660
1.0
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
†
Drain-to-source voltag
e
.
………………………………………………………………………………………………………………………
.
B
V
DSS
Drain-to-gate voltage……………………………………………………………………………………………………………………………BV
DGS
Gate-to-source voltage………………………………………………………………………………………………………………………….. ±20V
Operating and Storage
T
e
mperatur
e
.
…………………………………………………………………………………………… -55 to 150 °C
† Notice:
Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
ELECTRICAL CHARACTERISTICS
Electrical Specifications:
Unless otherwise specified, for all specifications T
A
= +25°C
Parameter
Symbol
Min
Typ
Max Units
Conditions
DC Parameters
(
Note 1
,
unless otherwise stated)
Drain-to-source breakdown voltage
Gate threshold voltage
BV
DSS
V
GS(th)
∆
V
GS(th)
I
GSS
60
–
–
V
V
V
GS
= 0V, I
D
= 10µA
0.8
–
2.0
V
GS
= V
DS
, I
D
= 1.0mA
V
GS(th)
change with temperature
Gate body leakage current
–
–
–
–
-3.8
-5.5 mV/°C
V
GS
= V
DS
, I
D
= 1.0mA (
Note 2
)
–
–
–
100
10
nA
µA
V
GS
= ±20
V
,
V
DS
= 0V
Zero gate voltage drain current
I
DSS
V
GS
= 0V, V
DS
= Max rating
500
V
DS
= 0.8 Max Rating,
V
GS
= 0V, T
A
= 125°C (
Note 2
)
On-state drain current
I
D(ON)
1.5
–
–
–
–
A
V
GS
= 10
V
,
V
DS
= 10V
V
GS
= 5.0
V
,
I
D
= 0.3A
V
GS
= 10
V
, I
D
= 1.0A
Static drain-to-source on-state
resistance
R
DS(ON)
–
–
5.0
3.0
Ω
AC Parameters
(
Note 2
)
Forward transconductance
Input capacitance
G
FS
C
ISS
170
–
–
–
–
–
–
–
mmho V
DS
= 25
V
,
I
D
= 0.5A
–
–
–
–
–
50
40
10
10
10
pF
V
GS
= 0V,
V
DS
= 24
V
,
f = 1.0MHz
Common source output capacitance
Reverse transfer capacitance
Turn-on time
C
OSS
C
RSS
t
(ON)
ns
V
DD
= 25
V
, I
D
= 1.0A,
R
GEN
= 25
ꢀ
Turn-off time
t
(OFF)
Diode Parameters
Diode forward voltage drop
Reverse recovery time
V
SD
t
rr
–
–
1.2
–
–
V
V
GS
= 0V, I
SD
= 1.0A (
Note 1
)
V
GS
= 0V, I
SD
= 1.0A (
Note 2
)
350
ns
Note 1:
All DC parameters are 100% tested at 25°C unless otherwise stated. Pulse test: 300 µs pulse, 2% duty cycle.
2:
Specification is obtained by characterization and is not 100% tested.
TEMPERATURE SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max Units
Conditions
Temperature Ranges
Operating and Storage
T
e
mperature
T
A
-55
–
150
°C
DS20005509A-page 2
2016 Microchip Technology Inc.
2N6660
THERMAL CHARACTERISTICS
I
D
(
1
)
continuous
(mA)
I
D
pulsed
(A)
Power
Dissipation
@T
A
= 25°C (W)
I
DR
(
1
)
(mA)
I
DRM
(A)
Package
TO-39
410
3.0
6.25
410
3.0
Note 1:
I
D
(continuous) is limited by max rated T
J
.
Product Summary
BV
DSX
/BV
DGS
(V)
R
DS(ON)
(max) (
ꢀ
)
I
DSS
(min) (A)
60
3.0
1.5
2.0
PIN DESCRIPTION
The locations of the pins are listed in
Package Types
and
Packaging Information
.
TABLE 2-1:
PIN DESCRIPTION
Pin # TO-39
Function
1
2
3
SOURCE
GATE
DRAIN
2016 Microchip Technology Inc.
DS20005509A-page 3
2N6660
3.0
FUNCTIONAL DESCRIPTION
Figure 3-1
shows the switching waveform and test cir-
cuit for 2N6660.
10V
VDD
90%
INPUT
Pulse
R
L
10%
Generator
0V
OUTPUT
t
(ON)
t
d(ON)
t
(OFF)
t
d(OFF)
R
GEN
t
f
t
r
VDD
OUTPUT
0V
INPUT
D.U.
T
.
10%
10%
90%
90%
FIGURE 3-1:
Switching Waveforms and
T
e
st Circuit
DS20005509A-page 4
2016 Microchip Technology Inc.
2N6660
4.0
4.1
PACKAGING INFORMATION
Package Marking Information
3-Lead TO-39
Example
XX
XXXXXXXXXX
YYWW
2N6660
1605
e4
e4
NNN
343
Legend:
XX…X Product
Code or Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC
®
designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
e
3
*
)
3
e
Note
: In
the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
2016 Microchip Technology Inc.
DS20005509A-page 5
2N6660
DS20005509A-page 6
2016 Microchip Technology Inc.
2N6660
APPENDIX A:
REVISION HISTORY
Revision A (March 2016)
• Converted
Supertex Doc #DSFP-2N6660 to
Microchip DS20005509A.
• Minor
text changes throughout.
• Update
to
Features
.
2016 Microchip Technology Inc.
DS20005509A-page 7
2N6660
PRODUCT IDENTIFICATION SYSTEM
To
o
rder or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office
.
–
–
PART NO.
Device
XX
X
X
Examples:
a)
2N6660
TO-39 package,
500/bag
Package Environmental
Media
Options Type
Device:
2N6660 = N-Channel,
Enhancement-Mode,
Vertical DMOS FET
Package:
(blank) =
TO-39, 3-lead
Environmental
Media Type:
(blank)
= Lead
(Pb)-free/ROHS-compliant package
(blank) =
500/Bag for TO-39 packages
DS20005509A-page 8
2016 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALIT
Y
,
P
ERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE
.
Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOS
T
,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTAR
T
,
P
IC32 logo,
Right
T
o
uch, SpyNIC, SS
T
,
S
ST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip
T
e
chnology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, m
T
o
uch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip
T
e
chnology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKI
T
,
c
hipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICS
P
,
I
nter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MP
F
,
M
PLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, Right
T
o
uch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II,
T
o
tal
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip
T
e
chnology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip
T
e
chnology Incorporated
in the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
®
MCUs and dsPIC
®
DSCs, K
EE
L
OQ
®
code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Silicon Storage
T
e
chnology is a registered trademark of
Microchip
T
e
chnology Inc. in other countries.
GestIC is a registered trademarks of Microchip
T
e
chnology
Germany II GmbH & Co. K
G
, a
s
ubsidiary of Microchip
T
e
chnology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITY
ꢀ
MANAGEMENT
ꢀꢀ
SYSTEM
ꢀ
CERTIFIED
ꢀ
BY
ꢀ
DNV
ꢀ
© 2016, Microchip
T
e
chnology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0433-0
==
ISO/TS
ꢀ
16949
ꢀ
==
ꢀ
2016 Microchip Technology Inc.
DS20005509A-page 9
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e
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e
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e
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DS20005509A-page 10
2016 Microchip Technology Inc.
