Microchip-Tech-APT56F60B2
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APT56F60B2
APT56F60L
600
V
,
6
0A, 0.11
Ω
Max, t
≤
290ns
rr
N-Channel FREDFET
Power MOS 8
™
is a high speed, high voltage N-channel switch-mode power MOSFE
T
.
T
–
Max
®
TO-264
This ‘FREDFET’ version has a drain-source (body) diode that has been optimized for
high reliability in ZVS phase shifted bridge and other circuits through reduced t
, soft
rr
recover
y
,
a
nd high recovery dv/dt capabilit
y
.
L
ow gate charge, high gain, and a greatly
reduced ratio of C
/C result
in excellent noise immunity and low switching loss.
The
rss iss
APT56F60B2
APT56F60L
intrinsic gate resistance and capacitance of the poly-silicon gate structure help control
di/dt during switching, resulting in low EMI and reliable paralleling, even when switching
at very high frequenc
y
.
Single die FREDFET
FEATURES
TYPICAL APPLICATIONS
• ZVS
phase shifted and other full bridge
• Fast
switching with low EMI
• Half
bridge
• Low
t for
high reliability
rr
• PFC
and other boost converter
• Buck
converter
• Ultra
low C
for improved noise immunity
rss
• Low
gate charge
• Single
and two switch forward
• Flyback
• Avalanche
energy rated
• RoHS
compliant
Absolute Maximum Ratings
Symbol Parameter
Unit
Ratings
60
Continuous Drain Current @ T
C
= 25°C
I
D
Continuous Drain Current @ T
C
= 100°C
38
A
Pulsed Drain Current
1
I
DM
V
GS
E
AS
I
AR
210
30
V
mJ
A
Gate-Source Voltage
Single Pulse Avalanche Energy
2
Avalanche Current, Repetitive or Non-Repetitive
1580
28
Thermal and Mechanical Characteristics
Symbol Characteristic
Min
Typ
Max
1040
0.12
Unit
P
D
T
o
tal Power Dissipation @ T
C
= 25°C
W
R
θ
JC
Junction to Case Thermal Resistance
°C/W
°C
R
θ
CS
0.11
Case to Sink Thermal Resistance, Flat, Greased Surface
T
J
,T
STG
-55
150
300
Operating and Storage Junction
T
e
mperature Range
T
L
Soldering
T
e
mperature for 10 Seconds (1.6mm from case)
oz
g
0.22
6.2
W
T
Package Weight
in·lbf
N·m
10
T
o
rque
Mounting
T
o
rque ( TO-264 Package), 4-40 or M3 screw
1.1
Static Characteristics
T =
25°C unless otherwise specified
J
APT56F60B2_L
Parameter
Test Conditions
Min
Typ
Max
Unit
V
Symbol
V
BR(DSS)
V
= 0V
,
I =
250µA
Drain-Source Breakdown Voltage
Breakdown Voltage
T
e
mperature Coefficient
Drain-Source On Resistance
3
Gate-Source Threshold Voltage
Threshold Voltage
T
e
mperature Coefficient
600
GS
D
Δ
V
BR(DSS)
/
Δ
T
J
Reference to 25°C, I
= 250µA
D
V/°C
Ω
V
0.57
0.09
4
V
= 10V
,
I =
28A
D
R
DS(on)
V
GS(th)
0.11
5
GS
2.5
V
= V
DS
,
I =
2.5mA
D
GS
Δ
V
GS(th)
/
Δ
T
J
mV/°C
-10
V
= 600V
= 0V
T =
25°C
J
250
1000
100
DS
I
DSS
I
GSS
Zero Gate Voltage Drain Current
Gate-Source Leakage Current
µA
nA
V
T =
125°C
J
GS
V
=
30V
GS
Dynamic Characteristics
T =
25°C unless otherwise specified
J
Symbol
Parameter
Test Conditions
Min
Typ
55
Max
Unit
g
fs
V
= 50V
,
I =
28A
S
Forward
T
r
ansconductance
Input Capacitance
DS
D
C
iss
C
rss
C
oss
11300
115
V
= 0V
,
V =
25V
DS
GS
Reverse
T
r
ansfer Capacitance
Output Capacitance
f = 1MHz
1040
pF
4
C
o(cr)
Effective Output Capacitance, Charge Related
Effective Output Capacitance, Energy Related
550
285
V
= 0V
,
V =
0V to 400V
DS
GS
5
C
o(er)
Q
g
Q
gs
Q
gd
t
d(on)
T
o
tal Gate Charge
Gate-Source Charge
Gate-Drain Charge
T
u
rn-On Delay Time
Current Rise Time
T
u
rn-Off Delay Time
Current Fall Time
280
60
V
= 0 to 10V
,
I =
28A,
GS
D
nC
ns
V
= 300V
DS
120
65
Resistive Switching
V =
400V
,
I =
28A
DD
t
r
t
d(off)
t
f
75
D
R
= 2.2
Ω
6
,
V
= 15V
GG
190
60
G
Source-Drain Diode Characteristics
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Continuous Source Current
(Body Diode)
MOSFET symbol
showing the
integral reverse p-n
junction diode
(body diode)
I
S
60
A
Pulsed Source Current
(Body Diode)
1
I
SM
V
SD
t
rr
210
I
= 28A
,
T =
25°C, V
= 0V
Diode Forward Voltage
1.
2
290
540
V
SD
J
GS
T =
25°C
J
255
450
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Peak Recovery dv/dt
ns
T =
125°C
J
3
I
= 28A
T =
25°C
J
1.41
3.66
10.7
15.8
SD
Q
rr
µC
A
di
SD
/
dt = 100A/µs
= 100V
T =
125°C
J
V
T =
25°C
J
DD
I
rrm
T =
125°C
J
I
≤
28A, di/dt
≤
1000A/µs, V
= 400
V
,
SD
DD
dv/dt
V/ns
20
T =
125°C
J
1
2
3
Repetitive Rating: Pulse width and case temperature limited by maximum junction temperature.
Starting at T
J
= 25°C, L = 4.03mH, R
G
= 25
Ω
, I
AS
= 28A.
Pulse test: Pulse Width < 380µs, duty cycle
< 2%.
4
5
C
o(cr)
is defined as a fixed capacitance with the same stored charge as C
OSS
with V
DS
= 67% of V
(BR)DSS
.
C
o(er)
is defined as a fixed capacitance with the same stored energy as C
OSS
with V
DS
= 67% of V
(BR)DSS
.
T
o
c
alculate C
o(er)
for any value of
V
DS
less than V
(BR)DSS,
use this equation:
C
o(er)
= -1.10E-7/V
DS
^2 + 4.60E-8/V
DS
+ 1.72E-10.
6
R
G
is external gate resistance, not including internal gate resistance or gate driver impedance.
(MIC4452)
Microsemi reserves the right to change, without notice, the specifications and information contained herein.
APT56F60B2_L
90
80
70
60
50
40
30
20
250
200
150
100
V
= 10V
T
= 125°C
GS
J
V
GS
= 7&8V
T
J
= -55°C
6V
T
J
= 25°C
5.5V
50
0
T
J
= 150°C
5V
4.5V
10
0
T
J
= 125°C
15
0
5
10
20
25
30
0
0
0
5
10
15
20
25
30
V
, DRAIN-TO-SOURCE VO
L
TAGE (V)
V
, DRAIN-TO-SOURCE VO
L
TAGE (V)
DS(ON)
DS
Figure 1,
Output Characteristics
Figure 2,
Output Characteristics
3.0
2.5
2.0
1.5
1.0
200
180
160
140
120
100
80
NORMALIZED TO
= 10V
28A
V
DS
> I
D(ON)
x R
DS(ON)
MAX.
250µSEC. PULSE TEST
@ <0.5 % DUTY CYCLE
V
@
GS
T
J
= -55°C
T
J
= 25°C
T
J
= 125°C
60
40
0.5
0
20
0
-55 -25
0
25 50 75
100 125 150
1
2
3
4
5
6
7
8
T , JUNCTION
TEMPER
A
T
URE (°C)
V
, G
A
T
E-TO-SOURCE VO
L
TAGE (V)
J
GS
Figure 3,
R
vs Junction Temperature
Figure 4, Transfer Characteristics
DS(ON)
20,000
10,000
100
80
60
40
20
0
C
iss
T
J
= -55°C
T
J
= 25°C
T
J
= 125°C
1000
C
oss
100
10
C
rss
0
10
20
30
40
50
60
70
100
, DRAIN-TO-SOURCE VO
L
TAGE (V)
DS
200
300
400
500
600
I ,
DRAIN CURRENT (A)
V
D
Figure 5,
Gain vs Drain Current
Figure 6, Capacitance vs Drain-to-Source Voltage
16
14
12
10
8
200
I
= 28A
D
180
160
140
120
100
80
V
DS
=
120V
V
DS
=
300V
T
J
= 25°C
6
T
J
= 150°C
V
DS
=
480V
60
4
40
2
20
0
0
0
50 100
150 200 250 300 350
400
0
0.2 0.4
V ,
SOURCE-TO-DRAIN VO
L
TAGE (V)
SD
0.6 0.8
1.0 1.2 1.4
Q ,
TOTAL GATE CHARGE (nC)
g
Figure 7, Gate Charge vs Gate-to-Source Voltage
Figure 8, Reverse Drain Current vs Source-to-Drain Voltage
APT56F60B2_L
250
100
250
100
I
I
DM
DM
13µs
100µs
1ms
10ms
100ms
DC line
13µs
100µs
1ms
10
1
10
R
ds(on)
10ms
R
ds(on)
T
T
J
=
150°C
C
=
25°C
100ms
DC line
1
Scaling for Different Case & Junction
T
e
mperatures:
T
T
J
=
125°C
C
=
75°C
I
D
=
I
D(T =
25
°
C)
*(
T
–
T
C
)/125
J
C
0.1
0.1
1
10
100
800
1
10
, DRAIN-TO-SOURCE VO
L
TAGE (V)
DS
100
800
V
, DRAIN-TO-SOURCE VO
L
TAGE (V)
V
DS
Figure 9, Forward Safe Operating Area
Figure 10, Maximum Forward Safe Operating Area
0.14
0.12
0.10
0.08
0.06
0.04
D = 0.9
0.7
Note:
0.5
t
1
t
0.3
2
t
= Pulse Duration
t
1
1
t
/
2
SINGLE PULSE
Duty Factor D =
0.02
0
0.1
Peak T
= P
x Z
+ T
θ
JC C
J
DM
0.05
10
-5
10
-4
10
-3
10
-2
10
-1
1.0
REC
T
A
NGULAR PULSE DUR
A
T
ION (seconds)
Figure 11. Maximum Effective Transient Thermal Impedance Junction-to-Case vs Pulse Duration
®
TO-264 (L) Package Outline
T
–
MAX (B2)
Package Outline
e3 100% Sn Plated
4.69 (.185)
4.60 (.181)
5.21 (.205)
5.31 (.209)
15.49 (.610)
16.26 (.640)
19.51 (.768)
20.50 (.807)
1.49 (.059)
2.49 (.098)
1.80 (.071)
2.01 (.079)
3.10 (.122)
3.48 (.137)
5.38 (.212)
6.20 (.244)
5.79 (.228)
6.20 (.244)
20.80 (.819)
21.46 (.845)
25.48 (1.003)
26.49 (1.043)
2.87 (.113)
3.12 (.123)
4.50 (.177) Max.
2.29 (.090)
2.69 (.106)
2.29 (.090)
2.69 (.106)
1.65 (.065)
2.13 (.084)
0.40 (.016)
0.79 (.031)
19.81 (.780)
20.32 (.800)
19.81 (.780)
21.39 (.842)
Gate
Drain
Source
Gate
Drain
Source
1.01 (.040)
1.40 (.055)
0.48 (.019)
0.84 (.033)
2.59 (.102)
3.00 (.118)
0.76 (.030)
1.30 (.051)
2.21 (.087)
2.59 (.102)
2.79 (.110)
5.45 (.215) BSC
2-Plcs.
3.18 (.125)
5.45 (.215) BSC
2-Plcs.
Dimensions in Millimeters and (Inches)
These dimensions are equal to the TO-247 without the mounting hole.
Dimensions in Millimeters and (Inches)
Microsemi’s products are covered by one or more of U.S.patents 4,895,810
5,045,903 5,089,434 5,182,234 5,019,522
5,262,336 6,503,786
5,256,583 4,748,103 5,283,202 5,231,474 5,434,095 5,528,058
and foreign patents.
US and Foreign patents pending.
All Rights Reserved.
