Microchip-Tech-ATA8202C-PXQW-1

Part #	Microchip-Tech-ATA8202C-PXQW-1
Download	Microchip-Tech-ATA8202C-PXQW-1

ATA8201/ATA8202

UHF ASK/FSK Receiver

DATASHEET

Features

●

Transparent RF receiver ICs for 315MHz (Atmel

ATA8201) and 433.92MHz

(Atmel ATA8202) with high receiving sensitivity

●

Fully integrated PLL with low phase noise VCO, PLL, and loop filter

●

High FSK/ASK sensitivity:

●

–105dBm (Atmel ATA8201, FSK, 9.6Kbits/s, Manchester, BER 10

-3

●

–114dBm (Atmel ATA8201, ASK, 2.4Kbits/s, Manchester, BER 10

-3

)

●

–104dBm (Atmel ATA8202, FSK, 9.6Kbits/s, Manchester, BER 10

-3

)

●

–113dBm (Atmel ATA8202, ASK, 2.4Kbits/s, Manchester, BER 10

-3

)

●

Supply current: 6.5mA in Active Mode (3

, 25°C, ASK Mode)

●

Data rate: 1Kbit/s to 10Kbits/s Manchester ASK, 1Kbit/s to 20Kbits/s Manchester

FSK with four programmable bit rate ranges

●

Switching between modulation types ASK/FSK and different data rates possible in

≤

1ms typically, without hardware modification on board to allow different

modulation schemes

●

Low standby current: 50µA at 3V, 25°C

●

ASK/FSK receiver uses a low-IF architecture with high selectivity, blocking, and low

intermodulation (typical 3-dB blocking 68.0dBC at ±3MHz/74.0dBC at ±20.0MHz,

system I1dBCP = –31dBm/system IIP3 = –24dBm)

●

legram pause up to 52ms supported in ASK Mode

●

Wide bandwidth AGC to handle large out-of-band blockers above the system

I1dBCP

●

440-kHz IF frequency with 30-dB image rejection and 420-kHz IF bandwidth to

support PLL transmitters with standard crystals or SAW-based transmitters

●

RSSI (received signal strength indicator) with output signal dynamic range of 65dB

●

Low in-band sensitivity change of typically ±2.0dB within ±160-kHz center

frequency change in the complete temperature and supply voltage range

●

Sophisticated threshold control and quasi-peak detector circuit in the data slicer

●

Fast and stable XTO start-up circuit (> –1.4 k

worst-case start impedance)

●

Clock generation for microcontroller

●

ESD protection at all pins (±4kV HBM, ±200V MM, ±500V FCDM)

4971G-INDCO-09/14

●

Dual supply voltage range: 2.7V to 3.3V or 4.5V to 5.5V

●

mperature range: –40°C to +85°C

●

Small 5mm

5mm QFN24 package

Applications

●

Industrial/aftermarket keyless entry and tire pressure monitoring systems

●

Alarm, telemetering and energy metering systems

●

Remote control systems for consumer and industrial markets

●

Access control systems

●

Home automation

●

Home entertainment

●

Benefits

●

Supports header and blanking periods of protocols common in RKE and TPM systems (up to 52ms in ASK Mode)

●

All RF relevant functions are integrated. The single-ended RF input is suited for easy adaptation to

/ 4 or printed-loop

antennas

●

Allows a low-cost application with only 8 passive components

●

Optimal bandwidth maximizes sensitivity while maintaining SAW transmitter compatibility

●

Clock output provides an external microcontroller crystal-precision time reference

●

Well suited for use with Atmel

PLL transmitter ATA8401/ATA8402/ATA8403/ATA8404/ATA8405

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

General Description

The Atmel

ATA8201/ATA8202 is a UHF ASK/FSK transparent receiver IC with low power consumption supplied in a small

QFN24 package (body 5mm

5mm, pitch 0.65mm). Atmel ATA8202 is used in the 433MHz to 435MHz band of operation,

and Atmel ATA8201 in 313MHz to 317MHz.

For improved image rejection and selectivity, the IF frequency is fixed to 440kHz. The IF block uses an 8th-order band pass

yielding a receive bandwidth of 420kHz. This enables the use of the receiver in both SAW- and PLL-based transmitter

systems utilizing various types of data-bit encoding such as pulse width modulation, Manchester modulation, variable pulse

modulation, pulse position modulation, and NRZ. Prevailing encryption protocols such as Keeloq

are easily supported due

to the receiver’s ability to hold the current data slicer threshold for up to 52ms when incoming RF telegrams contain a

blanking interval. This feature eliminates erroneous noise from appearing on the demodulated data output pin, and simplifies

software decoding algorithms. The decoding of the data stream must be carried out by a connected microcontroller device.

Because of the highly integrated design, the only required RF components are for the purpose of receiver antenna matching.

Atmel ATA8201 and Atmel ATA8202 support Manchester bit rates of 1Kbit/s to 10Kbits/s in ASK and 1Kbit/s to 20Kbits/s in

FSK mode. The four discrete bit rate passbands are selectable and cover 1.0Kbit/s to 2.5Kbits/s, 2.0Kbits/s to 5.0Kbits/s,

4.0Kbits/s to 10.0Kbits/s, and 8.0Kbits/s to 10.0Kbits/s or 20.0Kbits/s (for ASK or FSK, respectively). The receiver contains

an RSSI output to provide an indication of received signal strength and a SENSE input to allow the customer to select a

threshold below which the DATA signal is gated off. ASK/FSK and bit rate ranges are selected by the connected

microcontroller device via pins ASK_NFSK, BR0, and BR1.

Figure 1-1.

System Block Diagram

ATA8201/ATA8202

Digital Control

Logic

Power

Supply

Antenna

RF Receiver

Microcontroller

4 … 8

(LNA, Mixer,

VCO, PLL,

IF Filter,

Microcontroller

Interface

RSSI Amp.,

Demodulator)

XTO

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

Figure 1-2.

Pinning QFN24

24 23 22 21 20 19

TEST2

TEST1

CLK_OUT

TEST3

RSSI

SENSE_CTRL

SENSE

LNA_IN

CLK_OUT_CTRL1

CLK_OUT_CTRL0

ENABLE

LNA_GND

9 10

11 12

Table 1-1.

Pin Description

Symbol

Function

TEST2

TEST1

st pin, during operation at GND

Output to clock a connected microcontroller

Input to control CLK_OUT (MSB)

Input to control CLK_OUT (LSB)

Input to enable the XTO

CLK_OUT

CLK_OUT_CTRL1

CLK_OUT_CTRL0

ENABLE

XTAL2

Reference crystal

XTAL1

Reference crystal

DVCC

Digital voltage supply blocking

Power supply input for voltage range 4.5V to 5.5V

Power supply input for voltage range 2.7V to 3.3V

Ground

VS5V

VS3V_AVCC

GND

LNA_GND

LNA_IN

RF ground

RF input

SENSE

Sensitivity control resistor

Sensitivity selection

Low: Normal sensitivity, High: Reduced sensitivity

SENSE_CTRL

RSSI

TEST3

Output of the RSSI amplifier

st pin, during operation at GND

Input to activate the receiver

Bit rate selection, LSB

BR0

BR1

Bit rate selection, MSB

FSK/ASK selection

Low: FSK, High: ASK

ASK_NFSK

CDEM

DATA_OUT

GND

Capacitor to adjust the lower cut-off frequency data filter

Data output

Ground/backplane (exposed die pad)

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

Figure 1-3.

Block Diagram

ASK

FSK

ASK/FSK

Demo-

dulator

VS3V_AVCC

VS5V

Power

Supply

CDEM

ASK/FSK

Control

ASK_NFSK

IF Amp

SENSE

Data

DATA_OUT

BR0

BR1

Slicer

SENSE_CTRL

IF Filter

LPF

GND

Standby

Logic Control

CLK_OUT_CTRL1

CLK_OUT_CTRL0

CLK_OUT

XTO

DVCC

Div. by 3, 6, 12

IF Amp

LPF

RSSI

PLL

XTO

ENABLE

(/24, /32)

TEST1

TEST2

TEST3

LNA_IN

LNA

VCO

LNA_GND

XTAL2

XTAL1

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

RF Receiver

As seen in

Figure 1-3 on page 5

, the RF receiver consists of a low-noise amplifier (LNA), a local oscillator, and the signal

processing part with mixer, IF filter, IF amplifier with analog RSSI, FSK/ASK demodulator, data filter, and data slicer.

In receive mode, the LNA pre-amplifies the received signal which is converted down to a 440-kHz intermediate frequency

(IF), then filtered and amplified before it is fed into an FSK/ASK demodulator, data filter, and data slicer. The received signal

strength indicator (RSSI) signal is available at the pin RSSI.

2.1

Low-IF Receiver

The receive path consists of a fully integrated low-IF receiver. It fulfills the sensitivity, blocking, selectivity, supply voltage,

and supply current specification needed to design, e.g., an industrial/ aftermarket integrated receiver for RKE and TPM

systems. A benefit of the integrated receive filter is that no external components needed.

At 315MHz, the Atmel

ATA8201 receiver (433.92MHz for the Atmel ATA8202 receiver) has a typical system noise figure of

6.0dB (7.0dB), a system I1dBCP of –31dBm (–30dBm), and a system IIP3 of –24dBm (–23dBm). The signal path is linear for

out-of-band disturbers up to the I1dBCP and hence there is no AGC or switching of the LNA needed, and a better blocking

performance is achieved. This receiver uses an IF (intermediate frequency) of 440kHz, the typical image rejection is 30dB

and the typical 3-dB IF filter bandwidth is 420kHz (f

= 440kHz ± 210kHz, f

lo_IF

= 230kHz and f

hi_IF

= 650kHz). The

demodulator needs a signal-to-noise ratio of 8.5dB for 10Kbits/s Manchester with ±38kHz frequency deviation in FSK mode,

thus, the resulting sensitivity at 315MHz (433.92MHz) is typically –105dBm (–104dBm).

Due to the low phase noise and spurs of the synthesizer together with the 8th-order integrated IF filter, the receiver has a

better selectivity and blocking performance than more complex double superhet receivers, without using external

components and without numerous spurious receiving frequencies.

A low-IF architecture is also less sensitive to second-order intermodulation (IIP2) than direct conversion receivers where

every pulse or amplitude modulated signal (especially the signals from TDMA systems like GSM) demodulates to the

receiving signal band at second-order non-linearities.

2.2

Input Matching at LNA_IN

The measured input impedances as well as the values of a parallel equivalent circuit of these impedances can be seen in

ble 2-1

. The highest sensitivity is achieved with power matching of these impedances to the source impedance.

Table 2-1.

Measured Input Impedances of the LNA_IN Pin

[MHz]

315

(RF_IN) [

]

(72.4 – j298)

(55 – j216)

In_p

//C

In_p

[pF]

1300

//1.60

900

//1.60

433.92

The matching of the LNA input to 50

is done using the circuit shown in

Figure 2-1

and the values of the matching elements

given in

ble 2-2

. The reflection coefficients were always

≤

–10dB. Note that value changes of C1 and L1 may be

necessary to compensate individual board layout parasitics. The measured typical FSK and ASK Manchester-code

sensitivities with a bit error rate (BER) of 10

–3

are shown in

ble 2-3

and

ble 2-4 on page 7

. These measurements were

done with wire-wound inductors having quality factors reported in

ble 2-2

, resulting in estimated matching losses of 0.8dB

at 315MHz and 433.92MHz. These losses can be estimated when calculating the parallel equivalent resistance of the

inductor with R

loss

= 2

× π ×

and the matching loss with 10 log(1+R

In_p

/ R

loss

Figure 2-1.

Input Matching to 50

ATA8201/ATA8202

LNA_IN

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

Table 2-2.

Input Matching to 50

[MHz]

315

[pF]

2.2

[nH]

433.92

2.2

Table 2-3.

Measured Typical Sensitivity FSK,

38 kHz, Manchester, BER = 10

–3

BR_Range_0

1.0Kbit/s

BR_Range_0

2.5Kbits/s

BR_Range_1

5Kbits/s

BR_Range_2

10Kbits/s

BR_Range_3

10Kbits/s

BR_Range_3

RF Frequency

315MHz

20Kbits/s

–104dBm

–103dBm

–108dBm

–107dBm

–108dBm

–107dBm

–106dBm

–105dBm

–104dBm

–103dBm

433.92MHz

Table 2-4.

Measured Typical Sensitivity 100% ASK, Manchester, BER = 10

–3

BR_Range_0

1.0Kbit/s

BR_Range_0

2.5Kbits/s

BR_Range_1

5Kbits/s

BR_Range_2

10Kbits/s

BR_Range_3

10Kbits/s

RF Frequency

315MHz

–114dBm

–113dBm

–114dBm

–113dBm

–112dBm

–111dBm

–110dBm

–109dBm

–108dBm

433.92MHz

Conditions for the sensitivity measurement:

The given sensitivity values are valid for Manchester-modulated signals. For the sensitivity measurement the distance from

edge to edge must be evaluated. As can be seen in

Figure 6-1 on page 21

, in a Manchester-modulated data stream, the time

segments T

and 2

occur.

To reach the specified sensitivity for the evaluation of T

and 2

in the data stream, the following limits should be used

min, T

max, 2

min, 2

max).

Table 2-5.

Limits for Sensitivity Measurements

Bit Rate

1.0Kbit/s

2.4Kbits/s

5.0Kbits/s

9.6Kbits/s

Min

260µs

110µs

55µs

Typ

500µs

208µs

100µs

52µs

Max

790µs

310µs

155µs

78µs

Min

800µs

Typ

1000µs

416µs

Max

1340µs

525µs

320µs

160µs

200µs

260µs

27µs

81µs

104µs

131µs

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

2.3

Sensitivity Versus Supply Voltage, Temperature and Frequency Offset

To calculate the behavior of a transmission system, it is important to know the reduction of the sensitivity due to several

influences. The most important are frequency offset due to crystal oscillator (XTO) and crystal frequency (XTAL) errors,

temperature and supply voltage dependency of the noise figure, and IF-filter bandwidth of the receiver.

Figure 2-2

and

Figure 2-3 on page 8

show the typical sensitivity at 315MHz, ASK, 2.4Kbits/s and 9.6Kbits/s, Manchester,

Figure 2-4

and

Figure 2-5 on page 9

show a typical sensitivity at 315MHz, FSK, 2.4Kbits/s and 9.6Kbits/s, ±38kHz, Manchester versus the

frequency offset between transmitter and receiver at T

amb

= +25°C and supply voltage VS = VS3V_AVCC = VS5V = 3.0V.

Figure 2-2.

Measured Sensitivity (315MHz, ASK, 2.4Kbits/s, Manchester) Versus Frequency Offset

Input Sensitivity (dBm) at BER < 1e-3, ATA8201, ASK, 2.4Kbits/s (Manchester),

BR = 0

-118

-117

-116

3.0V/25°C

-115

-114

-113

-112

-111

-110

-109

-108

-107

-106

-105

-104

-103

-300

-200

-100

100

200

300

delta RF (kHz) at 315MHz

Figure 2-3.

Measured Sensitivity (315MHz, ASK, 9.6Kbits/s, Manchester) Versus Frequency Offset

Input Sensitivity (dBm) at BER < 1e-3, ATA8201, ASK, 9.6Kbits/s (Manchester),

BR = 2

-115

-114

-113

-112

3.0V/25°C

-111

-110

-109

-108

-107

-106

-105

-104

-103

-102

-101

-100

-300

-200

-100

100

200

300

delta RF (kHz) at 315MHz

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

Figure 2-4.

Measured Sensitivity (315MHz, FSK, 2.4Kbits/s, ±38kHz, Manchester) Versus Frequency Offset

Input Sensitivity (dBm) at BER < 1e-3, ATA8201, FSK, 2.4Kbits/s (Manchester),

BR = 0

-112

-111

-110

3.0V/25°C

-109

-108

-107

-106

-105

-104

-103

-102

-101

-100

-99

-98

-300

-200

-100

100

200

300

delta RF (kHz) at 315MHz

Figure 2-5.

Measured Sensitivity (315MHz, FSK, 9.6Kbits/s, ±38kHz, Manchester) Versus Frequency Offset

Input Sensitivity (dBm) at BER < 1e-3, ATA8201, FSK, 9.64Kbits/s (Manchester),

BR = 2

-110

-109

-108

-107

-106

3.0V/25°C

-105

-104

-103

-102

-101

-100

-99

-98

-97

-96

-95

-300

-200

-100

100

200

300

delta RF (kHz) at 315MHz

As can be seen in

Figure 2-5 on page 9

, the supply voltage has almost no influence. The temperature has an influence of

about ±1.0dB, and a frequency offset of ±160kHz also influences by about ±1dB. All these influences, combined with the

sensitivity of a typical IC (–105dB), are then within a range of –103.0dBm and –107.0dBm over temperature, supply voltage,

and frequency offset. The integrated IF filter has an additional production tolerance of ±10kHz, hence, a frequency offset

between the receiver and the transmitter of ±160kHz can be accepted for XTAL and XTO tolerances.

Note:

For the demodulator used in the Atmel

ATA8201/ATA8202, the tolerable frequency offset does not change

with the data frequency. Hence, the value of ±160kHz is valid for 1Kbit/s to 10Kbits/s.

This small sensitivity change over supply voltage, frequency offset, and temperature is very unusual in such a receiver. It is

achieved by an internal, very fast, and automatic frequency correction in the FSK demodulator after the IF filter, which leads

to a higher system margin. This frequency correction tracks the input frequency very quickly. If, however, the input frequency

makes a larger step (for example, if the system changes between different communication partners), the receiver has to be

restarted. This can be done by switching back to Standby mode and then again to Active mode (pin RX 1

→

1) or by

generating a positive pulse on pin ASK_NFSK (0

→

0).

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

2.4

RX Supply Current Versus Temperature and Supply Voltage

ble 2-7

shows the typical supply current of the receiver in Active mode versus supply voltage and temperature with

VS = VS3V_AVCC = VS5V.

Table 2-6.

Measured Current in Active Mode ASK

VS = VS3V_AVCC = VS5V

3.0V

amb

25°C

6.5mA

Table 2-7.

Measured Current in Active Mode FSK

VS = VS3V_AVCC = VS5V

3.0V

amb

25°C

6.7mA

2.5

Blocking, Selectivity

As can be seen in

Figure 2-6 on page 10

, and

Figure 2-7

and

Figure 2-8 on page 11

, the receiver can receive signals 3dB

higher than the sensitivity level in the presence of large blockers of –34.5dBm or –28dBm with small frequency offsets of

±3MHz or ±20MHz.

Figure 2-6

, and

Figure 2-7 on page 11

show the narrow-band blocking, and

Figure 2-8 on page 11

shows the wide-band

blocking characteristic. The measurements were done with a useful signal of 315MHz, FSK, 10Kbits/s, ±38kHz, Manchester,

BR_Range2 with a level of –105dBm + 3dB = –102dBm, which is 3dB above the sensitivity level. The figures show how

much larger than –102dBm a continuous wave signal can be, until the BER is higher than 10

–3

. The measurements were

done at the 50

input shown in

Figure 2-1 on page 6

. At 3 MHz, for example, the blocker can be 67.5dBC higher than –

102dBm, or

–102dBm + 67.5dBC = –34.5dBm.

Figure 2-6.

Close-in 3-dB Blocking Characteristic and Image Response at 315MHz

-10

-2

-1.5

-1

-0.5

0.5

1.5

Distance from Interfering to Receiving Signal (MHz)

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

Figure 2-7.

Narrow-band 3-dB Blocking Characteristic at 315MHz

-10

-5

-4

-3

-2

-1

Distance from Interfering to Receiving Signal (MHz)

Figure 2-8.

Wide-band 3-dB Blocking Characteristic at 315MHz

-10

-50

-40

-30

-20

-10

Distance from Interfering to Receiving Signal (MHz)

ble 2-8

shows the blocking performance measured relative to –102dBm for some frequencies. Note that sometimes the

blocking is measured relative to the sensitivity level 104dBm (denoted dBS), instead of the carrier –102dBm (denoted dBC).

Table 2-8.

Blocking 3dB Above Sensitivity Level With BER < 10

–3

Frequency Offset

+1.5MHz

–1.5MHz

+2MHz

Blocking Level

–44.5dBm

–39.0dBm

–36.0dBm

–34.5dBm

–28.0dBm

Blocking

57.5dBC, 60.5dBS

63dBC, 66dBS

–2MHz

66dBC, 69dBS

+3MHz

67.5dBC, 70.5dBS

74dBC, 77dBS

–3MHz

+20MHz

–20MHz

74dBC, 77dBS

The Atmel

ATA8201/ATA8202 can also receive FSK and ASK modulated signals if they are much higher than the I1dBCP.

It can typically receive useful signals at –10dBm. This is often referred to as the nonlinear dynamic range (that is, the

maximum to minimum receiving signal), and is 95dB for 10Kbits/s Manchester (FSK). This value is useful if the transmitter

and receiver are very close to each other.

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

2.6

In-band Disturbers, Data Filter, Quasi-peak Detector, Data Slicer

If a disturbing signal falls into the received band, or if a blocker is not a continuous wave, the performance of a receiver

strongly depends on the circuits after the IF filter. Hence, the demodulator, data filter, and data slicer are important.

The data filter of the Atmel

ATA8201/ATA8202 functions also as a quasi-peak detector. This results in a good suppression

of above mentioned disturbers and exhibits a good carrier-to-noise performance. The required useful-signal-to-disturbing-

signal ratio, at a BER of 10

–3,

is less than 14dB in ASK mode and less than 3dB (BR_Range_0 to BR_Range_2) and 6dB

(BR_Range_3) in FSK mode. Due to the many different possible waveforms, these numbers are measured for the signal, as

well as for disturbers, with peak amplitude values. Note that these values are worst-case values and are valid for any type of

modulation and modulating frequency of the disturbing signal, as well as for the receiving signal. For many combinations,

lower carrier-to-disturbing-signal ratios are needed.

2.7

RSSI Output

The output voltage of the pin RSSI is an analog voltage, proportional to the input power level. Using the RSSI output signal,

the signal strength of different transmitters can be distinguished. The usable dynamic range of the RSSI amplifier is 65dB,

the input power range P(RF

) is

–110dBm to –45dBm, and the gain is 15mV/dB.

Figure 2-9

shows the RSSI characteristic of a typical device at 315MHz with

VS3V_AVCC = VS5V = 3V and T

amb

= 25°C with a matched input as shown in

ble 2-2

and

Figure 2-1 on page 6

. At

433.92MHz, 1 dB more signal level is needed for the same RSSI results.

Figure 2-9.

Typical RSSI Characteristic at 315MHz Versus Temperature and Supply Voltage

1.7

1.6

3V, 25°C

1.5

1.4

1.3

1.2

max: +9dBm

1.1

1.0

0.9

0.8

0.7

0.6

min: -9dBm

0.5

0.4

-130 -120 -110 -100

-90 -80 -70 -60 -50 -40 -30 -20 -10

Pin (dBm)

As can be seen in

Figure 2-9 on page 12

, for single devices there is a variance over temperature and supply voltage range

of ±3dB. The total variance over production, temperature, and supply voltage range is ±9dB.

2.8

Frequency Synthesizer

The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal oscillator) generates the

reference frequency f

XTO

. The VCO (voltage-controlled oscillator) generates the drive voltage frequency f

for the mixer. f

is divided by the factor 24 (Atmel ATA8201) or 32 (Atmel ATA8202). The divided frequency is compared to f

XTO

by the phase

frequency detector. The current output of the phase frequency detector is connected to the fully integrated loop filter, and

thereby generates the control voltage for the VCO. By means of that configuration, the VCO is controlled in a way, such that

_{LO
/ 24 (f
LO
/ 32) is equal to f
XTO
. If f
LO
is determined, f
XTO
can be calculated using the following formula: f
XTO
= f
LO
/ 24}

XTO

= f

/ 32). The synthesizer has a phase noise of –130dBC/Hz at 3MHz and spurs of –75dBC.

Care must be taken with the harmonics of the CLK output signal, as well as with the harmonics produced by a

microprocessor clocked using the signal, as these harmonics can disturb the reception of signals.

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

XTO

The XTO is an amplitude-regulated Pierce oscillator type with external load capacitances (2

16pF). Due to additional

internal and board parasitics (C

) of approximately 2pF on each side, the load capacitance amounts to 2

18pF (9pF total).

The XTO oscillation frequency f

XTO

is the reference frequency for the integer-N synthesizer. When designing the system in

terms of receiving and transmitting frequency offset, the accuracy of the crystal and XTO have to be considered.

The XTO’s additional pulling (including the R

tolerance) is only ±5ppm. The XTAL versus temperature, aging, and

tolerances is then the main source of frequency error in the local oscillator.

The XTO frequency depends on XTAL properties and the load capacitances C

L1,2

at pin XTAL1 and XTAL2. The pulling (p)

of f

XTO

from the nominal f

XTAL

is calculated using the following formula:

——- ————————————————————

10 ppm

_{LN
– C
L}

-6

p =

(

+ C

) × (

+ C

)

, the crystal’s motional capacitance; C

, the shunt capacitance; and C

, the nominal load capacitance of the XTAL, are

found in the datasheet. C

is the total actual load capacitance of the crystal in the circuit, and consists of C

and C

connected in series.

Figure 3-1.

Crystal Equivalent Circuit

XTAL

= C

x C

/ (C

+ C

)

With C

≤

10fF, C

≥

1.0pF, C

= 9pF and C

L1,2

= 16pF ±1%, the pulling amounts to P

≤

±1ppm.

The C

of the XTAL has to be lower than C

Lmin

/ 2 = 7.9pF for a Pierce oscillator type in order to not enter the steep region of

pulling versus load capacitance where there is risk of an unstable oscillation.

To ensure proper start-up behavior, the small signal gain and the negative resistance provided by this XTO at start is very

large. For example, oscillation starts up even in the worst case with a crystal series resistance of 1.5k

at C

≤

2.2pF with

this XTO. The negative resistance is approximately given by

Z +

⎧

⎨

⎩

⎫

⎬

⎭

———————————————————————————-

{

Zxtocore

}

= Re

+ Z

with Z

and Z

as complex impedances at pins XTAL1 and XTAL2, hence

= –j / (2

XTO

) + 5

and Z

= –j / (2

XTO

) + 5

consists of crystal C

in parallel with an internal 110-k

resistor, hence

= –j / (2

XTO

) / 110 k

, gm is the internal transconductance between XTAL1 and XTAL2, with typically 20mS at

25°C.

With f

XTO

= 13.5MHz, gm = 20mS, C

= 9pF, and C

= 2.2pF, this results in a negative resistance of about 2k

. The worst

case for technology, supply voltage, and temperature variations is then always higher than 1.4k

for C

≤

2.2pF.

Due to the large gain at start, the XTO is able to meet a very low start-up time. The oscillation start-up time can be estimated

with the time constant

———————————————————————————————————–

× π

XTAL

× (

(

xtocor

)

+ R

)

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

After 10

to 20

τ,

an amplitude detector detects the oscillation amplitude and sets XTO_OK to High if the amplitude is large

enough; this activates the CLK_OUT output if it is enabled via the pins CLK_OUT_CTRL0 and CLK_OUT_CTRL1. Note that

the necessary conditions of the DVCC voltage also have to be fulfilled.

It is recommended to use a crystal with C

= 3.0fF to 10fF, C

= 9pF, R

< 120

and C

= 1.0pF to 2.2pF.

Lower values of C

can be used, slightly increasing the start-up time. Lower values of C

or higher values of C

(up to 15fF)

can also be used, with only little influence on pulling.

Figure 3-2.

XTO Block Diagram

XTAL1

XTAL2

CLK_OUT_CTRL0 CLK_OUT_CTRL1

CLK_OUT

FXTO

Divider

/3, /6, /12

XTO_OK

Amplitude

Detector

Divider

/16

DCLK

The relationship between f

XTO

and the f

is shown in

ble 3-1

Table 3-1.

Calculation of f

Frequency [MHz]

433.92 (Atmel ATA8202)

315.0 (Atmel ATA8201)

XTO

[MHz]

13.57375

13.1433

_{XTO
×
32 – 440kHz}

_{XTO
×
24 – 440kHz}

Attention must be paid to the harmonics of the CLK_OUT output signal f

CLK_OUT

as well as to the harmonics produced by an

microprocessor clocked with it, since these harmonics can disturb the reception of signals if they get to the RF input. If the

CLK_OUT signal is used, it must be carefully laid out on the application PCB. The supply voltage of the microcontroller must

also be carefully blocked.

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

3.1

Pin CLK_OUT

Pin CLK_OUT is an output to clock a connected microcontroller. The clock is available in Standby and Active modes. The

frequency f

CLK_OUT

can be adjusted via the pins CLK_OUT_CTRL0 and CLK_OUT_CTRL1, and is calculated as follows:

Table 3-2.

Setting of f

CLK_OUT

CLK_OUT_CTRL1

CLK_OUT_CTRL0

Function

Clock on pin CLK_OUT is switched off

(Low level on pin CLK_OUT)

CLK_OUT

= f

XTO

/ 3

CLK_OUT

= f

XTO

/ 6

CLK_OUT

= f

XTO

/ 12

The signal at CLK_OUT output has a nominal 50% duty cycle. To save current, it is recommended that CLK_OUT be

switched off during Standby mode.

3.2

Basic Clock Cycle of the Digital Circuitry

The complete timing of the digital circuitry is derived from one clock. As seen in

Figure 3-2 on page 14

, this clock cycle,

_{DCLK
, is derived from the crystal oscillator (XTO) in combination with a divider.}

XTO

———–

DCLK

controls the following application relevant parameters:

– Debouncing of the data signal stream

– Start-up time of the RX signal path

The start-up time and the debounce characteristic depend on the selected bit rate range (BR_Range) which is defined by

pins BR0 and BR1. The clock cycle T

XDCLK

is defined by the following formulas for further reference:

BR_Range

⇒

BR_Range 0: T

XDCLK

= 8

DCLK

BR_Range 1: T

XDCLK

= 4

DCLK

BR_Range 2: T

XDCLK

= 2

DCLK

BR_Range 3: T

XDCLK

= 1

DCLK

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

Sensitivity Reduction

The output voltage of the RSSI amplifier is internally compared to a threshold voltage V

Th_red

. V

Th_red

is determined by the

value of the external resistor R

Sense

. R

Sense

is connected between the pins SENSE and VS3V_AVCC (see

Figure 10-1 on

page 25

). The output of the comparator is fed into the digital control logic. By this means, it is possible to operate the receiver

at a lower sensitivity.

If the level on input pin SENSE_CTRL is low, the receiver operates at full sensitivity.

If the level on input pin SENSE_CTRL is high, the receiver operates at a lower sensitivity. The reduced sensitivity is defined

by the value of R

Sense

, the maximum sensitivity by the signal-to-noise ratio of the LNA input. The reduced sensitivity depends

on the signal strength at the output of the RSSI amplifier.

Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the

electrical characteristics refer to a specific input matching. This matching is illustrated in

Figure 2-1 on page 6

and exhibits

the best possible sensitivity.

If the sensitivity reduction feature is not used, pin SENSE can be left open, pin SENSE_CTRL must be set to GND.

To operate with reduced sensitivity, pin SENSE_CTRL must be set to high before the RX signal path will be enabled by

setting pin RX to high (see

Figure 4-1 on page 16

). As long as the RSSI level is lower than V

Th_red

(defined by the external

resistor R

Sense

) no data stream is available on pin DATA_OUT (low level on pin DATA_OUT). An internal RS flip-flop will be

set to high the first time the RSSI voltage crosses V

Th_red

, and from then on the data stream will be available on pin

DATA_OUT. From then on the receiver also works with full sensitivity. This makes sure that a telegram will not be interrupted

if the RSSI level varies during the transmission. The RS flip-flop can be set back, and thus the receiver switched back to

reduced sensitivity, by generating a positive pulse on pin ASK_NFSK (see

Figure 4-2 on page 17

). In FSK mode, operating

with reduced sensitivity follows the same way.

Figure 4-1.

Reduced Sensitivity Active

ENABLE

ASK_NFSK

SENSE_CTRL

Th_red

RSSI

Startup_PLL Startup_Sig_Proc

DATA_OUT

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

Figure 4-2.

Restart Reduced Sensitivity

ENABLE

ASK_NFSK

SENSE_CTRL

Th_red

RSSI

Startup_Sig_Proc

DATA_OUT

Power Supply

Figure 5-1.

Power Supply

VS3V_AVCC

SW_DVCC

OUT

V_REG

3.0V typ.

VS5V

DVCC

The supply voltage range of the Atmel

ATA8201/ATA8202 is 2.7V to 3.3V or 4.5V to 5.5V.

Pin VS3V_AVCC is the supply voltage input for the range 2.7V to 3.3V, and is used in battery applications using a single

lithium 3V cell. Pin VS5V is the voltage input for the range 4.5V to 5.5V (car applications) in this case the voltage regulator

V_REG regulates VS3V_AVCC to typically 3.0V. If the voltage regulator is active, a blocking capacitor of 2.2µF has to be

connected to VS3V_AVCC (see

Figure 10-1 on page 25

DVCC is the internal operating voltage of the digital control logic and is fed via the switch SW_DVCC by VS3V_AVCC.

DVCC must be blocked on pin DVCC with 68nF (see

Figure 9-1 on page 24

and

Figure 10-1 on page 25

Pin RX is the input to activate the RX signal processing and set the receiver to Active mode.

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

5.1

OFF Mode

A low level on pin RX and ENABLE will set the receiver to OFF mode (low power mode). In this mode, the crystal oscillator is

shut down and no clock is available on pin CLK_OUT. The receiver is not sensitive to a transmitter signal in this mode.

Table 5-1.

Standby Mode

ENABLE

Function

OFF mode

5.2

Standby Mode

The receiver activates the Standby mode if pin ENABLE is set to “1”.

In Standby mode, the XTO is running and the clock on pin CLK_OUT is available after the start-up time of the XTO has

elapsed (dependent on pin CLK_OUT_CTRL0 and CLK_OUT_CTRL1). During Standby mode, the receiver is not sensitive

to a transmitter signal.

In Standby mode, the RX signal path is disabled and the power consumption I

Standby

is typically 50 µA (CLK_OUT output off,

VS3V_AVCC = VS5V = 3V). The exact value of this current is strongly dependent on the application and the exact operation

mode, therefore check the section

“Electrical Characteristics: General” on page 26

for the appropriate application case.

Table 5-2.

Standby Mode

ENABLE

Function

Standby mode

Figure 5-2.

Standby Mode (CLK_OUT_CTRL0 or CLK_OUT_CTRL1 = 1)

CLK_OUT

XTO_Startup

ENABLE

Standby Mode

5.3

Active Mode

The Active mode is enabled by setting the level on pin RX to high. In Active mode, the RX signal path is enabled and if a

valid signal is present it will be transferred to the connected microcontroller.

Table 5-3.

Active Mode

ENABLE

Function

Active mode

During T

Startup_PLL

the PLL is enabled and starts up. If the PLL is locked, the signal processing circuit starts up

Startup_Sig_Proc

). After the start-up time, all circuits are in stable condition and ready to receive. The duration of the start-up

sequence depends on the selected bit rate range.

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

Figure 5-3.

Active Mode

CLK_OUT

ENABLE

DATA_OUT

DATA_OUT valid

Startup_Sig_Proc

Startup_PLL

Active

Standby

Active

Standby Mode

Startup

Active Mode

Table 5-4.

Start-up Time

Atmel ATA8202 (433.92MHz)

Startup_PLL

Startup_Sig_Proc

Atmel ATA8201 (315MHz)

BR1

BR0

Startup_PLL

Startup_Sig_Proc

1096µs

644µs

417µs

304µs

1132µs

665µs

431µs

324µs

261µs

269µs

Table 5-5.

Modulation Scheme

ASK_NFSK

at Pin LNA_IN

FSK_H

FSK_L

Level at Pin DATA_OUT

ASK

off

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

Bit Rate Ranges

Configuration of the bit rate ranges is carried out via the two pins BR0 and BR1. The microcontroller uses these two interface

lines to set the corner frequencies of the band-pass data filter. Switching the bit rate ranges while the RF front end is in

Active mode can be done on the fly and will not take longer than 100 µs if done while remaining in either ASK or FSK mode.

If the modulation scheme is changed at the same time, the switching time is (T

Startup_Sig_Proc

, see

Figure 7-1 on page 22

Each BR_Range is defined by a minimum edge-to-edge time. To maintain full sensitivity of the receiver, edge-to-edge

transition times of incoming data should not be less than the minimum for the selected BR_Range.

Table 6-1.

BR Ranges ASK

Minimum Edge-to-edge

Edge-to-edge Time Period T

Recommended Bit Rate

(Manchester)

(1)

Time Period T

of the

of the Data Signal During the

BR1 BR0

BR_Range

BR_Range0

BR_Range1

BR_Range2

BR_Range3

Data Signal

(2)

Start-up Period

(3)

1.0Kbit/s to 2.5Kbits/s

2.0Kbits/s to 5.0Kbits/s

4.0Kbits/s to 10.0Kbits/s

8.0Kbits/s to 10.0Kbits/s

200µs

100µs

50µs

200µs to 500µs

100µs to 250µs

50µs to 125µs

50µs to 62.5µs

50µs

Table 6-2.

BR Ranges FSK

Minimum Edge-to-edge

Edge-to-edge Time Period T

Recommended Bit Rate

(Manchester)

(1)

Time Period T

of the

of the Data Signal During the

BR1 BR0

BR_Range

BR_Range0

BR_Range1

BR_Range2

BR_Range3

Data Signal

(2)

Start-up Period

(3)

1.0Kbit/s to 2.5Kbits/s

2.0Kbits/s to 5.0Kbits/s

4.0Kbits/s to 10.0Kbits/s

8.0Kbits/s to 20.0Kbits/s

200µs

100µs

50µs

200µs to 500µs

100µs to 250µs

50µs to 125µs

25µs to 62.5µs

25µs

Note:

If during the start-up period (T

Startup_PLL

+ T

Startup_Sig_Proc

) there is no RF signal, the data filter settles to the

noise floor, leading to noise on pin DATA_OU

Notes: 1.

As can be seen, a bit stream of, for example, 2.5Kbits/s can be received in BR_Range0 and BR_Range1

(overlapping BR_Ranges).

et the full sensitivity, always use the lowest possible BR_Range (here,

BR_Range0). The advantage in the next higher BR_Range (BR_Range1) is the shorter start-up period, mean-

ing lower current consumption during Polling mode. Thus, it is a decision between sensitivity and current

consumption.

2. The

receiver is also capable of receiving non-Manchester-modulated signals, such as PWM, PPM, VPWM,

NRZ. In ASK mode, the header and blanking periods occurring in Keeloq-like protocols (up to 52ms) are

supported.

nsure an accurate settling of the data filter during the start-up period (

Startup_PLL

Startup_Sig_Proc

), the

edge-to-edge time T

of the data signal (preamble) must be inside the given limits during this period.

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

Figure 6-1.

Examples of Supported Modulation Formats

MAN:

PWM:

Logic 0

Logic 1

Logic 0

Logic 1

VPWM:

On Transition Low to High

On Transition High to Low

Logic 0

Logic 1

PPM:

NRZ:

Logic 0

Logic 1

Figure 6-2.

Supported Header and Blanking Periods

Preamble

Header

Data Burst

Guard Time

Data Burst

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

ASK_NFSK

The ASK_NFSK pin allows the microcontroller to rapidly switch the RF front end between demodulation modes. A logic 1 on

this pin selects ASK mode, and a logic 0 FSK mode. The time to change modes (T

Startup_Sig_Proc

) depends on the bit rate

range being selected (not current bit rate range) and is given in

ble 5-4 on page 19

. This response time is specified for

applications that require an ASK preamble followed by FSK data (for typical TPM applications). During T

Startup_Sig_Proc

, the

level on pin DATA_OUT is low.

Figure 7-1.

ASK Preamble 2.4Kbits/s followed by FSK Data 9.6Kbits/s

ENABLE

BR1

BR0

ASK_NFSK

DATA_OUT

Data valid BR0

Data valid BR3

Startup_Sig_Proc

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

Polling Current Calculation

Figure 8-1.

Polling Cycle

ENABLE

Active

Standby

Supply

Standby

(= 1 / Signal_Bitrate (average)

Bitcheck

(Startup Signal Processing)

Startup_Sig_Proc

(Startup RF-PLL)

Startup_PLL

In an industrial or aftermarket RKE and TPM system, the average chip current in Polling mode, I

Polling

, is an important

parameter. The polling period must be controlled by the connected microcontroller via the pins ENABLE and RX. The polling

current can be calculated as follows:

_{Polling
= (T
Startup_PLL
/ T
Polling_Period
)
×
I
Startup_PLL
+ (T
Startup_Sig_Proc
/ T
Polling_Period
)
×
I
Active}

Bitcheck

/ T

Polling_Period

)

Active

+ (T

Polling_Period

– T

Startup_PLL

– T

Startup_Sig_Proc

– T

Bitcheck

) / T

Polling_Period

Standby

Startup_PLL

Startup_Sig_Proc

depends on 315MHz/433.92MHz application.

depends on 315MHz/433.92MHz application and the selected bit

rate range.

Bitcheck

Polling_Period

Startup_PLL

Active

depends on the signal bit rate (1 / Signal_Bit_Rate).

depends on the transmitter telegram (preburst).

depends on 3V or 5V application and the setting of pin CLK_OUT.

depends on 3V or 5V application, ASK or FSK mode and the setting of

pin CLK_OUT.

Standby

depends on 3V or 5V application and the setting of pin CLK_OUT.

Example:-

315-MHz application (ATA8201), bit rate: 9.6Kbits/s, T

Polling_Period

= 8ms

–> T

Startup_PLL

–> T

Startup_Sig_Proc

–> T

Bitcheck

269µs

324µs (Bit Rate Range 3)

104µs

3V application; ASK mode, CLK_OUT disabled

–> I

Startup_PLL

–> I

Active

–> I

Standby

4.5mA

6.5mA

0.05mA

–> I

Polling

= 0.545mA

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

3V Application

Figure 9-1.

3V Application

15nF

output

input

TEST2

TEST3

RSSI

TEST1

ATA8201/

ATA8202

CLK_OUT

CLK_OUT_CTRL1

SENSE_CTRL

SENSE

2.2pF

CLK_OUT_CTRL0

ENABLE

LNA_IN

68nH/36nH

LNA_GND

output

315MHz/433.92MHz

VSS VCC

68nF

18pF

68nF

= 2.7V to 3.3V

Note:

Paddle (backplane) must be connected to GND

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

10. 5V

Application

Figure 10-1. 5V Application with Reduced/Full Sensitivity

15nF

output

input

TEST2

TEST3

RSSI

TEST1

ATA8201/

ATA8202

CLK_OUT

CLK_OUT_CTRL1

SENSE_CTRL

SENSE

Sense

2.2pF

CLK_OUT_CTRL0

ENABLE

LNA_IN

LNA_GND

output

VSS VCC

68nH/36nH

315MHz/433.92MHz

68nF

18pF

2.2µF

68nF

= 4.5V to 5.5V

Note:

Paddle (backplane) must be connected to GND

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

11. Absolute

Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameters

Symbol

Min.

Max.

+150

+125

+85

Unit

°C

Junction temperature

Storage temperature

Ambient temperature

Supply voltage VS5V

stg

–55

–40

amb

ESD (Human Body Model ESD S 5.1)

every pin

HBM

–4

ESD (Machine Model JEDEC A115A)

every pin

–200

–500

+200

ESD (Field Induced Charge Device Model ESD

STM 5.3.1-1999) every pin

FCDM

in_max

+500

Maximum input level, input matched to 50

dBm

12. Thermal

Resistance

Parameters

Symbol

Value

Unit

K/W

Junction ambient

thJA

13. Electrical

Characteristics: General

All parameters refer to GND and are valid for T

amb

= 25°C, V

VS3V_AVCC

= V

VS5V

= 3

, and V

VS5V

= 5V. Typical values are given at

= 315MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the

specific sections of the “Electrical Characteristics”.

No. Parameters

Test Conditions

(1)

Symbol

Min.

Typ.

Max.

Unit Type*

1.1

OFF Mode

VS3V_AVCC

= V

VS5V

≤

VS5V

= 5V

CLK_OUT disabled

10, 11

µA

Supply current in OFF

mode

SOFF

Standby Mode

XTO running

VS3V_AVCC

= V

VS5V

≤

CLK_OUT disabled

10,11

Standby

100

µA

Supply current

Standby mode

2.1

XTO running

VS5V

= 5V

CLK_OUT disabled

Standby

XTO startup

XTAL: C

= 5f

= 1.8p

= 15

2.2 System

start-up time

XTO_Startup

0.3

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. Pin

numbers in parenthesis were measured with RF_IN matched to 50

according to

Figure 2-1 on page 6

with compo-

nent values as in

ble 2-2 on page 7

(RF

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

13. Electrical

Characteristics: General (Continued)

All parameters refer to GND and are valid for T

amb

= 25°C, V

VS3V_AVCC

= V

VS5V

= 3

, and V

VS5V

= 5V. Typical values are given at

= 315MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the

specific sections of the “Electrical Characteristics”.

No. Parameters

Test Conditions

(1)

Symbol

Min.

Typ.

Max.

Unit Type*

From Standby mode to

Active mode

BR_Range_3

Atmel ATA5745

Atmel ATA5746

Startup_PLL

Startup_Sig_Pro

Active mode start-up

time

2.3

565

593

µs

Active Mode

Atmel ATA8201

Atmel ATA8202

313

433

317

435

MHz

RF operating frequency

range

3.1

VS3V_AVCC

= V

VS5V

= 3V

ASK mode

CLK_OUT disabled

SENSE_CTRL = 0

10,11

Active

6.5

6.7

6.9

VS3V_AVCC

= V

VS5V

= 3V

FSK mode

CLK_OUT disabled

SENSE_CTRL = 0

Supply current Active

mode

3.2

VS5V

= 5V

ASK mode

CLK_OUT disabled

SENSE_CTRL = 0

VS5V

= 5V

FSK mode

CLK_OUT disabled

SENSE_CTRL = 0

VS3V_AVCC

= V

VS5V

= 3V

Polling_Period

= 8ms

BR_Range_3, ASK

mode, CLK_OUT

disabled

Supply current Polling

mode

3.3

10,11

Polling

545

µA

Data rate = 9.6Kbits/s

FSK deviation

DEV

= ±38kHz

BER = 10

–

amb

= 25°C

Bit rate 9.6Kbits/s BR2

Bit rate 2.4Kbits/s BR0

(14)

REF_FSK

–103

–106

–105

–108

–106.5 dBm

–109.5 dBm

Input sensitivity FSK

3.4

_{RF
= 315MHz}

FSK deviation ±18kHz to

±50kHz

Bit rate 9.6Kbits/s BR2

Bit rate 2.4Kbits/s BR0

(14)

REF_FSK

–101

–104

dBm

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. Pin

numbers in parenthesis were measured with RF_IN matched to 50

according to

Figure 2-1 on page 6

with compo-

nent values as in

ble 2-2 on page 7

(RF

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

13. Electrical

Characteristics: General (Continued)

All parameters refer to GND and are valid for T

amb

= 25°C, V

VS3V_AVCC

= V

VS5V

= 3

, and V

VS5V

= 5V. Typical values are given at

= 315MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the

specific sections of the “Electrical Characteristics”.

No. Parameters

Test Conditions

(1)

Symbol

Min.

Typ.

Max.

Unit Type*

ASK 100% level of

carrier, BER = 10

–

amb

= 25°C

Input sensitivity ASK

= 315MHz

3.5

3.6

Bit rate 9.6Kbits/s BR2

Bit rate 2.4Kbits/s BR0

(14)

REF_ASK

–109

–112

–111

–114

–112.5 dBm

–115.5 dBm

Sensitivity change at

= 433.92MHz

compared to

= 315MHz to

= 433.92MHz

P = P

REF_ASK

REF1

P = P

REF_FSK

REF1

(14)

REF1

_{RF
= 315MHz}

FSK f

DEV

= ±38kHz

OFFSET

≤

±160kHz

Sensitivity change

versus temperature,

supply voltage and

frequency offset

ASK 100%

OFFSET

≤

±160kHz

P = P

REF_ASK

REF1

REF2

3.7

(14)

REF2

+4.5

–1.5

P = P

REF_FSK

REF1

REF2

Sense

connected from

pin SENSE to

pin VS3V_AVCC

dBm

(peak

level)

Ref_Red

Sense

= 62k

= 433.92MHz

–76

–88

–76

–88

dBm

Reduced sensitivity

Sense

= 82k

= 433.92MHz

3.8

Sense

= 62k

= 315MHz

Sense

= 82k

= 315MHz

Reduced sensitivity

variation over full

operating range

Sense

= 62k

Sense

= 82k

Red

= P

Ref_Red

+ P

Red

–10

+10

Maximum frequency

difference of f

between

receiver and transmitter

in FSK mode (f

is the

center frequency of the

FSK signal with

Maximum frequency

offset in FSK mode

3.9

(14)

OFFSET

–160

+160

kHz

BIT

= 10Kbits/s

DEV

= ±38kHz

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. Pin

numbers in parenthesis were measured with RF_IN matched to 50

according to

Figure 2-1 on page 6

with compo-

nent values as in

ble 2-2 on page 7

(RF

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

13. Electrical

Characteristics: General (Continued)

All parameters refer to GND and are valid for T

amb

= 25°C, V

VS3V_AVCC

= V

VS5V

= 3

, and V

VS5V

= 5V. Typical values are given at

= 315MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the

specific sections of the “Electrical Characteristics”.

No. Parameters

Test Conditions

(1)

Symbol

Min.

Typ.

Max.

Unit Type*

With up to 2dB

loss of sensitivity.

Note that the tolerable

frequency offset is 12kHz

lower for f

DEV

= ±50kHz

than for f

DEV

= ±38kHz,

hence,

Supported FSK

3.10

(14)

DEV

±18

±38

±50

kHz

frequency deviation

OFFSET

≤

±148kHz

= 315MHz

(14)

6.0

7.0

3.11 System

noise figure

= 433.92MHz

= 315MHz

440

kHz

3.12 Intermediate

frequency

3dB bandwidth

This value is for

information only!

Note that for crystal and

system frequency offset

calculations,

OFFSET

must be used.

3.13 System

bandwidth

(14)

SBW

IIP3

435

kHz

meas1

= 1.8MHz

meas2

= 3.6MHz

= 315MHz

System out-band

3.14 3rd-order

input intercept

point

–24

dBm

= 433.92MHz

(14)

IIP3

–23

–31

dBm

meas1

= 1MHz

= 315MHz

I1dBCP

–36

–35

System outband input 1-

3.15

dB compression point

= 433.92MHz

= 315MHz

(14)

I1dBCP

in_LNA

IN_max

–30

(72.4 – j298)

(55 – j216)

dBm

3.16 LNA

input impedance

= 433.92MHz

–

BER < 10

, ASK: 100%

FSK: f

DEV

= ±38kHz

f < 1GHz

(14)

–10

–57

–47

dBm

Maximum peak RF input

3.17

level, ASK and FSK

f >1GHz

= 315.44MHz

–90

–94

–68

(14)

dBm

3.18 LO

spurs at LNA_IN

= 434.36MHz

–92

–88

–58

With the complete image

band

= 315MHz

3.19 Image

rejection

(14)

= 433.92MHz

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. Pin

numbers in parenthesis were measured with RF_IN matched to 50

according to

Figure 2-1 on page 6

with compo-

nent values as in

ble 2-2 on page 7

(RF

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

13. Electrical

Characteristics: General (Continued)

All parameters refer to GND and are valid for T

amb

= 25°C, V

VS3V_AVCC

= V

VS5V

= 3

, and V

VS5V

= 5V. Typical values are given at

= 315MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the

specific sections of the “Electrical Characteristics”.

No. Parameters

Test Conditions

(1)

Symbol

Min.

Typ.

Max.

Unit Type*

Peak level of useful

signal to peak level of

interferer for BER < 10

–

with any modulation

scheme of interferer

Useful signal to interferer

ratio

3.20

FSK BR_Ranges 0, 1, 2

FSK BR_Range_3

(14)

SNR

FSK0-2

SNR

FSK3

SNR

ASK

RSSI

ASK (P

< P

RFIN_High

Dynamic range

)

(14)

(14),17

Lower level of range

= 315MHz

= 433.92MHz

(14),17

RFIN_Low

–110

dBm

3.21 RSSI

output

Upper level of range

= 315MHz

= 433.92MHz

RFIN_High

–45

Gain

(14),17

mV/dB

Output voltage range

RSSI

350

1675

12.5

Output resistance

RSSI pin

3.22

–

Sensitivity (BER = 10

)

is reduced by 3dB if a

continuous wave blocking

signal at ±

f is

Block

higher than the useful

signal level

(Bit rate = 10Kbits/s,

FSK, f

DEV

± 38kHz,

Manchester code,

BR_Range2)

= 315MHz

f ±1.5MHz

f ±2MHz

f ±3MHz

f ±10MHz

f ±20MHz

3.23 Blocking

57.5

63.0

67.5

72.0

74.0

(14)

Block

dBC

= 433.92MHz

f ±1.5MHz

f ±2MHz

f ±3MHz

f ±10MHz

f ±20MHz

56.5

62.0

66.5

71.0

73.0

(14)

Block

dBC

Capacitor connected to

pin 23 (CDEM)

3.24 CDEM

–5%

+5%

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. Pin

numbers in parenthesis were measured with RF_IN matched to 50

according to

Figure 2-1 on page 6

with compo-

nent values as in

ble 2-2 on page 7

(RF

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

13. Electrical

Characteristics: General (Continued)

All parameters refer to GND and are valid for T

amb

= 25°C, V

VS3V_AVCC

= V

VS5V

= 3

, and V

VS5V

= 5V. Typical values are given at

= 315MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the

specific sections of the “Electrical Characteristics”.

No. Parameters

Test Conditions

(1)

Symbol

Min.

Typ.

Max.

Unit Type*

XTO

At startup; after startup

the amplitude is regulated

to V

PPXTAL

Transconductance XTO

at start

4.1

7,8

m, XTO

≤

2.2pF

< 14fF

≤

120

4.2 XTO

start-up time

7,8

XTO_Startup

0max

300

µs

4.3 Maximum

of XTAL

Pulling of LO frequency

3.8

1.0pF

≤

2.2pF

= 4.0fF to 7.0fF

due to XTO, C

and

versus temperature

4.4

XTO

–5

ppm

≤

120

and supply changes

= 5f

= 1.8pF

_m
=
15
Ω

Amplitude XTAL after

startup

V(XTAL1, XTAL2)

peak-to-peak value

4.5

7,8

PPXTAL

700

350

mVpp

V(XTAL1)

peak-to-peak value

≤

2.2p

mall signal

start impedance, this

value is important for

crystal oscillator startup

Maximum series

4.6 resistance

of XTAL at

startup

7,8

XTAL12_START

–1400

–2000

Maximum series

4.7 resistance

of XTAL

after startup

≤

2.2pF

< 14fF

7,8

m_max

120

Nominal XTAL load

4.8

= 433.92MHz

= 315MHz

13.57375

13.1433

XTAL

MHz

resonant frequency

CLK_OUT_CRTL1 = 0

CLK_OUT_CTRL0 = 0

–> CLK_OUT disabled

CLK

disabled (low level on pin

CLK_OUT)

CLK_OUT_CRTL1 = 0

CLK_OUT_CTRL0 = 1

–> division ratio = 3

XTO

———–

CLK

External CLK_OUT

frequency

4.9

CLK_OUT

MHz

CLK_OUT_CRTL1 = 1

CLK_OUT_CTRL0 = 0

–> division ratio = 6

XTO

———–

CLK_OUT_CRTL1 = 1

CLK_OUT_CTRL0 = 1

–> division ratio = 12

XTO

———–

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. Pin

numbers in parenthesis were measured with RF_IN matched to 50

according to

Figure 2-1 on page 6

with compo-

nent values as in

ble 2-2 on page 7

(RF

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

13. Electrical

Characteristics: General (Continued)

All parameters refer to GND and are valid for T

amb

= 25°C, V

VS3V_AVCC

= V

VS5V

= 3

, and V

VS5V

= 5V. Typical values are given at

= 315MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the

specific sections of the “Electrical Characteristics”.

No. Parameters

Test Conditions

(1)

Symbol

Min.

Typ.

Max.

Unit Type*

= 433.92MHz

CLK_OUT division ratio

= 3

= 6

= 12

4.52458

2.26229

1.13114

CLK_OUT

MHz

CLK_OUT has nominal

50% duty cycle

= 315MHz

CLK_OUT division ratio

= 3

= 6

4.3811

2.190

CLK_OUT

MHz

= 12

1.0952

CLK_OUT has nominal

50% duty cycle

(XTAL1, XTAL2)

4.10 DC

voltage after startup

XTO running (Standby

mode, Active mode)

7,8

DCXTO

–250

–45

Synthesizer

At ±f

CLK_OUT

CLK_OUT enabled

(division ratio = 3)

= 315MHz

–75

–70

dBC

5.1 Spurs

in Active mode

= 433.92MHz

at ±f

XTO

= 315MHz

= 433.92MHz

Phase noise at 3 MHz

Active mode

= 315MHz

= 433.92MHz

5.2

RX3M

–130

–135

–127 dBC/Hz

–132 dBC/Hz

Phase noise at 20 MHz

Active mode

5.3

Noise floor

RX20M

Microcontroller Interface

CLK_OUT

< 4.5MHz

= 10pF

= Load capacitance on

pin CLK_OUT

2.7V

≤

VS5V

≤

3.3V or

4.5V

≤

VS5V

≤

5.5V

20% to 80% V

VS5V

rise

fall

CLK_OUT output rise

and fall time

6.1

Internal equivalent

capacitance

Used for current

calculation

6.2

CLK_OUT

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. Pin

numbers in parenthesis were measured with RF_IN matched to 50

according to

Figure 2-1 on page 6

with compo-

nent values as in

ble 2-2 on page 7

(RF

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

14. Electrical

Characteristic: 3V Application

All parameters refer to GND and are valid for T

amb

= 25°C, V

VS3V_AVCC

= V

VS5V

= 3V and V

VS5V

= 5V. Typical values are given at

= 433.92MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the

specific sections of the “Electrical Characteristics”.

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

3V Application

Supply current in OFF

VS3V_AVCC

= V

VS5V

≤

7.1

10, 11

SOFF

µA

mode

CLK_OUT disabled

VS3V_AVCC

= V

VS5V

≤

external load C on pin

CLK_OUT = 12pF

CLK enabled

420

290

220

Current in Standby

(division ratio 3)

7.2

10, 11

Standby

µA

mode (XTO is running)

CLK enabled

(division ratio 6)

CLK enabled

(division ratio 12)

CLK disabled

Current during

Startup_PLL

VS3V_AVCC

= V

VS5V

≤

CLK disabled

7.3

7.4

10, 11

Startup_PLL

4.5

VS3V_AVCC

= V

VS5V

≤

CLK disabled

SENSE_CTRL = 0

Current in Active mode

ASK

Active

6.5

6.7

VS3V_AVCC

= V

VS5V

≤

CLK disabled

Current in Active mode

FSK

7.5

10, 11

Active

SENSE_CTRL = 0

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

15. Electrical

Characteristics: 5V Application

All parameters refer to GND and are valid for T

amb

= 25°C, V

VS3V_AVCC

= V

VS5V

= 3V and V

VS5V

= 5V. Typical values are given at

= 433.92MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the

specific sections of the “Electrical Characteristics”.

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

5V Application

Supply current in OFF

VS5V

= 5V

8.1

SOFF

µA

mode

CLK_OUT disabled

VS5V

≤

external load C on pin

CLK_OUT = 12pF

CLK enabled

700

490

370

Current in Standby

(division ratio 3)

8.2

Standby

µA

mode (XTO is running)

CLK enabled

(division ratio 6)

CLK enabled

(division ratio 12)

CLK disabled

Current during

Startup_PLL

VS5V

= 5V

CLK disabled

8.3

8.4

Startup_PLL

4.7

VS5V

= 5V

CLK disabled

SENSE_CTRL = 0

Current in Active mode

ASK

Active

6.7

6.9

VS5V

= 5V

CLK disabled

SENSE_CTRL = 0

Current in Active mode

FSK

8.5

Active

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

16. Digital

Timing Characteristics

All parameters refer to GND and are valid for T

amb

= 25°C, V

VS3V_AVCC

= V

VS5V

= 3

, and V

VS5V

= 5V. Typical values are given at

= 433.92MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the

specific sections of the “Electrical Characteristics”

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

Basic Clock Cycle of the Digital Circuitry

Basic clock cycle

9.1

DCLK

16 / f

XTO

16 / f

XTO

µs

BR_Range_0

BR_Range_1

Extended basic clock

BR_Range_2

9.2

XDCLK

µs

cycle

BR_Range_3

DCLK

Active Mode

15 µs +

208

DCLK

10.1 Startup

PLL

Startup_PLL

BR_Range_0

BR_Range_1

BR_Range_2

BR_Range_3

929.5

545.5

Startup_Sig_Proc

353.5

257.5

929.5

545.5

353.5

257.5

DCLK

Startup signal

10.2

processing

DCLK

ASK

BR_Range =

BR_Range0

BR_Range1

BR_Range2

BR_Range3

FSK

1.0

2.0

4.0

2.5

5.0

10.0

8.0

10.3 Bit

rate range

BR_Range

Kbits/s

BR_Range =

BR_Range0

BR_Range1

BR_Range2

BR_Range3

1.0

2.0

4.0

8.0

2.5

5.0

10.0

20.0

BR_Range_0

BR_Range_1

BR_Range_2

BR_Range_3

Minimum time period

10.4 between

edges at pin

DATA_OUT

DATA_OUT_min

XDCLK

µs

Edge-to-edge time

period of the data

BR_Range_0

BR_Range_1

signal for full sensitivity

BR_Range_2

200

500

250

125

62.5

100

10.5

DATA_OUT

in Active mode

BR_Range_3

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

17. Digital

Port Characteristics

All parameters refer to GND and are valid for T

amb

= 25°C, V

VS3V_AVCC

= V

VS5V

= 3

, and V

VS5V

= 5V. Typical values are given at

= 433.92MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the

specific sections of the “Electrical Characteristics”

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

Digital Ports

= V

VS3V_AVCC

VS5V

= 2.7V to 3.3V

0.2

ENABLE input

– Low level input

voltage

= V

VS5V

0.12

4.5V to 5.5V

11.1

= V

VS3V_AVCC

VS5V

= 2.7V to 3.3V

– High level input

voltage

0.8

= V

VS5V

= 4.5V to

5.5V

= V

VS3V_AVCC

0.2

VS5V

= 2.7V to 3.3V

RX input

– Low level input voltage

= V

VS5V

0.12

4.5V to 5.5V

11.2

11.3

11.4

11.5

= V

VS3V_AVCC

VS5V

= 2.7V to 3.3V

– High level input

voltage

0.8

= V

VS5V

4.5V to 5.5V

= V

VS3V_AVCC

0.2

BR0 input

– Low level input

voltage

VS5V

= 2.7V to 3.3V

= V

VS5V

0.12

4.5V to 5.5V

= V

VS3V_AVCC

VS5V

= 2.7V to 3.3V

– High level input

voltage

= V

VS5V

4.5V to 5.5V

= V

VS3V_AVCC

BR1 input

– Low level input

voltage

VS5V

= 2.7V to 3.3V

0.2

= V

VS5V

0.12

4.5V to 5.5V

= V

VS3V_AVCC

VS5V

= 2.7V to 3.3V

– High level input

voltage

= V

VS5V

4.5V to 5.5V

= V

VS3V_AVCC

ASK_NFSK input

– Low level input

voltage

VS5V

= 2.7V to 3.3V

0.2

= V

VS5V

0.12

4.5V to 5.5V

= V

VS3V_AVCC

VS5V

= 2.7V to 3.3V

= V

VS5V

4.5V to 5.5V

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

– High level input

voltage

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

17. Digital

Port Characteristics (Continued)

All parameters refer to GND and are valid for T

amb

= 25°C, V

VS3V_AVCC

= V

VS5V

= 3

, and V

VS5V

= 5V. Typical values are given at

= 433.92MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the

specific sections of the “Electrical Characteristics”

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

= V

VS3V_AVCC

VS5V

= 2.7V to 3.3V

0.2

SENSE_CTRL input

– Low level input

voltage

= V

VS5V

0.12

4.5V to 5.5V

11.6

11.7

11.8

= V

VS3V_AVCC

VS5V

= 2.7V to 3.3V

– High level input

voltage

0.8

= V

VS5V

4.5V to 5.5V

= V

VS3V_AVCC

VS5V

= 2.7V to 3.3V

CLK_OUT_CTRL0

input

– Low level input

voltage

0.2

= V

VS5V

0.12

4.5V to 5.5V

= V

VS3V_AVCC

VS5V

= 2.7V to 3.3V

– High level input

voltage

0.8

= V

VS5V

4.5V to 5.5V

= V

VS3V_AVCC

VS5V

= 2.7V to 3.3V

CLK_OUT_CTRL1

input

– Low level input

voltage

0.2

= V

VS5V

0.12

4.5V to 5.5V

= V

VS3V_AVCC

VS5V

= 2.7V to 3.3V

– High level input

voltage

0.8

= V

VS5V

4.5V to 5.5V

TEST1 input must

always be connected

directly to GND

11.9 TEST1

input

11.10 TEST2

output

11.11 TEST3

input

TEST2 output must

always be connected

directly to GND

TEST3 input must

always be connected

directly to GND

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

17. Digital

Port Characteristics (Continued)

All parameters refer to GND and are valid for T

amb

= 25°C, V

VS3V_AVCC

= V

VS5V

= 3

, and V

VS5V

= 5V. Typical values are given at

= 433.92MHz unless otherwise specified. Details about current consumption, timing, and digital pin properties can be found in the

specific sections of the “Electrical Characteristics”

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

= V

VS3V_AVCC

VS5V

= 2.7V to 3.3V

DATA_OUT output

– Saturation voltage low

= V

VS5V

0.15

0.4

4.5V to 5.5V

DATA_OUT

= 250µA

11.12

= V

VS3V_AVCC

VS5V

= 2.7V to 3.3V

– Saturation voltage

high

–

0.15

= V

VS5V

– 0.4

4.5V to 5.5V

DATA_OUT

= –250µA

= V

VS3V_AVCC

VS5V

= 2.7V to 3.3V

CLK_OUT output

– Saturation voltage low

= V

VS5V

0.15

0.4

4.5V to 5.5V

DATA_OUT

= 100µA

11.13

= V

VS3V_AVCC

VS5V

= 2.7V to 3.3V

– Saturation voltage

high

–

0.15

= V

VS5V

– 0.4

4.5V to 5.5V

DATA_OUT

= –100µA

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

18. Ordering

Information

Extended Type Number

ATA8202C-PXQW-1

ATA8201C-PXQW-1

Package

QFN24

MOQ

Remarks

6000pcs

5mm

5mm, Pb-free, 433.92MHz

5mm

5mm, Pb-free, 315MHz

19. Package

Information

Top View

PIN 1 ID

technical drawings

according to DIN

specifications

Dimensions in mm

Side View

Bottom View

COMMON DIMENSIONS

(Unit of Measure = mm)

Symbol MIN

NOM

0.85

0.035

0.21

MAX NOTE

0.8

0.9

0.05

0.26

5.1

0.0

0.16

4.9

3.5

3.6

3.7

4.9

5.1

Z 10:1

3.5

3.6

3.7

0.35

0.2

0.4

0.45

0.3

0.25

0.65

10/18/13

TITLE

DRAWING NO.

GPC

Package Drawing Contact:

packagedrawings@atmel.com

Package: VQFN_5x5_24L

Exposed pad 3.6×3.6

6.543-5132.02-4

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

20. Revision

History

Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this

document.

Revision No.

History

•

Section 18 “Ordering Information” on page 39 updated

•

Section 19 “Package Information” on page 39 updated

•

Put datasheet in the latest template

4971G-INDCO-09/14

4971F-INDCO-07/14

4971E-INDCO-12/12

•

Section 18 “Ordering Information” on page 39 changed

•

Section 13 “Electrical Characteristics: General” on pages 26 to 32 changed

•

Section 14 “Electrical Characteristic: 3V Application” on page 33 changed

•

Section 15 “Electrical Characteristic: 5V Application” on page 34 changed

•

Section 18 “Ordering Information” on page 39 changed

•

Put datasheet in the newest template

4971D-INDCO-07/12

4971C-INDCO-04/09

4971B-INDCO-10/07

•

Benefits on page 2 updated

•

Put datasheet in the newest template

ATA8201/ATA8202 [DATASHEET]

4971G–INDCO–09/14

X X X X

Atmel Corporation

1600 Technology Drive, San Jose, CA 95110 USA

(+1)(408) 441.0311

(+1)(408) 436.4200

www.atmel.com

Atmel

, Atmel logo and combinations thereof, Enabling Unlimited Possibilities

, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and

other countries. Other terms and product names may be trademarks of others.

DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right

is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE

ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS

INCLUDIN

UT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILIT

ITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMEN

N NO EVENT

SHALL ATMEL BE LIABLE FOR ANY DIREC

NDIREC

ONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDIN

ITHOUT LIMITATION, DAMAGES

FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMEN

VEN IF ATMEL HAS

BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this

document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information

contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended,

authorized, or warranted for use as components in applications intended to support or sustain life.

SAFET

-CRITICAL, MILITAR

ND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where

the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer’s specific written

consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems.

Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are

not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade.

Microchip-Tech-ATA8202C-PXQW-1

Related Posts

CUI-CPE-171

DB-Unlimited-TP243408-1

DB-Unlimited-TE054003-2