Microchip-Tech-ATBTLC1000A-UU-T

ATBTLC1000 WLCSP SoC  

Ultra Low Power BLE 4.1 SoC  

DATASHEET  

Description  

The Atmel

®

ATBTLC1000 is an ultra-low power Bluetooth

®

SMART (BLE 4.1) System  

on a Chip with Integrated MCU, Transceiver, Modem, MAC, PA, TR Switch, and  

Power Management Unit (PMU). It can be used as a Bluetooth Low Energy link  

controller or data pump with external host MCU or as a standalone applications  

processor with embedded BLE connectivity and external memory.  

The qualified Bluetooth Smart protocol stack is stored in dedicated ROM. The  

firmware includes L2CAP service layer protocols, Security Manager, Attribute  

protocol (ATT), Generic Attribute Profile (GATT), and the Generic Access Profile  

(GAP). Additionally, application profiles such as Proximity, Thermometer, Heart Rate,  

Blood Pressure, and many others are supported and included in the protocol stack.  

Features  



Complies with Bluetooth V4.1, ETSI EN 300 328 and EN 300 440 Class 2, FCC  

CFR47 Part 15 and ARIB STD-T66  



2.4GHz transceiver and modem  

–

-95dBm/-93dBm programmable receiver sensitivity  

–

-20 to +3.5dBm programmable TX output power  

–

Integrated T/R switch  

–

Single wire antenna connection  



ARM

®

Cortex

®

-M0 32-bit processor  

–

Single wire Debug (SWD) interface  

–

Four-channel DMA controller  

–

Brownout detector and Power On Reset  

–

Watch Dog Timer  



Memory  

–

128kB embedded RAM (96kB available for application)  

–

128kB embedded ROM  



Hardware Security Accelerators  

–

AES-128  

–

SHA-256  



Peripherals  

–

10 digital and one wakeup GPIOs with 96k

Ω

internal pull-up resistors, one Mixed  

Signal GPIO  

–

2x SPI Master/Slave  

–

2x I

2

C Master/Slave and 1x I

2

C Slave  

–

2x UART  

–

1x SPI Flash  

–

Three-Axis quadrature decoder  

–

4x Pulse Width Modulation (PWM), three General Purpose Timers, and one  

Wakeup Timer  

Atmel-42493D-ATBTLC1000_WLCSP_SoC-Datasheet_02/2016  

–

1-channel 11-bit ADC  



Clock  

–

Integrated 26MHz RC oscillator  

–

26MHz crystal oscillator  

–

Integrated 2MHz sleep RC oscillator  

–

32.768kHz RTC crystal oscillator  



Ultra-low power  

–

1.1µA sleep current (8KB RAM retention and RTC running)  

–

3.0mA peak TX current (0dBm, 3.6V)  

–

4.0mA peak RX current (3.6V, -93dBm sensitivity)  

–

9.7µA average advertisement current (three channels, 1s interval)  



Integrated Power management  

–

1.8 to 4.3V battery voltage range  

–

Fully integrated Buck DC/DC converter  



Bluetooth SIG Certification  

–

QD ID Controller (see declaration

–

QD ID Host (see declaration

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ATBTLC1000 WLCSP SoC [DATASHEET]  

Atmel-42493D-ATBTLC1000_WLCSP_SoC-Datasheet_02/2016  

Table of Contents  

C Master/Slave Interface …………………………………………………………………………………………………..

C Interface Timin

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ATBTLC1000 WLCSP SoC [DATASHEET]  

Atmel-42493D-ATBTLC1000_WLCSP_SoC-Datasheet_02/2016  

1

2

Ordering Information  

Ordering code  

Package  

31L WLCSP  

Description  

ATBTLC1000 Tape and Reel  

ATBTLC1000A-UU-T  

Package Information  

Table 2-1.  

ATBTLC1000 31L WLCSP Package Information  

Parameter  

Value  

2.262 × 2.142  

0.502  

Tolerance  

±0.03  

Units  

Package size  

Total thickness  

I/O pitch  

±0.039  

mm  

0.35  

Ball diameter  

Ball count  

0.2  

±0.03  

31  

3

Block Diagram  

Figure 3-1.  

ATBTLC1000 Block Diagram  

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ATBTLC1000 WLCSP SoC [DATASHEET]  

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4

Pinout Information  

The ATBTLC1000 is offered in a 0.35mm-pitch staggered SAC405 balls 31L WLCSP package. The WLCSP  

package pin assignment is shown i

The color shading is used to indicate the pin type as follows:  











Red

–

analog  

Green

–

digital I/O (switchable power domain)  

Blue

–

digital I/O (always-on power domain)  

Yellow

–

digital power, purple

–

PMU  

Green/red

–

configurable mixed-signal GPIO (digital/analog)  

The ATBTLC1000 pins are described in

Figure 4-1.

 

ATBTLC1000 WLCSP Pin Assignment  

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ATBTLC1000 WLCSP SoC [DATASHEET]  

Atmel-42493D-ATBTLC1000_WLCSP_SoC-Datasheet_02/2016  

Table 4-1.  

ATBTLC1000 WLCSP Pin Description  

Pin #  

A2  

A4  

A6  

B1  

B3  

B5  

B7  

C2  

C4  

C6  

D1  

D3  

D5  

D7  

E2  

E4  

E6  

F1  

Pin Name  

Pin Type  

Digital Power  

Analog/RF  

Analog/RF  

Digital I/O  

Digital Power  

Analog/RF  

Analog/RF  

PMU  

Description / Default Function  

I/O Supply, can be less than or equal to VBATT_BUCK  

XO Crystal +  

VDDIO  

XO_P  

VDD_VCO & VDD_SXDIG  

AO_GPIO_0  

VDDIO_SWITCH  

XO_N  

Synthesizer VCO and Digital Supplies 1.2V  

Always-on External Wakeup  

I/O supply switch for external flash  

XO Crystal –  

RFIO  

RX input and TX output  

RTC_CLK_P  

TPP  

RTC terminal + / 32.768kHz XTAL +  

Test MUX + output  

Analog/RF  

Analog/RF  

PMU  

VDD_RF  

RF Supply 1.2V  

RTC_CLK_N  

LP_GPIO_13  

LP_GPIO_0  

RFGND  

RTC terminal

–

/ 32.768kHz XTAL –  

SPI MISO/SPI FLASH RXD  

SWD Clock  

Digital I/O  

Digital I/O  

Analog/RF  

PMU  

RF Ground  

CHIP_EN  

Master Enable for chip  

VSS  

Digital Power  

Analog/RF  

PMU  

Digital I/O and Core Ground  

AMS Supply 1.2V  

VDD_AMS  

LP_LDO_OUT_1P2  

GPIO_MS1  

Low Power LDO output (connect to 1µF decoupling cap)  

F3  

Mixed Signal I/O  

Configurable to be a GPIO Mixed Signal only (ADC inter-  

face)  

F5  

F7  

G2  

G4  

G6  

H1  

H3  

H5  

H7  

J2  

LP_GPIO_11  

LP_GPIO_1  

VBATT_BUCK  

LP_GPIO_12  

LP_GPIO_2  

VDDC_PD4  

GND_BUCK  

LP_GPIO_9  

LP_GPIO_3  

VSW  

Digital I/O  

Digital I/O  

PMU  

SPI MOSI/SPI FLASH TXD  

SWD I/O  

DC/DC Converter Supply and General Battery Connection  

SPI SSN/SPI FLASH SSN  

Digital I/O  

Digital I/O  

PMU  

UART RXD  

DC/DC Converter 1.2V output and feedback node  

DC/DC Converter Ground  

PMU  

Digital I/O  

Digital I/O  

PMU  

I

2

C SCL (high-drive pad, see

UART TXD  

DC/DC Converter Switching Node  

SPI SCK/SPI FLASH SCK  

J4  

LP_GPIO_10  

LP_GPIO_8  

Digital I/O  

Digital I/O  

J6  

I

2

C SDA (high-drive pad, see

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ATBTLC1000 WLCSP SoC [DATASHEET]  

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Package Drawing  

The ATBTLC1000 WLCSP package is RoHS/green compliant.  

Figure 5-1.  

ATBTLC1000 31L WLCSP Package Outline Drawing  

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ATBTLC1000 WLCSP SoC [DATASHEET]  

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6

Power Management  

6.1  

Power Architecture  

ATBTLC1000 uses an innovative power architecture to eliminate the need for external regulators and reduce the  

number of off-chip components. The integrated power management block includes a DC/DC buck converter and  

separate Low Drop out (LDO) regulators for different power domains. The DC/DC buck converter converts battery  

voltage to a lower internal voltage for the different circuit blocks and does this with high efficiency. The DC/DC  

requires three external components for proper operation (two inductors L 4.7µH and 9.1nH, and one capacitor C  

4.7µF).  

Figure 6-1.  

ATBTLC1000 Power Architecture  

RF/AMS  

VDD_VCO  

LDO2  

1.0V  

SX  

~

VDD_AMS,  

VDD_RF,  

VDD_SXDIG  

RF/AMS Core  

D

i

gital  

VDDIO  

Pads  

Digital Core  

e

F

u

se  

dcdc_e

n

a  

PMU  

Digital Core Voltage  

2.5V  

Sleep  

Osc  

EFuse  

LDO  

Dig Core  

LDO  

e

n

a  

LP LDO  

e

n

a  

CHIP_EN  

VDDC_PD4  

VSW  

e

n

a  

DC/DC Converter  

VBATT_BUCK  

Off-Chip  

LC  

V

i

n  

V

o

ut  

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Atmel-42493D-ATBTLC1000_WLCSP_SoC-Datasheet_02/2016  

6.2  

DC/DC Converter  

The DC/DC Converter is intended to supply current to the BLE digital core and the RF transceiver core. The  

DC/DC consists of a power switch, 26MHz RC oscillator, controller, external inductor, and external capacitor. The  

DC/DC is utilizing pulse skipping discontinuous mode as its control scheme. The DC/DC specifications are shown  

in the following tables and figures.  

Table 6-1.  

DC/DC Converter Specifications (Performance is Guaranteed for (L) 4.7µH and (C) 4.7µF  

Parameter  

Symbol  

Min.  

Typ.  

Max.  

Unit  

Note  

Dependent on external component values  

and DC/DC settings with acceptable effi-  

ciency  

Output current capability  

I

REG  

0

10  

30  

mA  

4.7  

-10%  

External capacitor range  

External inductor range  

C

EXT  

4.7  

4.7  

20  

µF  

µH  

External capacitance range  

External inductance range  

2.2  

-10%  

4.7  

+10%  

L

EXT  

Battery voltage  

V

BAT  

V

REG  

I

DD  

2.35  

1.05  

3

4.3  

Functionality and stability given  

25mV step size  

V

Output voltage range  

Current consumption  

1.2  

125  

1.47  

µA  

µs  

DC/DC quiescent current  

Dependent on external component values  

and DC/DC settings  

Startup time  

t

startup  

50  

5

600  

30  

Dependent on external component values  

and DC/DC settings  

Voltage ripple  

ΔV

REG  

10  

mV  

%

Efficiency  

η

85  

0

Measured at 3V VBAT, at load of 10mA  

No overshoot, no output pre-charge  

From 1.8 to 4.3V  

Overshoot at startup  

Line Regulation  

Load regulation  

V

OS  

ΔV

REG  

ΔV

REG  

10  

5

mV  

From 0 to 10mA  

Table 6-2.  

DC/DC Converter Allowable Onboard Inductor and Capacitor Values (VBAT = 3V)  

Vripple [mV]  

Inductor [µH]  

Efficiency [%]  

RX Sensitivity

(1)

[dBm]  

C=2.2µF C=4.7µF

 

C=10µF  

2.2  

4.7  

83  

85  

N/A  

9

<5  

5

<5  

<5  

~1.5 dB degrade  

~0.7 dB degrade  

Note:  

1. Degradation

 

relative to design powered by external LDO and DC/DC disabled.  

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Figure 6-2.  

DC/DC Converter Efficiency  

Efficiency vs. Battery Voltage  

95.0  

90.0  

85.0  

80.0  

75.0  

70.0  

2

2.2  

2.4  

2.6  

2.8  

3

3.2  

3.4  

3.6  

3.8  

4

4.3  

Battery Voltage (V)  

Efficiency vs. Load Current  

86.0  

85.0  

84.0  

83.0  

82.0  

81.0  

80.0  

79.0  

78.0  

77.0  

3

4

5

6

7

8

9

10  

11  

12  

13  

14  

15  

Load Current (mA)  

6.3  

Power Consumption  

6.3.1 Description

 

of Device States  

ATBTLC1000 has multiple device states, depending on the state of the ARM processor and BLE subsystem.  

Note: The

 

ARM is required to be powered on if the BLE subsystem is active.  











BLE_On_Transmit

–

Device is actively transmitting a BLE signal (Application may or may not be active)  

BLE_On_Receive

–

Device is actively receiving a BLE signal (Application may or may not be active)  

MCU_Only

–

Device has ARM processor powered on and BLE subsystem powered down  

Ultra_Low_Power

–

BLE is powered down and Application is powered down (with or without RAM retention)  

Power_Down

–

Device core supply off  

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6.3.2 Controlling

 

the Device States  

The following pins are used to switch between the main device states:  





CHIP_EN

–

used to enable PMU  

VDDIO

–

I/O supply voltage from external supply  

In Power_Down state, VDDIO is on and CHIP_EN is low (at GND level). To switch between Power_Down state  

and MCU_Only state CHIP_EN has to change between low and high (VDDIO voltage level). Once the device is  

MCU_Only state, all other state transitions are controlled entirely by software. When VDDIO is off and CHIP_EN is  

low, the chip is powered off with no leakage.  

When no power is supplied to the device (the DC/DC Converter output and VDDIO are both off and at ground  

potential), a voltage cannot be applied to the ATBTLC1000 pins because each pin contains an ESD diode from the  

pin to supply. This diode will turn on when voltage higher than one diode-drop is supplied to the pin.  

If a voltage must be applied to the signal pads while the chip is in a low power state, the VDDIO supply must be  

on, so the Power_Down state must be used. Similarly, to prevent the pin-to-ground diode from turning on, do not  

apply a voltage that is more than one diode-drop below ground to any pin.  

6.3.3 Current

 

Consumption in Various Device States  

Table 6-3.  

ATBTLC1000 Device Current Consumption at VBAT = 3.6V  

I

VBAT (typical)  

(note 3)  

I

VDDIO (typical)  

Device state  

CHIP_EN  

VDDIO  

Remark  

(note 3)  

Power_Down  

Off  

On  

On  

On  

<50nA  

900nA  

<50nA  

50nA  

Ultra_Low_Power Standby  

Ultra_Low_Power with 8KB retention, BLE  

timer, no RTC

(1)  

On  

On  

On  

On  

1.1µA  

0.2µA  

0.1uA  

Ultra_Low_Power with 8KB retention, BLE  

timer, with RTC

(2)  

1.25µA  

.85mA  

MCU_Only, idle (waiting for interrupt)  

BLE_On_Receive@-95dBm  

On  

On  

On  

On  

0.2µA  

0.2µA  

4.2mA  

3.0mA  

4.0mA  

BLE_On_Transmit, 0dBm output power  

BLE_On_Transmit, 3.5dBm output power  

On  

On  

On  

On  

0.2µA  

0.2µA  

Notes: 1. Sleep

 

clock derived from internal 32kHz RC oscillator.  

2. Sleep

 

clock derived from external 32.768kHz crystal specified for CL = 7pF, using the default on-chip capacitance  

only, without using external capacitance.  

3. Expected

 

values for production silicon.  

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Figure 6-3.  

ATBTLC1000 Average Advertising Current  

Notes: 1.

 

The Average advertising current is measured at VBAT = 3.6V, TX POUT=0dBm.  

6.4  

Power Sequences  

The power sequences for ATBTLC1000 is shown in

The timing parameters are provided  

i

Figure 6-4.  

ATBTLC1000 Power Sequences  

VBATT  

t

A  

t

A’  

VDDIO  

t

B  

t

B’  

CHIP_EN  

t

C  

XO Clock  

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Table 6-4.  

ATBTLC1000 Sequence Timings  

Parameter Min. Max.  

Units  

Description  

Notes  

VBATT and VDDIO can rise simultaneously  

or can be tied together  

t

A  

t

B  

t

C  

0

0

VBATT rise to VDDIO rise  

ms  

CHIP_EN must not rise before VDDIO.  

CHIP_EN must be driven high or low, not left  

floating.  

VDDIO rise to CHIP_EN rise  

CHIP_EN rise to 31.25kHz  

(2MHz/64) oscillator stabilizing  

10  

0

µs  

CHIP_EN must fall before VDDIO. CHIP_EN  

must be driven high or low, not left floating.  

1

t

A  

CHIP_EN fall to VDDIO fall  

VDDIO fall to VBATT fall  

ms  

VBATT and VDDIO can fall simultaneously or  

be tied together  

1

t

B  

0

6.5  

Power on Reset and Brown out Detector  

The ATBTLC1000 has a Power on Reset (POR) circuit for proper system power bring up and a brown out detector  

to reset the system’s operation when a drop in battery voltage is detected.  



POR is a power on reset circuit that outputs a HI logic value when the VBATT_BUCK is below a voltage  

threshold. The POR output becomes a LO logic value when the VBATT_BUCK is above a voltage threshold.  



Brown out Detector (BOD) is a brown out detector that outputs a HI logic value when the bandgap reference  

(BGR) voltage falls below a programmable voltage threshold. When the bandgap voltage reference voltage  

level is restored above a voltage threshold, the BOD output becomes a LO logic value.  



The counter creates a pulse that holds the chip in reset for 256*(64*T_2MHz) ~ 8.2ms  

and

illustrate the system block diagram and timing.  

Figure 6-5.

 

ATBTLC1000 POR and BOD Block Diagram  

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Figure 6-6.  

ATBTLC1000 POR and BOD Timing Sequence  

Table 6-5.  

ATBTLC1000 BOD Thresholds  

Parameter  

Min.  

Typ.  

1.80V  

Max.  

Comment  

BOD threshold  

1.73V  

1.92V  

BOD threshold temperature coefficient  

BOD current consumption  

t

POR  

-1.09mV/C  

300nA  

8.2ms  

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7

Clocking  

7.1  

Overview  

Figure 7-1.  

ATBTLC1000 Clock Architecture  

26 MHz  

52 MHz  

26 MHz  

XO  

×2  

BLE Clock  

ARM Clock  

26 MHz  

26 MHz  

2 MHz  

ARM  

Clock  

Control  

26 MHz  

RC Osc  

2 MHz  

RC Osc  

2 MHz  

Low  

Power  

Clock  

31.25 kHz  

÷64  

Low Power  

Clock  

Control  

32.768 kHz  

32.768 kHz  

RTC XO  

provides an overview of the clock tree and clock management blocks.  

The BLE Clock is used to drive the BLE subsystem. The ARM clock is used to drive the Cortex-M0 MCU and its  

interfaces (UART, SPI, and I

2

C), the nominal MCU clock speed is 26MHz. The Low Power Clock is used to drive  

all the low power applications like BLE sleep timer, always-on power sequencer, always-on timer, and others.  

The 26MHz Crystal Oscillator (XO) must be used for the BLE operations or in the event a very accurate clock is  

required for the ARM subsystem operations.  

The 26MHz integrated RC Oscillator is used for most general purpose operations on the MCU and its peripherals.  

In cases when the BLE subsystem is not used, the RC oscillator can be used for lower power consumption. The  

frequency variation of this RC oscillator is up to ±50% over process, voltage, and temperature.  

The 2MHz integrated RC Oscillator can be used as the Low Power Clock for applications that require fast wakeup  

of the ARM or for generating a ~31.25kHz clock for slower wakeup but lowest power in sleep mode. This 2MHz  

oscillator can also be used as the ARM Clock for low-power applications where the MCU needs to remain on but  

run at a reduced clock speed. The frequency variation of this RC oscillator is up to ±50% over process, voltage,  

and temperature.  

The 32.768kHz RTC Crystal Oscillator (RTC XO) is recommended to be used for BLE operations (although  

optional) as it will reduce power consumption by providing the best timing for wakeup precision, allowing circuits to  

be in low power sleep mode for as long as possible until they need to wake up and connect during the BLE  

connection event. The ~31.25kHz clock derived from the 2MHz integrated RC Oscillator can be used instead of  

RTC XO but it has low accuracy over process, voltage and temperature variations (up to ±50%) and thus needs to  

be frequently calibrated to within ±500ppm if the RC oscillator is used for BLE timing during a connection event.  

Because this clock is less accurate than RTC XO, it will require waking up earlier to prepare for a connection event  

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and this will increase the average power consumption. Calibration of the RC Oscillator is described in the  

application note.  

7.2  

26MHz Crystal Oscillator (XO)  

Table 7-1.  

ATBTLC1000 26MHz Crystal Oscillator Parameters  

Parameter  

Min.  

Typ.  

26  

Max.  

N/A  

150  

50  

Units  

MHz  

Ω

Crystal Resonant Frequency  

Crystal Equivalent Series Resistance  

Stability – Initial Offset

(1)  

N/A  

50  

-50  

-40  

ppm  

Stability – Temperature and Aging  

40  

Note:  

1. Initial

 

offset must be calibrated to maintain ±25ppm in all operating conditions. This calibration is performed during  

final production testing and calibration offset values are stored in eFuse. More details are provided in the  

calibration application note.  

The block diagram i

(a) shows how the internal Crystal Oscillator (XO) is connected to the external  

crystal.  

The XO has up to 10pF internal capacitance on each terminal XO_P and XO_N (programmable in steps of  

1.25pF). To bypass the crystal oscillator, an external Signal capable of driving 10pF can be applied to the XO_P  

terminal as shown i

(b).  

The needed external bypass capacitors depend on the chosen crystal characteristics. Refer to the datasheet of the  

preferred crystal and take into account the on chip capacitance.  

When bypassing XO_P from an external clock, XO_N is required to be floating.  

It is recommended that only crystals specified for CL=8pF be used in customer designs since this affects the  

sleep/wake up timing of the device. CL other than 8pF may require upgraded firmware and device re-  

characterization.  

Figure 7-2.  

ATBTLC1000 Connections to XO  

(a) Crystal oscillator is used  

(b) Crystal oscillator is bypassed  

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Table 7-2.  

ATBTLC1000 26MHz XTAL C_onchip Programming  

Register  

Cl_onchip  

1.00  

[pF]  

rx_xo_regs[7,6,15] = 000  

rx_xo_regs[7,6,15] = 001  

rx_xo_regs[7,6,15] = 010  

rx_xo_regs[7,6,15] = 011  

rx_xo_regs[7,6,15] = 100  

rx_xo_regs[7,6,15] = 101  

rx_xo_regs[7,6,15] = 110  

rx_xo_regs[7,6,15] = 111  

2.25  

3.50  

4.75  

6.00  

7.25  

8.50  

9.75  

If rx_reg7[1] = 1 add 5pF to above value  

specifies the electrical and performance requirements for the external clock.  

Table 7-3.

 

ATBTLC1000 XO Bypass Clock Specification  

Parameter  

Min.  

26  

Max.  

26  

Unit  

MHz  

V

pp  

Comments  

Oscillation frequency  

Voltage swing  

Must be able to drive 5pF load @ desired frequency  

0.75  

-25  

1.2  

Stability

–

Temperature and Aging  

Phase Noise  

+25  

ppm  

-130  

<1psec  

dBc/Hz At

 

10kHz offset  

Jitter (RMS)  

Based on integrated phase noise spectrum from  

1kHz to 1MHz  

7.3  

32.768kHz RTC Crystal Oscillator (RTC XO)  

7.3.1 General

 

Information  

ATBTLC1000 has a 32.768kHz RTC oscillator that is preferably used for BLE activities involving connection  

events. To be compliant with the BLE specifications for connection events, the frequency accuracy of this clock  

has to be within ±500ppm. Because of the high accuracy of the 32.768kHz crystal oscillator clock, the power  

consumption can be minimized by leaving radio circuits in low-power sleep mode for as long as possible until they  

need to wake up for the next connection timed event.  

The block diagram i

a) shows how the internal low frequency Crystal Oscillator (XO) is connected to  

the external crystal.  

The RTC XO has a programmable internal capacitance with a maximum of 15pF on each terminal, RTC_CLK_P  

and RTC_CLK_N. When bypassing the crystal oscillator with an external signal, one can program down the  

internal capacitance to its minimum value (~1pF) for easier driving capability. The driving signal can be applied to  

the RTC_CLK_P terminal as shown i

(b).  

The need for external bypass capacitors depends on the chosen crystal characteristics. Refer to the datasheet of  

the preferred crystal and take into account the on-chip capacitance.  

When bypassing RTC_CLK_P from an external clock, RTC_CLK_N is required to be floating.  

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Figure 7-3.  

ATBTLC1000 Connections to RTC XO  

(a) Crystal oscillator is used  

Table 7-4.

 

32.768kHz XTAL C_onchip Programming  

Register: pierce_cap_ctrl[3:0]  

(b) Crystal oscillator is bypassed  

Cl_onchip  

0.0  

[pF]  

0000  

0001  

0010  

0011  

0100  

0101  

0110  

0111  

1000  

1001  

1010  

1011  

1100  

1101  

1110  

1111  

1.0  

2.0  

3.0  

4.0  

5.0  

6.0  

7.0  

8.0  

9.0  

10.0  

11.0  

12.0  

13.0  

14.0  

15.0  

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7.3.2 RTC

 

XO Design and Interface Specification  

The RTC consists of two main blocks: The Programmable Gm stage and tuning capacitors. The programmable  

Gm stage is used to maintain a phase shift of 360°C with the motional arm and keep total negative resistance to  

sustain oscillation. Tuning capacitors are used to adjust the XO center frequency and control the XO precision for  

different crystal models. The output of the XO is driven to the digital domain via a digital buffer stage with supply  

voltage of 1.2V.  

Table 7-5.  

RTC XO Interface  

Pin name  

Function  

Register default  

Digital Control Pins  

Control feedback resistance value:  

Pierce_res_ctrl  

0 = 20M

Ω

Feedback resistance  

1 = 30M

Ω

Feedback resistance  

0X4000F404<15>=’1’  

Control the internal tuning capacitors with step of 700fF:  

0000=700fF  

Pierce_cap_ctrl<3:0>  

0X4000F404<23:20>

=”1000”  

1111=11.2pF  

Refer to crystal datasheet to check for optimum tuning cap  

value  

Controls the Gm stage gain for different crystal mode:  

0011= for crystal with shunt cap of 1.2pF  

1000= for crystal with shunt cap >3pF  

Pierce_gm_ctrl<3:0>  

VDD_XO  

0X4000F404<19:16>=”1000”  

Supply Pins  

1.2V  

7.3.3 RTC

 

Characterization with Gm Code Variation at Supply 1.2V and Temp. = 25°C  

This section shows the RTC total drawn current and the XO accuracy versus different tuning capacitors and  

different GM codes, at supply voltage of 1.2V and temp. = 25°C.  

Figure 7-4.  

RTC Drawn Current vs. Tuning Caps at 25°C  

600  

500  

400  

300  

200  

100  

0

gm code=1  

gm code=2  

gm code=4  

gm code=8  

gm code=12  

gm code=16  

0

5

10  

15  

20  

Tuning Caps in pF  

20  

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Figure 7-5.  

RTC Oscillation Frequency Deviation vs. Tuning Caps at 25°C  

450  

400  

350  

300  

250  

200  

150  

100  

50  

gm code=1  

gm code=2  

gm code=4  

gm code=8  

gm code=12  

gm code=16  

0

0

2

4

6

8

10  

12  

14  

16  

18  

Tuning Caps  

7.3.4 RTC

 

Characterization with Supply Variation and Temp. = 25°C  

Figure 7-6.  

1400  

RTC Drawn Current vs. Supply Variation  

1200  

1000  

800  

600  

400  

200  

0

gm code=0 &  

Tuning Cap=8pF  

gm code=0 &  

Tuning Cap=0pF  

gm code=16 &  

Tuning Cap=16pF  

gm code=16 &  

Tuning Cap =0pF  

0.9  

1

1.1  

1.2  

1.3  

1.4  

1.5  

Supply voltage  

21  

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Figure 7-7.  

400  

RTC Frequency Deviation vs. Supply Voltage  

350  

300  

250  

200  

150  

100  

50  

gm code=0 & Tuning  

Cap=8pF  

gm code=0 & Tuning  

Cap=0pF  

gm code=16 & Tuning  

Cap=16pF  

gm code=16 & Tuning Cap=0  

0

0.9  

1

1.1  

1.2  

1.3  

1.4  

1.5  

Supply Voltage  

7.4  

2MHz and 26MHz Integrated RC Oscillators  

The 2MHz integrated RC Oscillator circuit without calibration has a frequency variation of 50% over process,  

temperature, and voltage variation. The ~31.25kHz clock is derived from the 2MHz clock by dividing by 64 and  

provides for lowest sleep power mode with a real-time clock running. As described above, calibration over process,  

temperature, and voltage are required to maintain the accuracy of this clock.  

Figure 7-8.  

32kHz RC Oscillator PPM Variation vs. Calibration Time at Room Temperature  

22  

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Figure 7-9.  

32kHz RC Oscillator Frequency Variation over Temperature  

The 26MHz integrated RC Oscillator circuit has a frequency variation of 50% over process, temperature, and  

voltage variation.  

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8

CPU and Memory Subsystem  

8.1  

ARM Subsystem  

ATBTLC1000 has an ARM Cortex-M0 32-bit processor. It is responsible for controlling the BLE Subsystem and  

handling all application features.  

The Cortex-M0 Microcontroller consists of a full 32-bit processor capable of addressing 4GB of memory. It has a  

RISC-like load/store instruction set and internal 3-stage Pipeline Von Neumann architecture.  

The Cortex-M0 processor provides a single system-level interface using AMBA technology to provide high speed,  

low latency memory accesses.  

The Cortex-M0 processor implements a complete hardware debug solution, with four hardware breakpoint and two  

watch point options. This provides high system visibility of the processor, memory, and peripherals through a 2-pin  

Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices.  

Figure 8-1.  

ATBTLC1000 ARM Cortex-M0 Subsystem  

BLE  

Retention  

Ahb_to_sram  

PD1  

ROM  

Ahb_to_rom  

Ahb_to_sram  

Ahb_to_sram  

Timer  

IDRAM1  

IDRAM2  

DualTimer  

AHB  

Slave  

AHB  

GPIO Ctrl x3  

System Level AHB Slave  

System Regs  

Watch Dog  

Timer x2  

Master  

SPI x2  

I2C x2  

Security Cores  

DMA Controller  

UART x2  

System Level  

AHB Master  

Nested Vector  

IRQ Ctrl  

SPI Flash Ctrl  

Control Registers  

EFUSE Registers  

LP Clock Calibration  

AON Sleep Timer  

LP  

CORTEX  

M0  

AON Power  

Sequencer  

8.1.1 Features  

The processor features and benefits are:  









Tight integration with the system peripherals to reduce area and development costs  

Thumb instruction set combines high code density with 32-bit performance  

Integrated sleep modes using a Wakeup Interrupt Controller for low power consumption  

Deterministic, high-performance interrupt handling via Nested Vector Interrupt Controller for time-critical  

applications  





Serial Wire Debug reduces the number of pins required for debugging  

DMA engine for Peripheral-to-Memory, Memory-to-Memory, and Memory-to-Peripheral operation  

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8.1.2 Module

 

Descriptions  

8.1.2.1

Timer  

The 32-bit timer block allows the CPU to generate a time tick at a programmed interval. This feature can be used  

for a wide variety of functions such as counting, interrupt generation, and time tracking.  

8.1.2.2

Dual Timer  

The APB dual-input timer module is an APB slave module consisting of two programmable 32-bit down-counters  

that can generate interrupts when they expire. The timer can be used in a Free-running, Periodic, or One-shot  

mode.  

8.1.2.3

Watchdog  

The two watchdog blocks allow the CPU to be interrupted if it has not interacted with the watchdog timer before it  

expires. In addition, this interrupt will be an output of the core so that it can be used to reset the CPU in the event  

that a direct interrupt to the CPU is not useful. This will allow the CPU to get back to a known state in the event a  

program is no longer executing as expected. The watchdog module applies a reset to a system in the event of a  

software failure, providing a way to recover from software crashes.  

8.1.2.4

Wake-up Timer  

This timer is a 32-bit count-down timer that operates on the 32kHz sleep clock. It can be used as a general  

purpose timer for the ARM or as a wakeup source for the chip. It has the ability to be a onetime programmable  

timer, as it will generate an interrupt/wakeup on expiration and stop operation. It also has the ability to be  

programmed in an auto reload fashion where it will generate an interrupt/wakeup and then proceed to start another  

count down sequence.  

8.1.2.5

SPI Controller  

See Section

8.1.2.6

I

2

C Controller  

See Section

8.1.2.7

SPI-Flash Controller  

The AHB SPI-Flash Controller is used to access an external SPI Flash device to access various instruction/data  

code needed for storing application code, code patches, and OTA images. Supports several SPI modes including  

0, 1, 2, and 3. See Section

8.1.2.8

UART  

See Section

8.1.2.9

DMA Controller  

Direct Memory Access (DMA) allows certain hardware subsystems to access main system memory independently  

of the Cortex-M0 Processor.  

The DMA features and benefits are:  









Supports any address alignment  

Supports any buffer size alignment  

Peripheral flow control, including peripheral block transfer  

The following modes are supported:  

–

–

–

–

Peripheral to peripheral transfer  

Memory to memory  

Memory to peripheral  

Peripheral to memory  

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–

Register to memory  



















Interrupts for both TX done and RX done in memory and peripheral mode  

Scheduled transfers  

Endianness byte swapping  

Watchdog timer  

4-channel operation  

32-bit data width  

AHB MUX (on read and write buses)  

Command lists support  

Usage of tokens  

8.1.2.10

Nested Vector Interrupt Controller (NVIC)  

External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software can set the priority  

of each interrupt. The NVIC and the Cortex-M0 processor core are closely coupled, providing low latency interrupt  

processing and efficient processing of late arriving interrupts.  

All NVIC registers are accessible via word transfers and are little-endian. Any attempt to read or write a half-word  

or byte individually is unpredictable.  

The NVIC allows for the CPU to be able to individually enable, disable each interrupt source, and hold each  

interrupt until it has been serviced and cleared by the CPU.  

Table 8-1.  

NVIC Register Summary  

Name  

Description  

ISER  

Interrupt Set-Enable Register  

ICER  

Interrupt Clear-Enable Register  

Interrupt Set-Pending Register  

Interrupt Clear-Pending Register  

Interrupt Priority Registers  

ISPR  

ICPR  

IPR0-IPR7  

For a description of each register, see the Cortex-M0 documentation from ARM.  

8.1.2.11

GPIO Controller  

The AHB GPIO is a general-purpose I/O interface unit allowing the CPU to independently control all input or output  

signals on ATBTLC1000. These can be used for a wide variety of functions pertaining to the application.  

The AHB GPIO provides a 16-bit I/O interface with the following features:  









Programmable interrupt generation capability  

Programmable masking support  

Thread safe operation by providing separate set and clear addresses for control registers  

Inputs are sampled using a double flip-flop to avoid meta-stability issues  

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8.2  

Memory Subsystem  

The M0 core uses a 128kB instruction/boot ROM along with a 128kB shared instruction and data RAM.  

8.2.1 BLE

 

Retention Memory  

The BLE functionality requires 8KB (or more depending on the application) state, instruction, and data to be  

retained in memory when the processor either goes into Sleep Mode or Power Off Mode. The RAM is separated  

into specific power domains to allow tradeoff in power consumption with retention memory size.  

8.3  

Non-volatile Memory  

ATBTLC1000 has 768 bits of non-volatile eFuse memory that can be read by the CPU after device reset. This non-  

volatile one-time-programmable memory can be used to store customer-specific parameters, such as BLE  

address, XO calibration information, TX power, crystal frequency offset, as well as other software-specific  

configuration parameters. The eFuse is partitioned into six 128-bit banks. The bit map of the first bank is shown in  

he purpose of the first 80 bits in bank 0 is fixed, and the remaining bits are general-purpose software  

dependent bits, or reserved for future use. Since each bank and each bit can be programmed independently, this  

allows for several updates of the device parameters following the initial programming, e.g. updating BLE address  

(this can be done by invalidating the last programmed bank and programming a new bank). Refer to the  

ATBTLC1000 Programming Guide for the eFuse programming instructions.  

Figure 8-2.  

ATBTLC1000 eFuse Bit Map  

128 Bits  

Bank 0  

Bank 1  

Bank 2  

Bank 3  

Bank 4  

Application  

Specific  

Configuration  

Bank 5  

F

BT ADDR  

48  

8

XO  

1

1

3

3

Calibration  

Tx Power  

Calibration  

HW Config  

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9

Bluetooth Low Energy (BLE) Subsystem  

The BLE subsystem implements all the critical real-time functions required for full compliance with Specification of  

the Bluetooth System, v4.1, Bluetooth SIG.  

It consists of a Bluetooth 4.1 baseband controller (core), radio transceiver and the Atmel Bluetooth Smart Stack,  

the BLE Software Platform.  

9.1  

BLE Core  

The baseband controller consists of modem and Medium Access Controller (MAC) and it encodes and decodes  

HCI packets, constructs baseband data packages, schedules frames, and manages and monitors connection  

status, slot usage, data flow, routing, segmentation, and buffer control.  

The core performs Link Control Layer management supporting the main BLE states, including advertising and  

connection.  

9.1.1 Features  















Broadcaster, Central, Observer, Peripheral  

Simultaneous Master and Slave operation, connect up to eight slaves  

Frequency Hopping  

Advertising/Data/Control packet types  

Encryption (AES-128, SHA-256)  

Bit stream processing (CRC, whitening)  

Operating clock 52MHz  

9.2  

BLE Radio  

The radio consists of a fully integrated transceiver, including Low Noise Amplifier, Receive (RX) down converter,  

and analog baseband processing as well as Phase Locked Loop (PLL), Transmit (TX) Power Amplifier, and  

Transmit/Receive switch. At the RF front end, no external RF components on the PCB are required other than the  

antenna and a matching component.  

The RX sensitivity and TX output power of the radio together with the 4.1 PHY core provide a 100dB RF link  

budget for superior range and link reliability.  

9.2.1 Receiver

 

Performance  

Table 9-1.

 

ATBTLC1000 BLE Receiver Performance  

Parameter  

Min.  

Typ.  

Max.  

Unit  

Frequency  

2,402  

2,480  

MHz  

Sensitivity with external 1.2V  

Sensitivity with on-chip DC/DC  

Maximum receive signal level  

CCI  

-96  

-95  

+5  

dBm  

12.5  

0

ACI (N±1)  

N+2 Blocker (Image)  

N-2 Blocker  

-22  

-38  

-35  

-43  

dB  

N+3 Blocker (Adj. Image)  

N-3 Blocker  

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Parameter  

Min.  

Typ.  

-45  

Max.  

Unit  

N±4 or greater  

dB  

Intermod (N+3, N+6)  

-32  

OOB (2GHz<f<2.399GHz)  

OOB (f<2GHz) or (f>2.4GHz)  

RX peak current draw  

-15  

-10  

dBm  

mA  

4.0

(1)  

Note:  

1. At

 

-93dBm sensitivity setting. Add 0.2mA at 3.6V for best sensitivity setting.  

All measurements performed at 3.6V VBATT and 25°C, with tests following Bluetooth V4.1 standard tests.  

There are two gain settings for Sensitivity; high gain (-95dBm) and low gain (-93dBm). Low gain has lower current  

consumption.  

9.2.2 Transmitter

 

Performance  

The transmitter has fine step power control with P

out

variable in <3dB steps below 0dBm and in <0.5dB steps  

above 0dBm.  

Table 9-2.  

ATBTLC1000 BLE Transmitter Performance  

Parameter Min.  

Typ.  

Max.  

2,480  

3.5  

Unit  

Frequency  

2,402  

-20  

MHz  

Output power range  

Maximum output power  

In-band Spurious (N±2)  

In-band Spurious (N±3)  

2

nd

harmonic P

out  

0

3.5  

-45  

-55  

dBm  

-41  

-41  

-41  

-41  

3

rd

harmonic P

out  

4

th

harmonic P

out  

5

th

harmonic P

out  

Frequency deviation  

TX peak current draw  

±250  

kHz  

mA  

3.0

(1)  

Note:  

1. At

 

0dBm TX output power.  

All measurements performed at 3.6V VBATT and 25°C, with tests following Bluetooth V4.1 standard tests.  

9.3  

Atmel Bluetooth SmartConnect Stack  

The ATBTLC1000 has a completely integrated Bluetooth Low Energy stack on chip, fully qualified, mature, and  

Bluetooth V4.1 compliant.  

Customer applications interface with the BLE protocol stack through the Atmel BLE API which supports direct  

access to the GAP, SMP, ATT, GATT client / server, and L2CAP service layer protocols in the embedded  

firmware.  

The stack includes numerous BLE profiles for applications like:  





Smart Energy  

Consumer Wellness  

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











Home Automation  

Security  

Proximity Detection  

Entertainment  

Sports and Fitness  

Automotive  

Together with the Atmel Studio Software Development environment, additional customer profiles can be easily  

developed.  

The Atmel Bluetooth SmartConnect software development kit is based on Keil and IAR

™

compiler tools and  

contains numerous application code examples for embedded and hosted modes.  

In addition to the protocol stack, drivers for each peripheral hardware block are provided.  

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10 External

 

Interfaces  

10.1 Overview  

ATBTLC1000 external interfaces include: 2xSPI Master/Slave (SPI0 and SPI1), 2xI

2

C Master/Slave (I

2

C0 and  

I

2

C1), 1xI

2

C Slave-only (I

2

C2), 2xUART (UART1 and UART2), 1xSPI Flash, 1xSWD, and General Purpose  

Input/Output (GPIO) pins. For specific programming instructions, refer to the ATBTLC1000 Programming Guide.  

illustrates the different peripheral functions that are software selectable for each pin. This allows for  

maximum flexibility of mapping desired interfaces on GPIO pins. MUX1 option allows for any MEGAMUX option  

from

to be assigned to a GPIO.  

Table 10-1.  

ATBTLC1000 Pin-MUX Matrix of External Interfaces  

Pin Name  

LP_GPIO_0  

LP_GPIO_1  

LP_GPIO_2  

LP_GPIO_3  

LP_GPIO_8  

LP_GPIO_9  

Pin# Pull  

MUX0  

MUX1  

MUX2  

SWD CLK  

MUX3  

MUX4  

MUX5  

MUX6  

MUX7  

TEST OUT 0  

TEST OUT 1  

D5 Up

 

GPIO 0  

MEGAMUX 0  

MEGAMUX 1  

MEGAMUX 2  

MEGAMUX 3  

MEGAMUX 8  

MEGAMUX 9  

MEGAMUX 10  

MEGAMUX 11  

MEGAMUX 12  

MEGAMUX 13  

WAKEUP  

F7  

G6  

H7  

J6  

Up GPIO

 

1  

Up GPIO

 

2  

Up GPIO

 

3  

Up GPIO

 

8  

Up GPIO

 

9  

Up GPIO

 

10  

Up GPIO

 

11  

Up GPIO

 

12  

Up GPIO

 

13  

Up GPIO

 

31  

Up GPIO

 

47  

SWD I/O  

UART1 RXD  

UART1 TXD  

I

2

C0 SDA  

SPI1 SCK  

SPI1 MOSI  

SPI0 SCK  

SPI FLASH SCK

 

TEST OUT 2  

SPI FLASH TXD

 

TEST OUT 3  

SPI FLASH SSN

 

TEST OUT 8  

SPI FLASH RXD

 

TEST OUT 9  

SPI FLASH SCK

 

TEST OUT 10  

SPI FLASH TXD

 

TEST OUT 11  

SPI FLASH SSN

 

TEST OUT 12  

SPI FLASH RXD

 

TEST OUT 13  

SPI0 MOSI  

SPI0 SSN  

SPI0 MISO  

I

2

C2 SDA  

H5  

I

2

C0 SCL  

I

2

C2 SCL  

LP_GPIO_10 J4  

LP_GPIO_11 F5  

LP_GPIO_12 G4  

LP_GPIO_13 D3  

SPI0 SCK  

SPI0 MOSI  

SPI0 SSN  

SPI0 MISO  

RTC CLK IN  

AO_GPIO_0  

GPIO_MS1  

B1  

F3  

32KHZ CLK OUT  

shows the various software selectable MEGAMUX options that correspond to specific peripheral  

functionality. Several MEGAMUX options provide an interface to manage Wi-Fi

®

– BLE coexistence.  

Table 10-2.  

ATBTLC1000 Software Selectable MEGAMUX Options  

MUX_Sel  

Function  

UART1 RXD  

UART1 TXD  

UART1 CTS  

UART1 RTS  

UART2 RXD  

UART2 TXD  

UART2 CTS  

UART2 RTS  

I

2

C0 SDA  

Notes  

0

1

2

3

4

5

6

7

8

9

I

2

C0 SCL  

10  

11  

I

2

C1 SDA  

I

2

C1 SCL  

31  

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MUX_Sel  

12  

Function  

Notes  

PWM 1  

13  

PWM 2  

14  

PWM 3  

15  

PWM 4  

16  

LP CLOCK OUT  

32kHz clock output (RC Osc. or RTC XO)  

Coexistence: Wi-Fi is currently transmitting  

Coexistence: Wi-Fi is currently receiving  

Coexistence: BLE is currently transmitting  

Coexistence: BLE is currently receiving  

Coexistence Signal  

17  

WLAN TX ACTIVE  

WLAN RX ACTIVE  

BLE TX ACTIVE  

BLE RX ACTIVE  

BLE IN PROCESS  

BLE MBSY  

18  

19  

20  

21  

22  

Coexistence Signal  

23  

BLE SYNC  

Coexistence Signal  

24  

BLE RXNTX  

Coexistence Signal  

25  

BLE PTI 0  

Coexistence: BLE Priority  

26  

BLE PTI 1  

Coexistence: BLE Priority  

27  

BLE PTI 2  

Coexistence: BLE Priority  

28  

BLE PTI 3  

Coexistence: BLE Priority  

29  

QUAD DEC X IN A  

QUAD DEC X IN B  

QUAD DEC Y IN A  

QUAD DEC Y IN B  

QUAD DEC Z IN A  

QUAD DEC Z IN B  

30  

31  

32  

33  

34  

An example of peripheral assignment using these MEGAMUX options is as follows:  







I

2

C0 pin-muxed on LP_GPIO_10 and LP_GPIO_11 via MUX1 and MEGAMUX=8 and 9  

I

2

C1 pin-muxed on LP_GPIO_0 and LP_GPIO_1 via MUX1 and MEGAMUX=10 and 11  

PWM pin-muxed on LP_GPIO_12 via MUX1 and MEGAMUX=12  

Another example is to illustrate the available options for pin LP_GPIO_3, depending on the pin-MUX option  

selected:  







MUX0: the pin will function as bit 3 of the GPIO bus and is controlled by the GPIO controller in the ARM  

subsystem  

MUX1: any option from the MEGAMUX table can be selected, for example it can be a quad_dec, pwm, or  

any of the other functions listed in the MEGAMUX table  

MUX2: the pin will function as UART1 TXD; this can be also achieved with the MUX1 option via MEGAMUX,  

but the MUX2 option allows a shortcut for the recommended pinout  





MUX3: this option is not used and thus defaults to the GPIO option (same as MUX0)  

MUX4: the pin will function as SPI1 MOSI (this option is not available through MEGAMUX)  

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





MUX5: the pin will function as SPI0 MOSI (this option is not available through MEGAMUX)  

MUX6: the pin will function as SPI FLASH SCK (this option is not available through MEGAMUX)  

MUX7: the pin will function as bit 3 of the test output bus, giving access to various debug signals  

10.2 I

2

C Master/Slave Interface  

10.2.1 Description  

ATBTLC1000 provides I

2

C Interface that can be configured as Slave or Master. I

2

C Interface is a two-wire serial  

interface consisting of a serial data line (SDA) and a serial clock line (SCL). ATBTLC1000 I

2

C supports I

2

C bus  

Version 2.1 – 2000 and can operate in the following speed modes:  







Standard mode (100kb/s)  

Fast mode (400kb/s)  

High-speed mode (3.4Mb/s)  

The I

2

C is a synchronous serial interface. The SDA line is a bidirectional signal and changes only while the SCL  

line is low, except for STOP, START, and RESTART conditions. The output drivers are open-drain to perform wire-  

AND functions on the bus. The maximum number of devices on the bus is limited by only the maximum  

capacitance specification of 400pF. Data is transmitted in byte packages.  

For specific information, refer to the

Philips Specification entitled “

The I

2

C -Bus Specification, Ver2.1

”

.  

10.2.2 I

2

C Interface Timing  

The I

2

C Interface timing (common to Slave and Master) is provided i

The timing parameters for Slave  

and Master modes are specified in

and

respectively.  

Figure 10-1.

 

ATBTLC1000 I

2

C Slave Timing Diagram  

t

PR  

t

HDDAT  

t

SUDAT  

t

BUF  

t

SUSTO  

SDA  

SCL  

t

HL  

t

LH  

t

LH  

t

HL  

t

WL  

t

HDSTA  

t

WH  

t

PR  

t

PR  

f

SCL  

t

SUSTA  

Table 10-3.  

ATBTLC1000 I

2

C Slave Timing Parameters  

Parameter Symbol

 

Min. Max. Units  

Remarks  

SCL Clock Frequency  

SCL Low Pulse Width  

SCL High Pulse Width  

SCL, SDA Fall Time  

f

SCL  

t

WL  

t

WH  

t

HL  

0

400  

kHz  

1.3  

0.6  

µs  

300  

ns  

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Parameter  

SCL, SDA Rise Time  

Symbol Min. Max. Units  

Remarks  

This is dictated by external compo-  

nents  

t

LH  

300  

START Setup Time  

START Hold Time  

SDA Setup Time  

t

SUSTA  

t

HDSTA  

t

SUDAT  

0.6  

0.6  

100  

0

µs  

ns  

Slave and Master Default  

SDA Hold Time  

t

HDDAT  

40  

0.6  

1.3  

0

Master Programming Option  

STOP Setup time  

t

SUSTO  

t

BUF  

µs  

ns  

Bus Free Time Between STOP and START  

Glitch Pulse Reject  

t

PR  

50  

Table 10-4.  

ATBTLC1000 I

2

C Master Timing Parameters  

Standard  

Mode  

High-speed  

Fast Mode  

Mode  

Parameter  

Symbol  

Units  

Min.  

Max.  

Min.  

Max.  

Min.  

0

Max.  

SCL Clock Frequency  

SCL Low Pulse Width  

SCL High Pulse Width  

SCL Fall Time  

f

SCL  

t

WL  

0

4.7  

4

100  

0

400  

3400  

kHz  

µs  

1.3  

0.6  

0.16  

0.06  

10  

t

WH  

t

HLSCL  

t

HLSDA  

t

LHSCL  

t

LHSDA  

t

SUSTA  

t

HDSTA  

t

SUDAT  

t

HDDAT  

t

SUSTO  

t

BUF  

300  

300  

300  

300  

300  

300  

40  

80  

40  

80  

SDA Fall Time  

10  

ns  

SCL Rise Time  

1000  

1000  

10  

SDA Rise Time  

10  

START Setup Time  

START Hold Time  

SDA Setup Time  

4.7  

4

0.6  

0.6  

100  

40  

0.16  

0.16  

10  

µs  

ns  

250  

5

SDA Hold Time  

0

70  

STOP Setup time  

4

0.6  

1.3  

0

0.16  

µs  

ns  

Bus Free Time Between STOP and START  

Glitch Pulse Reject  

4.7  

t

PR  

50  

10.3 SPI

 

Master/Slave Interface  

10.3.1 Description  

ATBTLC1000 provides a Serial Peripheral Interface (SPI) that can be configured as Master or Slave. The SPI  

Interface pins are mapped as shown i

he SPI Interface is a full-duplex slave-synchronous serial  

interface. When the SPI is not selected, i.e., when SSN is high, the SPI interface will not interfere with data  

transfers between the serial-master and other serial-slave devices. When the serial slave is not selected, its  

transmitted data output is buffered, resulting in a high impedance drive onto the serial master receive line. The SPI  

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Slave interface responds to a protocol that allows an external host to read or write any register in the chip as well  

as initiate DMA transfers. For the details of the SPI protocol and more specific instructions, refer to the  

ATBTLC1000 Programming Guide.  

Table 10-5.  

ATBTLC1000 SPI Interface Pin Mapping  

Pin Name  

SPI Function  

SSN  

Active Low Slave Select  

Serial Clock  

SCK  

MOSI  

MISO  

Master Out Slave In (Data)  

Master In Slave Out (Data)  

10.3.2 SPI

 

Interface Modes  

The SPI Interface supports four standard modes as determined by the Clock Polarity (CPOL) and Clock Phase  

(CPHA) settings. These modes are illustrated i

and

The red lines i

correspond to Clock Phase = 0 and the blue lines correspond to Clock Phase = 1.  

Table 10-6.  

ATBTLC1000 SPI Modes  

Mode  

CPOL  

CPHA  

0

1

2

3

0

0

1

1

0

1

0

1

Figure 10-2.

 

ATBTLC1000 SPI Clock Polarity and Clock Phase Timing  

CPOL = 0  

SCK  

CPOL = 1  

SSN  

CPHA = 0  

CPHA = 1  

z

1

2

3

4

5

6

7

8

z

RXD/TXD  

(MOSI/MISO)  

z

1

2

3

4

5

6

7

8

z

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10.3.3 SPI

 

Slave Timing  

The SPI Slave timing is provided i

an

Figure 10-3.

 

ATBTLC1000 SPI Slave Timing Diagram  

Table 10-7.  

ATBTLC1000 SPI Slave Timing Parameters  

Parameter  

Symbol  

f

SCK  

Min.  

Max.  

Units  

Clock Input Frequency  

Clock Low Pulse Width  

Clock High Pulse Width  

Clock Rise Time  

2

MHz  

t

WL  

240  

240  

t

WH  

ns  

t

LH  

10  

10  

Clock Fall Time  

t

HL  

Input Setup Time  

t

ISU  

5

5

0

5

5

Input Hold Time  

t

IHD  

ns  

Output Delay  

t

ODLY  

t

SUSSN  

t

HDSSN  

20  

Slave Select Setup Time  

Slave Select Hold Time  

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10.3.4 SPI

 

Master Timing  

The SPI Master Timing is provided in

and

Figure 10-4.

 

ATBTLC1000 SPI Master Timing Diagram  

f

SCK  

t

LH  

t

WH  

t

WL  

SCK  

t

HL  

SSN,  

TXD  

t

ODLY  

t

ISU  

t

IHD  

RXD  

Table 10-8.  

ATBTLC1000 SPI Master Timing Parameters  

Parameter  

Symbol  

f

SCK  

t

WL  

Min.  

Max.  

Units  

Clock Output Frequency  

Clock Low Pulse Width  

Clock High Pulse Width  

Clock Rise Time  

4

MHz  

120  

120  

t

WH  

t

LH  

5

5

Clock Fall Time  

t

HL  

ns  

Input Setup Time  

Input Hold Time  

t

ISU  

5

5

0

t

IHD  

Output Delay  

t

ODLY  

5

10.4 SPI

 

Flash Master Interface  

10.4.1 Description  

ATBTLC1000 provides an SPI Master interface for accessing external Flash memory. The TXD pin is the same as  

the Master Output, Slave Input (MOSI), and the RXD pin is the same as the Master Input, Slave Output (MISO).  

The SPI Master interface supports all four standard modes of clock polarity and clock phase shown i

External SPI Flash memory is accessed by a processor programming commands to the SPI Master interface,  

which in turn initiates an SPI master access to the Flash. For more specific instructions. Refer to ATBTLC1000  

Programming Guide.  

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10.4.2 SPI

 

Master Timing  

The SPI Master Timing is provided in

and

Figure 10-5.

 

ATBTLC1000 SPI Master Timing Diagram  

f

SCK  

t

LH  

t

WH  

t

WL  

SCK  

t

HL  

SSN,  

TXD  

t

ODLY  

t

ISU  

t

IHD  

RXD  

Table 10-9.  

ATBTLC1000 SPI Master Timing Parameters  

Parameter  

Symbol  

f

SCK  

t

WL  

t

WH  

t

LH  

Min.  

Max.  

Units  

Clock Output Frequency  

Clock Low Pulse Width  

Clock High Pulse Width  

Clock Rise Time  

13  

MHz  

33  

33  

5

5

Clock Fall Time  

t

HL  

ns  

Input Setup Time  

Input Hold Time  

t

ISU  

t

IHD  

t

ODLY  

5

5

0

Output Delay  

5

10.5 UART

 

Interface  

ATBTLC1000 provides Universal Asynchronous Receiver/Transmitter (UART) interfaces for serial communication.  

The Bluetooth subsystem has two UART interfaces: a 4-pin interface for control and data transfer. The UART  

interfaces are compatible with the RS-232 standard, where ATBTLC1000 operates as Data Terminal Equipment  

(DTE). The 4-pin UART has two pins for data (TX and RX) and two pins for flow control/handshaking: Request To  

Send (RTS) and Clear To Send (CTS

).

The RTS and CTS are used for hardware flow control; they MUST be  

connected to the host MCU UART and enabled for the UART interface to be functional.

The pins associated  

with each the UART interfaces can be enabled on several alternative pins by programming their corresponding pin-  

MUX control registers (see

an

for available options).  

The UART features programmable baud rate generation with fractional clock division, which allows transmission  

and reception at a wide variety of standard and non-standard baud rates. The Bluetooth UART input clock is  

selectable between 26MHz, 13MHz, 6.5MHz, and 3.25MHz. The clock divider value is programmable as 13 integer  

bits and three fractional bits (with 8.0 being the smallest recommended value for normal operation). This results in  

the maximum supported baud rate of 26MHz/8.0 = 3.25MBd.  

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The UART can be configured for seven or eight bit operation, with or without parity, with four different parity types  

(odd, even, mark, or space), and with one or two stop bits. It also has RX and TX FIFOs, which ensure reliable  

high speed reception and low software overhead transmission. FIFO size is 4×8 for both RX and TX direction. The  

UART also has status registers showing the number of received characters available in the FIFO and various error  

conditions, as well the ability to generate interrupts based on these status bits.  

An example of UART receiving or transmitting a single packet is shown i

his example shows 7-bit  

data (0x45), odd parity, and two stop bits.  

Refer to the ATBTLC1000 Programming Guide for more specific instructions.  

Figure 10-6.

 

Example of UART RX or TX Packet  

10.6 GPIOs  

12 General Purpose Input/Output (GPIO) pins total, labeled LP_GPIO, GPIO_MS, and AO_GPIO, are available to  

allow for application specific functions. Each GPIO pin can be programmed as an input (the value of the pin can be  

read by the host or internal processor) or as an output (the output values can be programmed by the host or  

internal processor).  

LP_GPIO are digital interface pins, GPIO_MS is a mixed signal/analog interface pin and AO_GPIO is an always-on  

digital interface pin that can detect interrupt signals while in deep sleep mode for wake up purposes.  

The LP_GPIO have interrupt capability but only when in active/standby mode. In sleep mode, they are turned off to  

save power consumption.  

10.7 Analog

 

to Digital Converter (ADC)  

10.7.1 Overview  

The ATBTLC1000 has an integrated Successive Approximation Register (SAR) ADC with 11-bit resolution and  

variable conversion speed up 1MS/s. The key building blocks are the capacitive DAC, comparator, and  

synchronous SAR engine as shown i

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Figure 10-7.

 

BTLC1000 SAR ADC Block Diagram  

The ADC reference voltage can be either generated internally or set externally via one of the two available Mixed  

Signal GPIO pins on the ATBTLC1000.  

There are two modes of operation:  

A. High

 

resolution (11-bit): Set the reference voltage to half the supply voltage or below. In this condition the  

input signal dynamic range is equal to twice the reference voltage (ENOB=10bit).  

B. Medium

 

Resolution (10-bit): Set the reference voltage to any value below supply voltage (up to supply  

voltage – 300mV) and in this condition the input dynamic range is from zero to reference voltage (ENOB = 9  

bit).  

There are four input channels that are time multiplexed to the input of the SAR ADC. However on the  

ATBTLC1000, only one channel input is accessible from the outside, through the Mixed Signal GPIO pin.  

In power saving mode, the internal reference voltage is completely off and the reference voltage is set externally.  

The ADC characteristics are summarized in

Table 10-10.

 

SAR ADC Characteristics  

Conversion rate  

1ks → 1MS  

Selectable Resolution  

Power consumption  

10 → 11bit  

13.5µA (at 100KS/s)

(1)  

Note:  

1. With

 

external reference.  

10.7.2 Timing  

The ADC timing is shown i

The input signal is sampled twice, in the first sampling cycle the input  

range is defined either to be above reference voltage or below it and in the 2

nd

sampling instant the ADC start its  

normal operation.  

The ADC takes two sampling instants and N-1 conversion cycle (N=ADC resolution) and one cycle to sample the  

data out. So for 11-bit resolution it takes 13 clock cycles to do one Sample conversion.  

The Input clock equals N+2 the sampling clock frequency (N is the ADC resolution).  

CONV signal

 

: Gives indication about end of conversion.  

SAMPL  

: The input signal is sampled when this signal is high.  

RST ENG  

: When High SAR Engine is in reset mode (SAR engine output is set to mid-scale).  

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Figure 10-8.

 

SAR ADC Timing  

10.7.3 Performance  

Table 10-11.

 

Static Performance of SAR ADC  

Parameter  

Input voltage range  

Resolution  

Condition  

Min.  

Typ.  

Max.  

Unit  

V

0

VBAT  

11  

bits  

KSPS  

mV  

%

Sample rate  

100  

1000  

+10  

+4  

Input offset  

Gain error  

Internal VREF  

Internal VREF