Microchip-Tech-ATR2406-PNQW

Part #	Microchip-Tech-ATR2406-PNQW
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ATR2406

Low-IF 2.4-GHz ISM Transceiver

DATASHEET

Features

●

ully integrated low IF receiver

●

Fully integrated GFSK modulator for 72, 144, 288, 576 and 1152Kbits/s

●

High sensitivity of typically –93dBm due to integrated LNA

●

High output power of typically +4dBm

●

Multi-channel operation

●

95 channels

●

Support frequency hopping (ETSI) and digital modulation (FCC)

●

Supply-voltage range 2.9V to 3.6V (unregulated)

●

Auxiliary voltage regulator on chip (3.2V to 4.6V)

●

Low current consumption

●

Few low-cost external components

●

Integrated ramp-signal generator and power control for an additional power amplifier

●

Low profile lead-free plastic package QFN32 (5mm

5mm

0.9mm)

●

RoHs complia

Applications

●

High-tech multi-user toys

●

Wireless game controllers

●

lemetry

●

Wireless audio/video

●

Electronic point of sales

●

Wireless head set

●

FCC CFR47, part 15, ETSI EN 300 328, EN 300 440 and ARIB STD-T-66

compliant radio links

4779Q-ISM-09/14

Description

The Atmel

ATR2406 is a single chip RF transceiver intended for applications in the 2.4GHz ISM band.

The QFN32-packaged IC is a complete transceiver including image rejection mixer, low IF filter, FM demodulator, RSSI, TX

preamplifier, power-ramping generator for external power amplifier, integrated synthesizer, and a fully integrated VCO and

TX filter. No mechanical adjustment is necessary in production.

The RF transceiver offers a clock recovery function on-chip.

Figure 1-1.

Block Diagram

REG_DEC VREG REG_CTRL

VS_REG IREF

VS_SYN

VCO

REG

AUX

REG

AUX

REG

VS_IFD

VREG_VCO

RX_IN

VS_IFA

VS_RX/TX

LIMITER

RSSI

DEMOD

LNA

IR-Mixer

RX_DATA

RSSI

VCO

CLOCK

DATA

ENABLE

Divider

by 2

TX_OUT

BUS

TEST1

TEST2

PU_REG

PU_TRX

RX_ON

TX_ON

nOLE

GAUSSIAN

FILTER

RAMP

GEN

CTRL

LOGIC

RAMP_OUT

PLL

CP REF_CLK

TX_DATA VTUNE

ATR2406 [DATASHEET]

4779Q–ISM–09/14

Pin Configuration

Figure 2-1.

Pinning QFN32 – 5

32 31 30 29 28 27 26 25

PU_REG

REF_CLK

RSSI

VS_IFD

VS_IFA

RX_ON

RAMP_OUT

TX_OUT

RX_IN1

RX_IN2

VS_TRX

ATR2406

RX-CLOCK

IREF

10 11 12 13 14 15 16

Table 2-1.

Pin Description

Symbol

PU_REG

REF_CLK

RSSI

Function

Power-up input for auxiliary regulator

Reference frequency input

Received signal strength indicator output

Digital supply voltage

VS_IFD

VS_IFA

RX-CLOCK

Analog supply voltage for IF circuits

RX-CLOCK, if RX mode with clock recovery is active

Internally connected. Connect to V

if internal AUX regulator is not used

External resistor for band-gap reference

IREF

REG_CTRL

VREG

Auxiliary voltage regulator control output

Auxiliary voltage regulator output

VS_REG

REG_DEC

Auxiliary voltage regulator supply voltage

Decoupling pin for VCO_REG

VREG_VCO VCO

voltage regulator

VTUNE

VCO tuning voltage input

Charge-pump output

VS_SYN

VS_TRX

RX_IN2

RX_IN1

TX_OUT

Synchronous supply voltage

Transmitter receiver supply voltage

Differential receiver input 2

Differential receiver input 1

TX driver amplifier output

RAMP_OUT Ramp

generator output for PA power ramping

Internally connected, do not connect on PCB

RX control input

RX_ON

ATR2406 [DATASHEET]

4779Q–ISM–09/14

Table 2-1.

Pin Description (Continued)

Symbol

TX_ON

NOLE

Function

TX control input

Open loop enable input

RX/TX/PLL/VCO power-up input

RX data output

PU_TRX

RX_DATA

TX_DATA

CLOCK

DATA

TX data input

3-wire-bus: Clock input

3-wire-bus: Data input

3-wire-bus: Enable input

Ground

ENABLE

GND

Paddle

ATR2406 [DATASHEET]

4779Q–ISM–09/14

Functional Description

3.1

Receiver

The RF signal at RF_IN is differentially fed through the LNA to the image rejection mixer IR_MIXER, driving the integrated

low-IF band-pass filter. The IF frequency is 864kHz. The limiting IF_AMP with an integrated RSSI function feeds the signal to

the digital demodulator DEMOD. No tuning is required. Data slicing is handled internally.

3.2

3.3

Clock Recovery

For a 1152Kbit/s data rate, the receiver has a clock recovery function on-chip.

The receiver includes a clock recovery circuit which regenerates the clock out of the received data. The advantage is that

this recovered clock is synchronous to the clock of the transmitting device (and thus to the transmitted data), which

significantly reduces the load of the processing microcontroller.

The falling edge of the clock is the optimal sampling position for the RX_Data signal, so at this event the data must be

sampled by the microcontroller. The recovered clock is available at pin 6.

Transmitter

The transmit data at TX_DATA is filtered by an integrated Gaussian filter (GF) and fed to the fully integrated VCO operating

at twice the output frequency. After modulation, the signal is frequency divided by 2 and fed to the internal preamplifier PA.

This preamplifier supplies typically +4dBm output power at TX_OUT.

A ramp-signal generator RAMP_GEN, providing a ramp signal at RAMP_OUT for the external power amplifier, is integrated.

The slope of the ramp signal is controlled internally so that spurious requirements are fulfilled.

3.4

3.5

Synthesizer

The IR_MIXER, the PA, and the programmable counter (PC) are driven by the fully integrated VCO, using on-chip inductors

and varactors. The output signal is frequency divided to supply the desired frequency to the TX_DRIVER, the 0/90 degree

phase shifter for the IR_MIXER, and to be used by the PC for the phase detector (PD) (f

= 1.728MHz). Open loop

modulation is supported.

Power Supply

An integrated band-gap–stabilized voltage regulator for use with an external low-cost PNP transistor is implemented.

Multiple power-down and current saving modes are provided.

ATR2406 [DATASHEET]

4779Q–ISM–09/14

Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameters

Symbol

Min.

–0.3

–40

Max.

+4.7

+3.6

Unit

Supply voltage auxiliary regulator

Supply voltage

Control voltages

contr

stg

Storage temperature

Input RF level

+125

+10

°C

dBm

ESD_ana

ESD_dig

TBD

ESD protection

Thermal Resistance

Parameters

Symbol

Value

Unit

Junction ambient

thJA

K/W

Operating Range

Parameters

Symbol

Min.

2.9

Max.

3.6

Unit

Supply voltage

Auxiliary regulator supply voltage

mperature ambient

Input frequency range

S_BATT

amb

3.2

4.6

–10

2400

+60

2483

°C

MHz

ATR2406 [DATASHEET]

4779Q–ISM–09/14

Electrical Characteristics

= 3.6V with AUX regulator, T

amb

= 25°C, unless otherwise specified

No. Parameters

Supply

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

1.1 Supply

voltage

1.2 Supply

voltage

With AUX regulator

3.2

2.9

3.6

3.0

4.6

3.6

Without AUX regulator

CW mode (peak current)

Burst mode at 10Kbits/s

(4)

CW mode (peak current)

Burst mode at 10Kbits/s

(4)

µA

1.3 RX

supply current

1.4 TX

supply current

625

500

Battery lifetime of a remote

1.5 control

application using an

AVR

See

Section 11. “Appendix:

Current Calculations for a Remote

Control” on page 21

Supply current in power-down

With AUX regulator

1.6

< 1

µA

mode

PU_TRX = 0; PU_REG = 0

Supply current in power-down

Without AUX regulator

1.7

mode

PU_TRX = 0; PU_REG = 0

Voltage Regulator

2.1 AUX

regulator

2.2 VCO

regulator

VREG

3.0

2.7

VREG_VCO

Transmitter Part

3.1 TX

data rate

72/144/288/576/1152

kBits/s

dBm

MHz

kHz

3.2 Output

power

PTX

3.3 TX

data filter clock

3.4 Frequency

deviation

9 taps in filter

TXFCLK

10.368/13.824

±400

e tuned by GFCS bits

FM_nom

GFFM = GF

FM_nom

GFCS

(Refer to bus protocol D9 to D11)

3.5 Frequency

deviation scaling

(3)

GFCS

130

With standard loop filter and slot

length of 1400µs (refer to the

application note “ATR2406 Loop

Filter and Data Rates”)

3.6 Frequency

drift

3.7 Harmonics

Dfo (drift)

±40

kHz

BW = 100kHz

(1)

–41.2

dBm

Spurious emissions

30 to 1000MHz

3.8 1

to 12.75GHz

1.8 to 1.9GHz

–57

dBm

BW = 100kHz

(1)

5.15 to 5.3GHz

Ramp Generator, Pin 21

4.1 Minimum

output voltage

4.2 Maximum

output voltage

4.3 Rise

time

TX_ON = low

min

max

0.7

Refer to bus protocol D12 to D13

1.1

1.9

µs

Notes: 1.

Measured and guaranteed only on the Atmel

evaluation board, including microstrip filter, balun, and smart radio fre-

quency (smart RF) firmware. Conducted measured.

2. Timing

is determined by external loop filter characteristics. Faster timing can be achieved by modification of the loop fil-

ter. For further information refer to the application notes.

3. The

Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation devia-

tion in production to the nominal value of 400kHz.

4. Burst

mode with 0.9% duty cycle

ATR2406 [DATASHEET]

4779Q–ISM–09/14

Electrical Characteristics (Continued)

= 3.6V with AUX regulator, T

amb

= 25°C, unless otherwise specified

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

4.4 Fall

time

µs

Receiver Part

5.1 RX

input impedance

Differential

170 + j0

–93

At input for BER

≤

-3

5.2 Sensitivity

dBm

1152Kbits/s

(1)

5.3 Third

order input intercept point

IIP3

–15

BER < 10

-3

, wanted at –83dBm,

level of interferers in channels

N + 2 and N + 4

(1)

5.4 Intermodulation

rejection

5.5 Co-channel

rejection

–11

dBc

BER < 10

-3

, wanted at –76dBm

(1)

BER < 10

-3

, wanted at –76dBm,

adjacent level referred to wanted

channel level

(1)

Adjacent channel rejection

±1.728MHz

5.6

i (N – 1)

BER < 10

-3

, wanted at –76dBm,

bi-adjacent level referred to

wanted channel level

(1)

Bi-adjacent channel rejection

±3.456MHz

5.7

i (N – 2)

dBc

Rejection with

≥

3 channels

5.8 separation

BER < 10

-3

, wanted at –76dBm,

≥

3 adjacent level referred to

wanted channel level

(1)

BER < 10

-3

, wanted at –83dBm at

2.45GHz

(1)

i (n

≥

dBc

≥

±5.128MHz

5.9 Out

of band rejection > 6MHz

df>6MHz

Out of band rejection

5.10 2300MHz

to 2394MHz

2506MHz to 2600GHz

BER < 10

-3

, wanted at –83dBm at

2.45GHz

(1)

near

Out of band rejection

5.11 30MHz

to 2300MHz

2600MHz to 6GHz

BER < 10

-3

, wanted at –83dBm at

2.45GHz

(1)

far

dBc

RSSI Part

6.1 Maximum

RSSI output voltage

Under high RX input signal level

RSSImax

RSSI

2.1

RSSI output voltage, monotonic

With –33dBm at RF input

1.9

0.1

6.2

over range –96dBm to –36dBm

With –96dBm at RF input

VCO

Oscillator frequency defined at

TX output

7.1

Over full temperature range

(1)

2400

0.5

2483

MHz

Frequency control voltage

range

–

7.2

7.3

VTUNE

VCO

0.5

VCO tuning input gain defined

at TX output

240

MHz/V

Notes: 1.

Measured and guaranteed only on the Atmel

evaluation board, including microstrip filter, balun, and smart radio fre-

quency (smart RF) firmware. Conducted measured.

2. Timing

is determined by external loop filter characteristics. Faster timing can be achieved by modification of the loop fil-

ter. For further information refer to the application notes.

3. The

Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation devia-

tion in production to the nominal value of 400kHz.

4. Burst

mode with 0.9% duty cycle

ATR2406 [DATASHEET]

4779Q–ISM–09/14

Electrical Characteristics (Continued)

= 3.6V with AUX regulator, T

amb

= 25°C, unless otherwise specified

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Synthesizer

External reference input

frequency

D7 = 0

D7 = 1

10.368

13.824

MHz

8.1

REF_CLK

Sinusoidal input signal level

(peak-to-peak value)

8.2

AC-coupled sine wave

500

1000

8.3 Scaling

factor prescaler

PSC

32/33

–

8.4 Scaling

factor main counter

8.5 Scaling

factor swallow counter

86/87/88/89

Phase Detector

Phase detector comparison

frequency

9.1

1728

kHz

10 Charge-pump

Output

10.1 Charge-pump

output current

10.2 Leakage

current

= 1/2 V

±2

±100

1000

11 Timing

Conditions

(1)(2)

11.1 Transmit

to receive time

11.2 Receive

to transmit time

11.3 Channel

switch time

11.4 Power

down to transmit

11.5 Power

down to receive

11.6 Programming

11.7 PLL

settling time

Reference clock stable

→

RX time

→

TX time

CS time

200

250

200

µs

→

TR time

→

RX time

PRR time

PLL set time

200

12 Interface

Logic Input and Output Signal Levels, Pin DATA, CLOCK, ENABLE

12.1 HIGH-level

input voltage

12.2 LOW-level

input voltage

12.3 HIGH-level

output voltage

12.4 LOW-level

output voltage

12.5 Input

bias current

Logic 1

1.4

3.1

+0.4

3.1

Logic 0

–0.3

Logic 1

Logic 0

Logic 1 or logic 0

bias

–5

µA

12.6 3-wire

bus clock frequency

CLKmax

MHz

Notes: 1.

Measured and guaranteed only on the Atmel

evaluation board, including microstrip filter, balun, and smart radio fre-

quency (smart RF) firmware. Conducted measured.

2. Timing

is determined by external loop filter characteristics. Faster timing can be achieved by modification of the loop fil-

ter. For further information refer to the application notes.

3. The

Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation devia-

tion in production to the nominal value of 400kHz.

4. Burst

mode with 0.9% duty cycle

ATR2406 [DATASHEET]

4779Q–ISM–09/14

PLL Principle

Figure 8-1.

PLL Principle

Programmable counter PC

“- Main counter MC

“- Swallow counter SC

_{CVO
= 1728kHz x (S
MC
x 32 + S
SC
)}

External

loop filter

PA driver

Mixer

Phase frequency

Charge

pump

Divide

by 2

detector (PD)

VCO

_{PD
= 1728kHz}

Gaussian

filter (GF)

Reference counter (RC)

REF_CLK

10.368MHz

13.824MHz

TXDAT

PLL reference frequency

REF_CLK

Baseband controller

ble 8-1

shows the LO frequencies for RX and TX in the 2.4-GHz ISM band. There are 95 channels available. Since the

ATR2406 supports wideband modulation with 400-kHz deviation, every second channel can be used without overlap in the

spectrum.

Table 8-1.

LO Frequencies

Mode

/kHz

Channel

ANT

/MHz

2401.056

2401.920

…

VCO

/MHz divided by 2

2401.056

2401.920

…

2779

2780

…

C93

C94

2481.408

2482.272

2401.056

2401.920

…

2481.408

2482.272

2401.920

2402.784

…

2872

2873

2780

2781

…

864

…

C93

C94

2481.408

2482.272

2483.136

2873

2874

ATR2406 [DATASHEET]

4779Q–ISM–09/14

8.1

TX Register Setting

The following 16-bit word has to be programmed for TX.

MSB

LSB

Data bits

D15

D14

D13

D12

D11

D10

GFCS

Note:

D12 and D13 are only relevant if ramping generator in conjunction with external PA is used, otherwise it can be

programmed 0 or 1.

Table 8-2.

Output Power Settings with Bits D12 – D13

PA (Output Power Settings)

D13

D12

RAMP_OUT (Pin 21)

1.3V

1.35V

1.4V

1.75V

The VRAMP voltage is used to control the output power of an external power amplifier. The voltage ramp is started with the

TX_ON signal.

These bits are only relevant in TX mode.

8.2

RX Register Setting

There are two RX settings possible. For a data rate of 1152kBits/s, an internal clock recovery function is implemented.

8.3

Must be used for data rates below 1.152Mbits/s.

MSB

LSB

Data bits

D15

D14

D13

D12

D11

D10

Note:

X values are not relevant and can be set to 0 or 1.

ATR2406 [DATASHEET]

4779Q–ISM–09/14

8.4

RX Register Setting with Internal Clock Recovery

Recommended for 1.152Mbit/s data rate.

The output pin of the recovered clock is pin 6. The falling edge of the recovered clock signal samples the data signal.

MSB

Data bits

D24

D23

D22

D21

D20

D19

D18

D17

D16

LSB

Data bits

D15

D14

D13

D12

D11

D10

Note:

X values are not relevant and can be set to 0 or 1.

8.5

PLL Settings

RC, MC and SC bits control the synthesizer frequency as shown in

ble 8-3

ble 8-4 on page 12

and

ble 8-5 on page

Formula for calculating the frequency:

TX frequency: f

ANT

= 864kHz

(32

+ S

)

RX frequency: f

ANT

= 864kHz

(32

+ S

– 1)

Table 8-3.

PLL Settings of the Reference Counter Bit D7

RC (Reference Counter)

CLK Reference

10.368MHz

13.824MHz

Table 8-4.

PLL Settings of the Main Counter Bits D5 to D6

MC (Main Counter)

ATR2406 [DATASHEET]

4779Q–ISM–09/14

Table 8-5.

PLL Settings of the Swallow Counter Bits D0 to D4

SC (Swallow Counter)

…

8.6

GFCS Adjustment

The Gaussian filter control setting (GFCS) is used to compensate for production tolerances by tuning the modulation

deviation in production to the nominal value of 400kHz. These bits are only relevant in TX mode.

Table 8-6.

GFCS Adjustment of Bits D9 – D11

GFCS

D11

D10

GFCS

60%

70%

80%

90%

100%

110%

120%

130%

8.7

Control Signals

The various transceiver functions are activated by the following control signals. A timing proposal is shown in

Figure 8-3 on

page 15

Table 8-7.

Control Signals and Functions

Signal

Functions

Activates AUX voltage regulator and the VCO voltage regulator supplying the complete

transceiver

PU_REG

PU_TRX

RX_ON

TX_ON

NOLE

Activates RX/TX blocks

Activates RX circuits: DEMOD, IF AM

R MIXER

Activates TX circuits: PA, RAMP GEN, Starts RAMP SIGNAL at RAMP_OUT

Disables open loop mode of the PLL

ATR2406 [DATASHEET]

4779Q–ISM–09/14

8.8

8.9

Serial Programming Bus

The transceiver is programmed by the SPI (CLOCK, DATA and ENABLE).

After setting the enable signal to low, the data is transferred bit by bit into the shift register on the rising edge of the clock

signal, starting with the MSBit. When the enable signal has returned to high, the programmed information is active.

Additional leading bits are ignored and there is no check made of how many clock pulses arrived during enable low.

The programming of the transceiver is done by a 16-bit or 25-bit data word (for the RX clock recovery mode).

3-wire Bus Timing

Figure 8-2.

3-wire Bus Protocol Timing Diagram

DATA

CLOCK

ENABLE

TPER

TS TC

TEC

Table 8-8.

3-wire Bus Protocol Table

Description

Symbol

Minimum Value

Unit

Clock period

TPER

100

Set time data to clock

Hold time data to clock

Clock pulse width

Set time enable to clock

Hold time enable to data

Time between two protocols

100

TEC

250

ATR2406 [DATASHEET]

4779Q–ISM–09/14

Figure 8-3.

Example TX and RX Timing Diagram

Signals to TRX (Input)

Signals from

TRX (Output)

ATR2406 [DATASHEET]

4779Q–ISM–09/14

Table 8-9.

Description of the Conditions/States

Condition

Description

Power down

ATR2406 is switched off and the supply current is lower than 1µA.

Power up

ATR2406 is powered up by toggling PU_REG and PU_TRX to high.

PU_REG enables the external AUX regulator transistor including VCO regulator. PU_TRX

enables internal blocks like the PLL and the VCO.

Depending on the value of the external capacitors (for example, at the AUX regulator, if one is

used), it is necessary to wait at least 40µs until the different supply voltages have settled.

Programming

The internal register of the ATR2406 is programmed via the three-wire interface. At TX, this is just

the PLL (transmit channel) and the deviation (Gaussian filter).

At RX, this is just the PLL (receive channel) and, if the clock recovery is used, also the bits to

enable this option. At the start of the three-wire programming, the enable signal is toggled from

high to low to enable clocking the data into the internal register. When the enable signal rises

again to high, the programmed data is latched. This is the time point at which the settling of the

PLL starts. It is necessary to wait the settling time of 200µs so that the VCO frequency is stable.

The reference clock needs to be applied to ATR2406 for at least the time when the PLL is in

operation, which is the programming state (C3) and the active slot (C4, C5). Out of the reference

clock, several internal signals are also derived, for example, the Gaussian filter circuitry and

TX_DATA sampling.

This is the receive slot where the transmit burst is received and data as well as recovered clock

are available.

This is the active transmit slot. As soon as TX_DATA is applied to ATR2406, the signal nOLE

toggles to low which enables modulation in open-loop mode.

The preamble (1-0-1-0 pattern) should start being sent at the start of TX_ON.

8.10 Received

Signal Strength Indication (RSSI)

The RSSI is given as an analog voltage at the RSSI pin. A typical plot of the RSSI value is shown in

Figure 8-4

Figure 8-4.

Typical RSSI Value versus Input Power

2.5

2.0

1.5

1.0

0.5

-130

-110

-90

-70

-50

-30

-10

RF Level (dBm)

ATR2406 [DATASHEET]

4779Q–ISM–09/14

Application Circuit

The Atmel

ATR2406 requires only a few low-cost external components for operation. A typical application is shown in

Figure 9-3 on page 18

9.1

Typical Application Circuit

Figure 9-1.

Microcontroller Interfacing with General Purpose MCU, Pin Connections between Microcontroller and

ATR2406

Microcontroller

ATR2406

TX_DATA

RX_DATA

RX-CLOCK

ENABLE

CLOCK

DATA

Ctrl_Lines

REF_CLK

XTAL

(1)

XTAL_OUT

Figure 9-2.

Example with AVR MCU

AVR_MCU

ATR2406

USART

RF_DATA

TXD

RXD

XCK

TX_DATA

RX_DATA

RX-CLOCK

GPIO

RF_CTRL

ENABLE

CLOCK

DATA

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

nOLE

TX_ON

RX_ON

PU_REG

PU_TRX

RSSI

13.824MHz XTAL

REF_CLK

Note:

1. XTAL:

for example, XRFBCC-NANL; 13.824MHz, 10ppm

Order at:

itien Electronic,

itien Specific No.: A009-x-B26-3, SMD

ATR2406 [DATASHEET]

4779Q–ISM–09/14

Figure 9-3.

Application Circuit for ATR2406-DEV-BOARD

F antenna

ANT

GND

ANT2

GND

R2 NC

SMASI

J24

1.8pF

R5 1.5k

Microstrip

Low-passfilter

2.2pF

1.5k

Slug

2.2pF

GND3

GND1

GND6

GND5

GND4

GND9

GND8

GND7

GND2

C10

Microstrip

1.5pF

1.8pF

IC2P

GND

VBATT

Microstrip

balun

5.6pF

Microstrip

TP1 TP2

RAMP_OUT

RX_ON

J26

C14

C20

22nF

IC2

C20, C21, COG

dielectric

TX_ON

nOLE

390pF

RAMP

GND

TX_ON

nOLE

PU_TRX

RX_DATA

TX_DATA

CLOCK

DATA

C21

VS_SYN

VTUNE

PU_TRX

RX_DATA

C18

2.2nF

VREG_VCO

REG_DEC

VS_REG

VREG

REG_CTRL

C17

TX_DATA

68pF

C19

CLOCK

ENABLE

DATA

470nF

ENABLE

C29

62k

C24

4.7pF

C16

4.7μF

PU_REG

REF_CLK

RSSI

4.7nF

C11

BC808

18pF

C15

C12

C13

100nF

4.7μF

RX_CLOCK

ATR2406 [DATASHEET]

4779Q–ISM–09/14

10. PCB

Layout Design

Figure 10-1. PCB Layout ATR2406-DEV-BOARD

ATR2406 [DATASHEET]

4779Q–ISM–09/14

Table 10-1.

Bill of Materials

Part

Value

5.6pF

1.8pF

390pF

4.7pF

2.2pF

1.5pF

18pF

Part Number

Vendor

Package

0402

Comment

C3, C10

0402

C6, C7

0402

C11

0402

C12, C15

C13, C16

C14

100nF

4.7µF

1nF

0402

B45196H2475M109

Epcos

3216

Optional

(2)

0402

C17

3.3nF

68pF

0402

C18

0402

C19

470nF

0402/0603

mportant for good

RF performance

C20

C21

22n

GRM21B5C1H223JA01

2.2n

GRM1885C1H222JA01

Murata

0805

0603

mportant for good

RF performance

C23

C24

4.7nF

4.7pF

0402

MLF32

62k

1.0k

1.5k

62k,

≤

1k0,

≤

1k5,

≤

1k5,

≤

Ref_Clk level, optional

(1)

Ref_Clk level, optional

(1)

IC2

ATR2406 ATR2406

Atmel

BC808-40, any standard type can be

used, but it is important that be “–40”!

Vishay

BC808-40

FR4

SOT-23

Optional

(2)

Philips

, etc.

FR4, e_r = 4.4 at 2.45GHz, H = 500µm, T = 35µm, t

and

= 0.02, surface, that is, chem. tin or chem.

gold

MSUB

Notes: 1.

Not necessary if supplied RefClk level is within specification range

2. If

no AUX regulator is used, then T1 and C16 can be removed and a jumper is needed from the collector to the

emitter pad. Additionally, pin 7 of the ATR2406 has to be connected to pin 4 or pin 5 to use the integrated F

antenna, set jumper R2 (0R resistor 0603)

Table 10-2.

Parts Count Bill of Materials

Parts Count

Capacitors 0402

Capacitors >0402

Resistors 0402

Inductors 0402

Semiconductors

Required (Minimal BOM)

Optional (Depending on Application)

–

ATR2406 [DATASHEET]

4779Q–ISM–09/14

11. Appendix:

Current Calculations for a Remote Control

Assumptions:

A data packet consists of 24 bytes.

Protocol

24 bytes = 240bits (USART connection)

packet_length

= 210µs at 1.152Mbits/s

The system will use five predefined channels for frequency hopping spread spectrum

(FHSS) which gives improved immunity against interferers

Channel

Loop filter

Loop filter settling time will be 110µs

If not in use, the handheld device will be in power-down mode with the AVR

watchdog

timer disabled. The AVR power-down current is typically 1.25µA. If an external voltage

regulator is used, additional power-down current has to be taken into account

Handheld device

The base station will periodically scan all the channels of the used subset. The base station

will stay on one channel for 2 seconds. If the base station receives a correct packet, an

acknowledge will be returned to the handheld device. The power consumption of the base

station device is not power-sensitive, as this part of the application is normally mains

powered

Base station device

Basic Numbers:

Peak current ATR2406 in TX at 1.152Kbits/s

Peak current ATR2406 in RX at 1.152Kbits/s

Peak current ATR2406 with synthesizer running

Current ATmega88 active

42mA

57mA

26mA

5mA

Current ATmega88 power down (no WDT)

Current ATmega88 power down (+ WDT)

Loop settling time of ATR2406

1.25µA

5µA

110µs

30µs

Configuration of ATR2406

Time needed for exchanging a packet at 1.152Kbits/s

210µs

Amount of Current Needed to Transmit One Packet:

Q1 = (0.005A + 0.026A)

5030µs = 155µAs (charge up time ATR2406 + AVR internal calculations)

Q2 = (0.005A + 0.026A)

30µs = 0.93µAs (charge for configuring the ATR2406)

Q3 = (0.005A + 0.026A)

110µs = 3.41µAs (charge for settling the loop filter)

Q4 = (0.005A + 0.042A)

210µs = 9.87µAs (charge for transmitting the packet)

Q5 = (0.005A) ´ 250 µs = 1.25µAs (charge for turn around (TX to RX, RX to TX, etc.))

Q6 = (0.005A + 0.026A)

30µs = 0.93µAs (charge for configuring the ATR2406)

Q7 = (0.005A + 0.026A)

60µs = 1.86µAs (charge for settling the loop filter)

Q8 = (0.005A + 0.057A)

50µs = 3.10 µAs (charge until valid data can be received)

Q9 = (0.005A + 0.057A)

210µs = 13.02µAs (charge for receiving the packet)

Q10 = (0.005A + 0.057A)

50µs = 3.1µAs (charge for latency before receiving)

ATR2406 [DATASHEET]

4779Q–ISM–09/14

A successful packet exchange needs the following charge

Q = Q1 + Q2 + Q3 + Q4 + Q5 + Q6 + Q7 + Q8 + Q9 + Q10 = 192.47µAs

As the described system is a FHSS system with 5 different channels, the system has to do this up to five times before the

packet is acknowledged by the base station. The average will be 2.5 times. In the case of an interfered environment, some

more retries may be required; therefore, it is assumed the factor will be 3. The power-up time is included only once, as the

cycle will be completed without powering up and down the handheld in order to be as power efficient as possible.

Average current needed for a packet exchange:

155µAs + (37.5µAs

3) = 267.5µAs

If the device will be used 1000 times a day

→

3.1µA

Average current in active mode:

→

System power down current:

Current ATmega88:

Current ATR2406:

1.25µA

1.0µA

Current VREG (+ ShutDown):

2.75µA

Assumed average power-down current is 5µA.

→

Overall power consumption is 8.1µA

It is assumed the system uses a small battery with a capacity of 100mAh. This is 100.000µAh.

→

Battery lifetime will be around: 12345 hours = 514 days = 1.4 years.

The most important factor is to get the power-down current as low as possible!

Example:

Assume a system where the handheld is used just 10 times per day.

→

active

= 0.031µA

and assuming the power-down current of this device is just 4 µA.

→

I = 0.031µA + 4µA = 4.03µA

→

Battery lifetime will be around 24807 hours = 1033 days = 2.83 years.

→

Power-down current is the main factor influencing the battery lifetime.

ATR2406 [DATASHEET]

4779Q–ISM–09/14

12. Ordering

Information

Extended Type Number

Package

Remarks

MOQ

ATR2406-PNQW

QFN32 – 5×5

ped and reeled, Pb-free

6000

13. Package

Information

Top View

technical drawings

according to DIN

specifications

PIN 1 ID

Dimensions in mm

Side View

Bottom View

COMMON DIMENSIONS

(Unit of Measure = mm)

Symbol MIN

NOM

0.85

0.035

0.21

MAX NOTE

0.8

0.9

0.05

0.26

5.1

Z 10:1

0.16

4.9

3.5

4.9

3.5

0.35

0.2

3.6

3.7

5.1

3.6

3.7

0.4

0.45

0.3

0.25

0.5

05/20/14

TITLE

DRAWING NO.

GPC

Package Drawing Contact:

packagedrawings@atmel.com

Package: QFN_5x5_32L

Exposed pad 3.6×3.6

6.543-5203.01-4

ATR2406 [DATASHEET]

4779Q–ISM–09/14

14. Recommended

Footprint/Landing Pattern

Figure 14-1. Recommenced Footprint/Landing Pattern

Table 14-1.

Recommended Footprint/Landing Pattern Signs

Sign

Size

3.2mm

1.2mm

0.3mm

1.1mm

0.3mm

0.2mm

0.55mm

0.5mm

ATR2406 [DATASHEET]

4779Q–ISM–09/14

15. Revision

History

Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this

document.

Revision No.

History

•

Section 11 “Ordering Information” on page 23 updated

•

Section 12 “Package Information” on page 23 updated

•

Section 11 “Ordering Information” on page 23 updated

•

Put datasheet in the latest template

4779Q-ISM-09/14

4779P-ISM-09/14

4779O-ISM-03/14

•

Put datasheet in the latest template

4779N-ISM-12/08

4779M-ISM-02/07

•

Section 12 “Package Information” on page 22 updated

•

Put datasheet in the latest template

•

ble 9-1 “Bill of Materials” on page 19 updated

•

ble “Electrical Characteristics” on pages 6 to 8 updated

•

Section 10 “Appendix: Current calculations for a remote control” on pages 20 to 21

updated

4779L-ISM-08/06

4779K-ISM-06/06

•

ble “Ordering Information” on page 22 updated

•

Minor corrections to grammar and style throughout document

•

Put datasheet in a new template

•

ble “Electrical Characteristics” on pages 6 to 8 updated

•

Section 10 “Appendix: Current calculations for a remote control” on pages 20 to 21

added

•

Ordering information on page 22 updated

ATR2406 [DATASHEET]

4779Q–ISM–09/14

X X X X

Atmel Corporation

1600 Technology Drive, San Jose, CA 95110 USA

(+1)(408) 441.0311

(+1)(408) 436.4200

www.atmel.com

Atmel

, Atmel logo and combinations thereof, Enabling Unlimited Possibilities

, AVR

, and others are registered trademarks or trademarks of Atmel Corporation or its

subsidiaries. Other terms and product names may be trademarks of others.

DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right

is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE

ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS

INCLUDIN

UT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILIT

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NDIREC

ONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDIN

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FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMEN

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-CRITICAL, MILITAR

ND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where

the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer’s specific written

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Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are

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Microchip-Tech-ATR2406-PNQW

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