Microchip-Tech-ATSAMR34J18B-I-7JX

SAM R34/R35  

®

SAM R34/R35 Low Power LoRa

 

Sub-GHz SiP Datasheet  

Introduction  

The SAM R34/R35 is a family of ultra-low power microcontrollers combined with a UHF transceiver  

®

®

communication interface. It uses a 32-bit ARM

 

Cortex -M0+

 

processor and offers up to 256 KB of  

Flash and 40 KB of SRAM, including an area of battery backed-up SRAM. The UHF transceiver supports  

®

LoRa and

 

FSK modulation. LoRa technology is a spread spectrum protocol optimized for low data-rate,  

ultra-long range signaling. It is ideal for battery-powered remote sensors and controls.  

The SAM R34 includes an integrated microcontroller with USB and the UHF transceiver, making it  

suitable for USB dongle applications or for software updates via USB. The SAM R35 offers the same  

microcontroller functions along with the UHF transceiver without the USB interface.  

Features  

Operational Features  

• Processor:  

®

– ARM

 

Cortex -M0+ CPU running at up to 48 MHz (2.46CoreMark

 

/MHz)  

– Single-Cycle

 

Hardware Multiplier  

– Micro

 

Trace Buffer (MTB)  

• Memory:  

– In-System

 

Self-Programmable Flash Memory, with options for sizes – 256 KB, 128 KB or 64 KB  

– Static

 

Random Access Memory (SRAM) with options for sizes – 32 KB, 16 KB or 8 KB  

– Low

 

power SRAM Memory with option for sizes – 4 KB or 8 KB  

• System:  

– Power-on

 

Reset (POR) and Brown-out Reset  

– Internal

 

and External Clock Options with 48 MHz Digital Frequency Locked Loop (DFLL48M)  

and 48 MHz to 96 MHz Fractional Digital Phase Locked Loop (FDPLL96M)  

– External

 

Interrupt Controller (EIC)  

– Up

 

to 16 External Interrupts  

– One

 

Non-Maskable Interrupt  

– Two

 

Pin Serial Wire Debug (SWD) Programming,

T

e

st and Debugging Interfaces  

• Operating

 

Voltage: 1.8V- 3.6V  

• Low

 

Power Consumption  

– Transceiver:  

• RX

 

= 16 mA (typical)  

• RFO_HF

 

= 33 mA (typical)  

• PA_BOOST

 

= 95 mA (typical)  

DS70005356C-page 1  

Datasheet  

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SAM R34/R35  

– MCU:  

• Idle,

 

Standby, and Backup Sleep Modes  

• SleepWalking

 

peripherals  

•

T

e

mperature

 

Range: -40°C to +85°C (Industrial)  

RF/Analog Features  

• Integrated

 

LoRa

T

e

chnology Transceiver:  

– Tri-band

 

Coverage  

• 137

 

MHz to 175 MHz  

• 410

 

MHz to 525 MHz  

• 862

 

MHz to 1020 MHz  

– +20

 

dBm (100 mW) Max Power (VDDANA > 2.4 VDC)  

– +17

 

dBm (50 mW) Max Power (Regulated PA)  

– +13

 

dBm (20 mW) High-efficency PA  

• High

 

Sensitivity:  

™

– Down

 

to -136 dBm (LoRaWAN

 

protocol compliant modes)  

– Down

 

to -148 dBm (proprietary narrowband modes)  

• Up

 

to 168 dB Maximum Link Budget  

• Robust

 

Front-End: IIp3 = -11 dBm  

• Excellent

 

Blocking Immunity  

• Low

 

RX Current of 17 mA (typical)  

• Fully

 

Integrated Synthesizer with a Resolution of 61 Hz  

• LoRa

 

T

e

chnology, (G)FSK, (G)MSK and OOK Modulation  

• Preamble

 

Detection  

• 127

 

dB Dynamic Range RSSI  

• Automatic

 

RF Sense and CAD with Ultra-Fast Automatic Frequency Control (AFC) Packet Engine up  

to 256 bytes with Cyclic Redundancy Check (CRC)  

Peripheral Information  

• 16-Channel

 

Direct Memory Access Controller (DMAC)  

• 12-Channel

 

Event System  

• Three

 

16-bit Timer/Counters (TC), configurable as either of the following:  

– One

 

8-bit TC with compare/capture channels  

– One

 

16-bit TC with compare/capture channels  

– One

 

32-bit TC with compare/capture channels, by using two TCs  

• Two

 

24-bit and one 16-bit Timer/Counters for Control (TCC), with Extended Functions:  

– Up

 

to four compare channels with optional complementary output  

– Generation

 

of synchronized Pulse Width Modulation (PWM) pattern across port pins  

– Deterministic

 

fault protection, fast decay and configurable dead-time between complementary  

output  

– Dithering

 

that increases resolution with up to five bit and reduces quantization error  

• 32-bit

 

Real Time Counter (RTC) with Clock/Calendar Function  

• Watchdog

 

Timer (WDT)  

DS70005356C-page 2  

Datasheet  

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SAM R34/R35  

• CRC-32

 

Generator  

• One

 

Full-Speed (12 Mbps) Universal Serial Bus (USB) 2.0 Interface:  

– Embedded

 

host and device function  

– Eight

 

endpoints  

• Up

 

to Five Serial Communication Interfaces (SERCOM), each configurable to operate as either of the  

following:  

– USART

 

with full-duplex and single-wire half-duplex configuration  

– I2C

 

up to 3.4 MHz  

– Serial

 

Peripheral Interface (SPI)  

– Local

 

Interconnect Network (LIN) Slave  

• One

 

12-bit, 1 Msps Analog-to-Digital Converter (ADC) with up to Eight External Channels:  

– Differential

 

and single-ended input  

– Automatic

 

offset and gain error compensation  

– Oversampling

 

and decimation in hardware to support 13-, 14-, 15-, or 16-bit resolution  

• Two

 

Analog Comparators (AC) with Window Compare Function  

• Peripheral

 

T

o

uch Controller (PTC):  

– 18-channel

 

capacitive touch and proximity sensing  

Package Information  

• 27

 

Programmable I/O Pins  

• 64

 

Lead Ball Grid Array (BGA)  

DS70005356C-page 3  

Datasheet  

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SAM R34/R35  

Table of Contents  

Introduction……………………………………………………………………………………………………….1  

Features………………………………………………………………………………………………………….. 1  

1. Description…………………………………………………………………………………………………..6  

2. Configuration

 

Summary………………………………………………………………………………..

.

7  

3. Ordering

 

Information for SAM R34/R35………………………………………………………….. 9  

3.1. SAM

 

R34/R35 Ordering Codes………………………………………………………………………………………

.

9  

4. System

 

Introduction…………………………………………………………………………………….10  

4.1. SAM

 

R34/R35 Pinout Details……………………………………………………………………………………….. 10  

4.2. SiP

 

Block Diagram……………………………………………………………………………………………………… 10  

4.3. Peripheral

 

Key

T

a

ble…………………………………………………………………………………………………… 11  

5. I/O

 

Multiplexing and Considerations………………………………………………………………14  

5.1. Multiplexed

 

Signals…………………………………………………………………………………………………….. 14  

5.2. Internal

 

Multiplexed Signals…………………………………………………………………………………………. 15  

5.3. Other

 

Functions…………………………………………………………………………………………………………..16  

6. Signal

 

Description……………………………………………………………………………………….18  

6.1. Signal

 

Details…………………………………………………………………………………………………………….. 18  

7. Processor

 

and Architecture…………………………………………………………………………. 21  

7.1. Cortex

 

M0+ Processor………………………………………………………………………………………………… 21  

7.2. Nested

 

Vector Interrupt Controller………………………………………………………………………………….22  

7.3. Micro

 

Trace Buffer………………………………………………………………………………………………………

.

2

4  

7.4. High-Speed

 

Bus System……………………………………………………………………………………………… 25  

8. Application

 

Schematic Introduction………………………………………………………………. 30  

8.1. SAM

 

R34/R35 Basic Application Schematic…………………………………………………………………… 30  

8.2. SAM

 

R34/R35 Bill of Materials……………………………………………………………………………………..

.

3

2  

9. Transceiver

 

Circuit Description……………………………………………………………………..34  

9.1. Transceiver

 

Pin Description…………………………………………………………………………………………..34  

9.2. Transceiver

 

Validation…………………………………………………………………………………………………. 35  

10. Microcontroller Interface……………………………………………………………………………..

.

3

6  

11. Electrical Characteristics…………………………………………………………………………….. 38  

11.1. Absolute

 

Maximum Ratings…………………………………………………………………………………………..38  

11.2. General

 

Operating Conditions……………………………………………………………………………………….38  

11.3. Performance

 

Characteristics………………………………………………………………………………………..

.

3

9  

12. SAM R34/R35 Package Information………………………………………………………………44  

DS70005356C-page 4  

Datasheet  

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SAM R34/R35  

12.1. Package

 

Drawings……………………………………………………………………………………………………… 44  

12.2. SAM

 

R34/R35 Land Pattern………………………………………………………………………………………….45  

13. Best Practices for Designers……………………………………………………………………….. 46  

13.1. Introduction…………………………………………………………………………………………………………………46  

13.2. Power

 

Supply…………………………………………………………………………………………………………….. 46  

13.3. External

 

Reset Circuit…………………………………………………………………………………………………..49  

13.4. Unused

 

or Unconnected Pins………………………………………………………………………………………..50  

13.5. Clocks

 

and Crystal Oscillators……………………………………………………………………………………….50  

13.6. Programming

 

and Debug Ports……………………………………………………………………………………..52  

14. Reference Documentation……………………………………………………………………………57  

15. Document Revision History…………………………………………………………………………. 58  

The Microchip Web Site…………………………………………………………………………………… 59  

Customer Change Notification Service………………………………………………………………..59  

Customer Support…………………………………………………………………………………………… 59  

Microchip Devices Code Protection Feature……………………………………………………….. 59  

Legal Notice…………………………………………………………………………………………………….60  

Trademarks……………………………………………………………………………………………………. 60  

Quality Management System Certified by DNV…………………………………………………….61  

Worldwide Sales and Service…………………………………………………………………………….62  

DS70005356C-page 5  

Datasheet  

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SAM R34/R35  

Description  

1.  

Description  

The SAM R34/R35 devices are a series of ultra-low power microcontrollers equipped with a UHF  

transceiver. It uses the 32-bit ARM Cortex-M0+ processor at max. 48 MHz (2.46 CoreMark/MHz) and  

offers 256 KB of Flash and 40 KB of SRAM. Sophisticated power management technologies, such as  

power domain gating, SleepWalking, ultra-low power peripherals and more, allow for very low line-power  

consumptions.  

The UHF transceiver supports LoRa and FSK modulation schemes. The LoRa technology is optimized for  

long-range communication with minimal line-power demand. The transceiver can work from frequencies  

of 137 MHz to 1020 MHz. Maximum transmit power is +20 dBm without an external amplification.  

Operational frequency bands and power limits are defined by local regulations and the LoRa Alliance.  

LoRa network stack regional options insure compliance. FSK modulation is also supported for  

applications including IEEE 802.15.4g, WiSUN, and legacy proprietary networks.  

All devices have accurate low power external and internal oscillators. Different clock domains can be  

independently configured to run at different frequencies, enabling power-saving by running each  

peripheral at its optimal clock frequency, thus maintaining a high CPU frequency while reducing power  

consumption.  

The SAM R34/R35 devices have four software-selectable sleep modes: Idle, Standby, Backup and Off. In  

Idle mode, the CPU is stopped while all other functions may be kept running. In Standby mode, all clocks  

and functions are stopped except those selected to continue running. In this mode all RAMs and logic  

contents are retained. The device supports SleepWalking, which allows some peripherals to wake-up  

from sleep based on predefined conditions, thus allowing some internal operations like DMA transfer  

and/or the CPU to wake-up only when needed; for example, when a threshold is crossed or a result is  

ready. The event system supports synchronous and asynchronous events, allowing peripherals to  

receive, react to and send events even in Standby mode. Off mode is not advised, as high impedance on  

the internal SPI bus results in metastability.  

The SAM R34/R35 devices have two software-selectable performance levels (PL0 and PL2) allowing the  

user to scale the lowest core voltage level that supports the operating frequency.

T

o

f

urther minimize  

current consumption, specifically leakage dissipation, the devices utilize a power domain gating technique  

with retention to turn off some logic areas while keeping their logic state. This technique is fully handled in  

hardware.  

The Flash program memory can be reprogrammed in-system through the Serial Wire Debug (SWD)  

interface. The same interface can also be used for non-intrusive on-chip debugging of application code. A  

boot loader running in the device can use any communication interface to download and upgrade the  

application program in the Flash memory.  

The SAM R34/R35 devices are supported with a full suite of programs and system development tools,  

including C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation  

kits.  

DS70005356C-page 6  

Datasheet  

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SAM R34/R35  

Configuration Summary  

2.  

Configuration Summary  

Table 2-1.ꢀConfiguration Summary  

Parameter  

SAM R34  

SAM R35  

T

o

tal Pins  

64  

64  

27  

General Purpose I/O pins

 

27  

(GPIOs)  

Flash  

256 KB  

256 KB  

8 KB  

32 KB  

8 KB  

3

Flash RWW Section  

System SRAM  

Low Power SRAM  

8 KB  

32 KB  

8 KB  

3

Timer Counter (TC)  

Instances  

Waveform Output  

Channels per TC  

Instance  

2

2

Timer Counter for Control

 

3  

(TCC) Instances  

3

Waveform Output  

Channels per TCC  

4/2/2  

4/2/2  

USB Interface  

1

0

Serial Communication  

Interface (SERCOM)  

Instances  

5+1

(1)  

5+1

(1)  

Analog-to-Digital  

Converter (ADC)  

Channels  

8

2

8

2

Analog Comparators  

(AC)  

Real-Time Counter (RTC)

 

Yes  

Y

e

s  

RTC Alarms  

1

1

RTC Compare Values  

1 for 32-bit value or  

2 for 16-bit values  

1 for 32-bit value or  

2 for 16-bit values  

External Interrupt Lines  

15  

15  

Maximum CPU  

Frequency  

48 MHz  

48 MHz  

Package  

BGA  

BGA  

DS70005356C-page 7  

Datasheet  

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SAM R34/R35  

Configuration Summary  

………..continued  

Parameter  

SAM R34  

SAM R35  

External  

32.768 kHz Crystal  

External  

Oscillator (XOSC32K)  

Oscillators  

• 16

 

MHz crystal oscillator for TRX

 

• 16

 

MHz crystal oscillator for TRX  

(XOSCRF)  

(XOSCRF)  

• 0.4-32

 

MHz crystal oscillator  

(XOSC)  

• 0.4-32

 

MHz crystal oscillator  

(XOSC)  

• 32.768

 

kHz external oscillator  

(OSC32K)  

• 32.768

 

kHz external oscillator  

(OSC32K)  

• 32

 

kHz ultra-low power internal  

oscillator (OSCULP32K)  

• 32

 

kHz ultra-low power internal  

oscillator (OSCULP32K)  

• 8

 

MHz high-accuracy internal  

oscillator (OSC8M)  

• 8

 

MHz high-accuracy internal  

oscillator (OSC8M)  

• 48

 

MHz Digital Frequency  

Locked Loop (DFLL48M)  

• 48

 

MHz Digital Frequency  

Locked Loop (DFLL48M)  

• 96

 

MHz Fractional Digital  

• 96

 

MHz Fractional Digital  

Phased Locked Loop (FDPLL96)  

Phased Locked Loop (FDPLL96)  

Event System Channels

 

12  

12  

SW Debug Interface  

Y

e

s  

Y

e

s  

Y

e

s  

Y

e

s  

Watchdog Timer (WDT)  

1. SERCOM4

 

is internally connected to the Transceiver (TRX).  

DS70005356C-page 8  

Datasheet  

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SAM R34/R35  

Ordering Information for SAM R34/R35  

3.  

Ordering Information for SAM R34/R35  

Figure 3-1.ꢀSAM R34/R35 Ordering Information  

34  

J

18  

B

T-  

I /  

xxx  

ATSAMR  

Product Family  

SAMR = SoC Microcontroller with RF  

Product Series  

34 = Cortex M0+ CPU + DMA + USB + LoRa Transeiver  

35 = Cortex M0+ CPU + DMA + LoRa Transeiver  

Pin Count  

J = 64 Pins  

Flash Memory Density  

16 = 64 KB  

17 = 128 KB  

18 = 256 KB  

Device Variant  

B = Release to Production  

Package Carrier  

T =

T

a

pe and Reel  

T

e

mperature Rating  

I = – 40 to + 85

o

C  

Package Type  

7JX = 64 Ball 6×6 mm TFBGA  

3.1  

SAM R34/R35 Ordering Codes  

Table 3-1.ꢀSAM R34/R35 Ordering Codes  

Ordering Code  

Description  

ATSAMR34J16BT-I/7JX  

ATSAMR34J17BT-I/7JX  

LoRa SiP Transceiver USB 64K Flash 8K SRAM, 4KB LP SRAM, T&R  

LoRa SiP Transceiver USB 128K Flash 16K SRAM, 8KB LP SRAM,  

T&R  

ATSAMR34J18BT-I/7JX  

LoRa SiP Transceiver USB 256K Flash 32K SRAM, 8KB LP SRAM,  

T&R  

ATSAMR35J16BT-I/7JX  

ATSAMR35J17BT-I/7JX  

ATSAMR35J18BT-I/7JX  

LoRa SiP Transceiver 64K Flash 8K SRAM, 4KB LP SRAM, T&R  

LoRa SiP Transceiver 128K Flash 16K SRAM, 8KB LP SRAM, T&R  

LoRa SiP Transceiver 256K Flash 32K SRAM, 8KB LP SRAM, T&R  

Note:ꢀ

The device variant (last letter of the ordering number) is independent of the die revision.  

DS70005356C-page 9  

Datasheet  

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SAM R34/R35  

System Introduction  

4.  

System Introduction  

4.1  

SAM R34/R35 Pinout Details  

Figure 4-1.ꢀSAM R34/R35 Pin Placement  

1

2

3

4

5

6

7

8

A

B

C

D

E

RFI_HF  

RFO_HF  

VBAT_RF  

VR_PA  

GND_RF  

GND_RF  

VDDANA  

RXTX  

PA00  

GNDANA  

PB03  

PA01  

PB02  

VDDCORE  

GND  

VSW  

RESET*  

PA28  

VDDIN  

GND  

VDDIO2  

PA24  

PA05  

PA30  

PB23  

PA25  

PA04  

GND  

PA31  

GND  

PA23  

PA22  

GND_RF  

PA_BOOST  

RFO_LF  

RFI_LF  

GNDANA  

GND_RF  

GND_RF  

VR_ANA  

PA06  

PA27  

PB22  

PA17  

PA18  

PA19  

F

PA07  

PA08  

PA09  

PA13  

PA16  

PA14  

G

H

GND_RF  

VBAT_ANA  

VDDI01  

VR_DIG  

GND_RF  

GND_RF  

GND_RF  

XTA  

GND_RF  

XTB  

PA15  

VBAT_DIG  

4.2  

SiP Block Diagram  

The following figure illustrates the SAM R34/R35 System-in-Package (SiP) block diagram.  

DS70005356C-page 10  

Datasheet  

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SAM R34/R35  

System Introduction  

Figure 4-2.ꢀSystem Block Diagram with MCU and Transceiver  

IOBUS  

256/128/64KB  

NVM  

32/16/8KB  

RAM  

CORTEX-M0+  

PROCESSOR  

Fmax 48 MHz  

SWCLK  

SWDIO  

SERIAL  

WIRE  

NVM Controller  

Cache  

SRAM  

CONTROLLER  

DEVICE  

SERVICE  

UNIT  

M

S

S

S

M

DP  

HIGH SPEED  

BUS MATRIX  

USB FS  

DEVICE  

MINI-HOST  

DM  

SOF 1KHZ  

S

(SAMR34 ONLY)  

M

S

8/8/4KB  

RAM  

AHB-APB  

BRIDGE B  

S

S

M

LP SRAM  

CONTROLLER  

S

LOW POWER  

BUS MATRIX  

PERIPHERAL  

ACCESS  

M

DMA  

CONTROLLER  

S

S

S

EVENT  

AHB-APB  

BRIDGE E  

AHB-APB  

BRIDGE A  

AHB-APB  

BRIDGE D  

AHB-APB  

BRIDGE C  

PAD0  

PAD1  

DMA  

DMA  

PAD2  

PAD3  

5 x SERCOM  

6 x SERCOM  

MAIN CLOCKS  

CONTROLLER  

WO0  

WO1  

4 x TIMER / COUNTER  

8 x Timer Counter  

EVENT  

OSCILLATORS CONTROLLER  

OSC16M  

WO0  

WO1  

(2)  

WOn  

DMA  

3x TIMER / COUNTER  

FOR CONTROL  

DFLL48M  

EVENT  

XIN  

XOSC  

XOUT  

FDPLL96M  

DMA  

AES  

DMA  

GENERIC CLOCK  

GCLK_IO[7..0]  

TRNG  

CONTROLLER  

WATCHDOG  

TIMER  

POWER  

MANAGER  

OSC32K CONTROLLER  

XIN32  

XOUT32  

WO0  

WO1  

DMA  

XOSC32K  

OSCULP32K  

OSC32K  

TIMER / COUNTER  

AIN[19..0]  

DMA  

8-CHANNEL  

12-bit ADC 1MSPS  

VREFA  

VREFB  

SUPPLY CONTROLLER  

EVENT  

BOD33  

VREF  

VREG  

AIN[3..0]  

2 ANALOG  

X[15..0]  

Y[15..0]  

PERIPHERAL  

TOUCH  

CONTROLLER  

RESET  

EXTWAKEx  

RESET  

CONTROLLER  

EVENT  

IN[2..0]  

OUT  

REAL TIME  

COUNTER  

3 x CCL  

EVENT  

EVENT  

PAD0  

PAD1  

EXTINT[15..0]  

NMI  

EXTERNAL INTERRUPT  

CONTROLLER  

SERCOM  

PAD2  

PAD3  

DIO(0…5)  

SERCOM4  

CONFIGURATION REGISTERS AND FIFO  

DEMOD  

MODULATOR  

LoRa/FSK/OOK  

LoRa/FSK/OOK  

ADC  

MUX  

i

Q

HIGH BAND  

FRAC-N PLL  

OSC  

RF  

LOW BAND  

FRAC-N PLL  

PA  

HF  

PA  

HP  

PA  

HF  

4.3  

Peripheral Key Table  

The following table lists all the peripherals supported in SAM R34 and SAM R35. Also, provides the  

references to relevant sections for detailed information.  

DS70005356C-page 11  

Datasheet  

©

2019 Microchip

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chnology Inc.  

SAM R34/R35  

System Introduction  

Note:ꢀ

The peripherals that are not listed in the following table must not be used.  

Table 4-1.ꢀPeripheral Key Table  

Peripheral  

Description  

Reference  

Document  

Topic # and Keyword  

Notes  

AC  

Analog Comparator  

1

1

43. AC – Analog Comparators  

ADC  

Analog-to-Digital  

Converter  

42. ADC – Analog-to-Digital  

Converter  

AES  

Advanced Encryption  

Engine  

1

38. AES – Advanced Encryption  

Standard  

BOD33  

CCL  

Brown-out Detector  

1

1

23. SUPC – Supply Controller  

Configurable Custom  

Logic  

40. CCL – Configurable Custom  

Logic  

CRC  

DMA  

EIC  

Cyclic Redundancy  

Check-sum  

1

1

1

15.11.3 32-bit Cyclic  

Redundancy Check CRC32  

Direct Memory Access  

Controller  

26. DMAC – Direct Memory  

Access Controller  

External Interrupt  

27. EIC – External Interrupt  

Controller  

EVSYS  

GCLK  

Event System  

1

1

30. EVSYS – Event System  

Generic Clock Control  

17. GCLK – Generic Clock  

Controller  

I2C  

Inter-integrated Circuit  

Interface  

1

34. SERCOM I2C – SERCOM  

Inter-integrated Circuit  

Peripheral function F-  

SERCOM4 pins  

(PB30, PB31, PC18,  

PC19) are internally  

connected to  

Transceiver. For  

details, refer to

10.  

Microcontroller  

Interface

.  

MCLK  

Main Clock Control  

1

1

18. MCLK – Main Clock  

NVMCTRL  

Nonvolatile Memory  

Controller  

28. NVMCTRL – Nonvolatile  

Memory Controller  

OSC32KCTRL 32

 

kHz Clock  

1

1

22. OSC32KCTRL – 32KHz  

Oscillators Controller  

OSCCTRL  

Clock Control  

21. OSCCTRL – Oscillators  

Controller  

PA_BOOST  

PM  

RF Output High-power  

Power Management  

GPIO Port Controller  

Power-On Reset  

5

1

1

1

5.4.2. RF Power Amplifiers  

20. PM – Power Manager  

29. PORT – I/O Pin Controller  

23. SUPC – Supply Controller  

PORT  

Limited to 27 ports  

PORT  

DS70005356C-page 12  

Datasheet  

©

2019 Microchip

T

e

chnology Inc.  

SAM R34/R35  

System Introduction  

………..continued  

Peripheral  

Description  

Reference  

Document  

Topic # and Keyword  

Notes  

PTC  

Peripheral

T

o

uch  

Controller (RC)  

1

45. PTC – Peripheral

T

o

uch  

Controller  

RFI_HF  

RF Input High  

Frequency  

5

5.5. Receiver Description  

RFI_LF  

RF Input Low Frequency

 

5  

5.5. Receiver Description  

5.4.2. RF Power Amplifiers  

RFO_HF  

RF Output High  

Frequency  

5

RFO_LF  

RF Output Low  

Frequency  

5

5.4.2. RF Power Amplifiers  

RSTC  

RTC  

SPI  

Reset Control  

1

1

1

19. RSTC – Reset Controller  

Real-Time Counter  

25. RTC – Real-Time Counter  

Serial Peripheral  

Interface  

33. SERCOM SPI – SERCOM  

Serial Peripheral Interface  

Peripheral function F-  

SERCOM4 pins  

(PB30, PB31, PC18,  

PC19) are internally  

connected to  

Transceiver. For  

details, refer to

10.  

Microcontroller  

Interface

.  

TC  

Timer Counter  

1

1

35. TC – Timer/Counter  

TCC  

Timer Counter for  

Control  

36. TCC – Timer/Counter for  

Control Applications  

TRNG  

Random Number  

Generator  

1

1

37. TRNG – True Random  

Number Generator  

USART  

Universal Synchronous  

and Asynchronous  

Receiver/Transmitter  

32. SERCOM USART –  

SERCOM Universal  

Synchronous and  

Peripheral function F-  

SERCOM4 pins  

(PB30, PB31, PC18,  

PC19) are internally  

connected to  

Asynchronous Receiver and  

Transmitter  

Transceiver.  

USB  

Full-speed Universal  

1

39. USB – Universal Serial Bus

 

SAMR34 Only. For  

Serial Bus 2.0 interface  

details, refer to

10.  

Microcontroller  

Interface

.  

VBAT  

WDT  

External Battery Input  

Watchdog Timer  

RF Oscillator  

1

1

5

23. SUPC – Supply Controller  

24. WDT – Watchdog Timer  

5.3. Frequency Synthesis  

XTA/B  

Note:ꢀ

For more details on the peripherals supported by the SAM R34, refer to

T

a

ble 5-1

.  

DS70005356C-page 13  

Datasheet  

©

2019 Microchip

T

e

chnology Inc.  

SAM R34/R35  

I/O Multiplexing and Considerations  

5.  

I/O Multiplexing and Considerations  

5.1  

Multiplexed Signals  

By default, each pin is controlled by the PORT as a general purpose I/O and alternatively may be  

assigned to one of the peripheral functions A, B, C, D, E,

F

,

G

, H or I.

T

o

e

nable a peripheral function on a  

pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin  

(PINCFGn.PMUXEN, n = 0..31) in the PORT must be written to ‘1’. The selection of peripheral functions  

A to H are done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing  

register (PMUXn.PMUXE/O) in the POR

T

.  

Table 5-1.ꢀPort Function Multiplexing  

(1)(2)  

SAM  

I/O Pin

 

Supply  

A

B

C

D

E

F

G

H

I

R34/R35  

Pin  

(1)(2)  

EIC  

RSTC  

REF  

ADC  

AC  

PTC X-

 

PTC Y-

 

SERCOM  

SERCOM- ALT  

TC/TCC  

TCC  

COM  

AC/GCLK/  

SUPC  

CCL  

lines  

lines  

A3  

A4  

D3  

C4  

E3  

F3  

F4  

F5  

F6  

F8  

G8  

F7  

E6  

E7  

E8  

D8  

D7  

B8  

C8  

E5  

C7  

PA00  

PA01  

PA04  

PA05  

PA06  

PA07  

PA08  

PA09  

PA13  

PA14  

PA15  

PA16  

PA17  

PA18  

PA19  

PA22  

PA23  

PA24  

PA25  

PB22  

PB23  

VSWOUT EXTINT[0]  

VSWOUT EXTINT[1]  

EXTWAKE[0]  

EXTWAKE[1]  

–

–

–

–

–

–

–

–

–

–

–

–

–

SERCOM1/  

PAD[0]  

TCC2/WO[0]  

TCC2/WO[1]  

TCC0/WO[0]  

TCC0/WO[1]  

TCC1/WO[0]  

TCC1/WO[1]  

–

–

–

–

–

–

–

–

–

–

–

–

SERCOM1/  

PAD[1]  

–

–

–

VDDANA  

VDDANA  

VDDANA  

VDDANA  

VDDIO  

VDDIO  

VDDIO  

VDDIO  

VDDIO  

VDDIO  

VDDIO  

VDDIO  

VDDIO  

VDDIO  

VDDIO  

VDDIO  

VDDIO  

VDDIN  

VDDIN  

EXTINT[4]  

EXTINT[5]  

EXTINT[6]  

EXTINT[7]  

NMI  

EXTWAKE[4] VREFB AIN[4]  

AIN[0]  

AIN[1]  

AIN[2]  

AIN[3]  

–

–

–

SERCOM0/  

PAD[0]  

–

–

CCL0/ IN[0]  

CCL0/ IN[1]  

CCL0/ IN[2]  

EXTWAKE[5]  

–

AIN[5]  

AIN[6]  

AIN[7]  

AIN[16]  

AIN[17]  

—

–

–

SERCOM0/  

PAD[1]  

–

–

EXTWAKE[6]  

–

–

Y[4]  

–

SERCOM0/  

PAD[2]  

–

–

EXTWAKE[7]  

–

–

SERCOM0/  

PAD[3]  

–

–

CCL0/  

OUT[0]  

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

–

X[0]  

X[1]  

—

Y[6]  

Y[7]  

—

—

—

—

—

—

—

—

—

—

—

—

—

SERCOM0/  

PAD[0]  

SERCOM2/  

PAD[0]  

TCC0/WO[0] TCC1/  

WO[2]  

–

–

CCL1/ IN[3]  

CCL1/ IN[1]  

—

EXTINT[9]  

EXTINT[13]  

EXTINT[14]  

EXTINT[15]  

EXTINT[0]  

EXTINT[1]  

EXTINT[2]  

EXTINT[3]  

EXTINT[6]  

EXTINT[7]  

EXTINT[12]  

EXTINT[13]  

EXTINT[6]  

EXTINT[7]  

—

—

—

—

—

—

—

—

—

—

—

—

—

—

SERCOM0/  

PAD[1]  

SERCOM2/  

PAD[1]  

TCC0/WO[1] TCC1/  

WO[3]  

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

SERCOM2/  

PAD[1]  

SERCOM4/  

PAD[1]  

TCC2/WO[1] TCC0/  

WO[7]  

AC/CMP[1]  

GCLK_IO[0]  

GCLK_IO[1]  

GCLK_IO[2]  

GCLK_IO[3]  

AC/CMP[0]  

AC/CMP[1]  

GCLK_IO[6]  

GCLK_IO[7]  

—

—

—

SERCOM2/  

PAD[2]  

SERCOM4/  

PAD[2]  

TC4/ WO[0]  

TC4/ WO[1]  

TCC0/  

WO[4]  

—

—

—

SERCOM2/  

PAD[3]  

SERCOM4/  

PAD[3]  

TCC0/  

WO[5]  

—

—

X[4]  

X[5]  

X[6]  

X[7]  

X[10]  

X[11]  

—

SERCOM1/  

PAD[0]  

SERCOM3/  

PAD[0]  

TCC2/WO[0] TCC0/  

WO[6]  

CCL0/ IN[0]  

CCL0/ IN[1]  

CCL0/ IN[2]  

—

SERCOM1/  

PAD[1]  

SERCOM3/  

PAD[1]  

TCC2/WO[1] TCC0/  

WO[1]  

—

SERCOM1/  

PAD[2]  

SERCOM3/  

PAD[2]  

TC4/ WO[0]  

TC4/ WO[1]  

TC0/ WO[0]  

TC0/ WO[1]  

TC1/ WO[0]  

TC1/ WO[1]  

TC3/ WO[0]  

TC3/ WO[1]  

TCC0/  

WO[2]  

—

SERCOM1/  

PAD[3]  

SERCOM3/  

PAD[3]  

TCC0/  

WO[3]  

CCL0/  

OUT[0]  

—

SERCOM3/  

PAD[0]  

SERCOM5/  

PAD[0]  

TCC0/  

WO[4]  

CCL2/ IN[0]  

CCL2/ IN[1]  

CCL2/ IN[2]  

—

SERCOM3/  

PAD[1]  

SERCOM5/  

PAD[1]  

TCC0/  

WO[5]  

USB/SOF 1  

kHz[6]  

—

SERCOM3/  

PAD[2]  

SERCOM5/  

PAD[2]  

TCC1/  

WO[2]  

USB/ DM[6]  

—

—

SERCOM3/  

PAD[3]  

SERCOM5/  

PAD[3]  

TCC1/  

WO[3]  

USB/ DP[6]  

—

CCL2/  

OUT[2]  

—

—

—

—

SERCOM5/  

PAD[2]  

—

—

—

—

GCLK_IO[0]  

GCLK_IO[1]  

CCL0/ IN[0]  

—

—

SERCOM5/  

PAD[3]  

CCL0/  

OUT[0]  

E4  

C6  

PA27  

PA28  

VDDIN  

VDDIN  

EXTINT[15]  

EXTINT[8]  

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

GCLK_IO[0]  

GCLK_IO[0]  

—

—

DS70005356C-page 14  

Datasheet  

©

2019 Microchip

T

e

chnology Inc.  

SAM R34/R35  

I/O Multiplexing and Considerations  

………..continued  

(1)(2)  

SAM  

I/O Pin

 

Supply  

A

B

C

D

E

F

G

H

I

R34/R35  

Pin  

(1)(2)  

EIC  

RSTC  

REF  

ADC  

AC  

PTC X-

 

PTC Y-

 

SERCOM  

SERCOM- ALT  

TC/TCC  

TCC  

COM  

AC/GCLK/  

SUPC  

CCL  

lines  

lines  

C5  

D5  

B4  

C3  

PA30  

PA31  

PB02  

PB03  

VDDIN  

VDDIN  

EXTINT[10]  

EXTINT[11]  

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

SERCOM1/  

PAD[2]  

TCC1/WO[0]  

TCC1/WO[1]  

TC2/ WO[0]  

TC2/ WO[1]  

—

—

—

—

SWCLK  

GCLK_IO[0]  

—

CCL1/ IN[0]  

(3)  

—

—

—

—

—

—

—

SERCOM1/  

PAD[3]  

SWDIO  

—

CCL1/  

OUT[1]  

VSWOUT EXTINT[2]  

VSWOUT EXTINT[3]  

AIN[10]  

AIN[11]  

SERCOM5/  

PAD[0]  

SUPC/ OUT[1]  

SUPC/VBAT  

CCL0/  

OUT[0]  

SERCOM5/  

PAD[1]  

—

1. All

 

analog pin functions are on peripheral function B. Peripheral function B must be selected to  

disable the digital control of the pin.  

2. Only

 

some pins can be used in SERCOM I2C mode. See

5.3.3 SERCOM

 

I2C Pins

.  

3. This

 

function is only activated in the presence of a debugger.  

4. When

 

an analog peripheral is enabled, the analog output of the peripheral interferes with the  

alternative functions of this pin. This is also true even when the peripheral is used for internal  

purposes.  

5. Clusters

 

of multiple GPIO pins are sharing the same supply pin. See

5.3.4 GPIO

 

Cluster

.  

6. USB

 

is not available on the SAM R35 devices.  

5.2  

Internal Multiplexed Signals  

By default, each pin is controlled by the PORT as a general purpose I/O and alternatively may be  

assigned to one of the peripheral functions A, B, C, D, E,

F

,

G

, H or I.

T

o

e

nable a peripheral function on a  

pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin  

(PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to ‘1’. The selection of peripheral functions A  

to H are done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing  

register (PMUXn.PMUXE/O) in the POR

T

.  

Table 5-2.ꢀInternal Multiplexed Signals  

Internal  

Signal  

I/O Pin

 

Supply  

Type  

A

B

C

D

E

F

G

H

I

EIC  

RSTC REF ADC  

AC PTC  

X-  

PTC  

SERCOM  

SERCOM-  

ALT  

TC/TCC TCC/  

SERCOM  

COM AC/GCLK/  

SUPC  

CCL  

Y-  

lines  

lines  

DIO0  

PB16  

PA11  

PA12  

PB17  

PA10  

PB00  

PB15  

PB30  

PB31  

PC18  

VDDIO  

VDDIO  

VDDIO  

VDDIO  

VDDIO  

I/O  

I/O  

I/O  

I/O  

I/O  

EXTINT[0]  

EXTINT[11]  

EXTINT[12]  

EXTINT[1]  

EXTINT[10]  

EXTINT[0]  

EXTINT[15]  

EXTINT[14]  

EXTINT[15]  

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

SERCOM5/  

PAD[0]  

–

TCC2/  

WO[0]  

TCC0/ WO[4]  

TCC0/ WO[3]  

TCC0/ WO[6]  

TCC0/ WO[5]  

TCC0/ WO[2]  

–

–

–

–

–

–

–

–

–

–

–

GCLK_IO[2]  

GCLK_IO[5]  

AC/CMP[0]  

GCLK_IO[3]  

GCLK_IO[4]  

SUPC_PSOK  

GCLK_IO[1]  

–

CCL3/  

IN[11]  

DIO1/  

DCLK  

AIN[19]  

X[3]  

Y[9]  

SERCOM0/  

PAD[3]  

SERCOM2/  

PAD[3]  

TCC1/  

WO[1]  

CCL1/  

OUT[1]  

DIO2/  

DATA  

–

–

–

SERCOM2/  

PAD[0]  

SERCOM4/  

PAD[0]  

TCC2/  

WO[0]  

–

DIO3  

DIO4  

DIO5  

RF_RST  

MOSI  

SEL  

–

–

–

SERCOM5/  

PAD[1]  

–

TCC2/  

WO[1]  

CCL3/  

OUT[3]  

AIN[18]  

X[2]  

Y[8]  

SERCOM0/  

PAD[2]  

SERCOM2/  

PAD[2]  

TCC1/  

WO[0]  

CCL1/  

IN[5]  

VDDANA I/O  

AIN[8]  

–

–

–

–

–

–

–

SERCOM5/  

PAD[2]  

TCC3/  

WO[0]  

CCL0/  

IN[1]  

VDDIO  

VDDIO  

VDDIO  

VDDIO  

I/O  

I/O  

I/O  

I/O  

–

–

–

–

X[15]  

SERCOM4/  

PAD[3]  

–

TCC0/  

WO[1]  

–

CCL3/  

IN[10]  

–

–

–

–

–

–

SERCOM5/  

PAD[0]  

TCC0/  

WO[0]  

SERCOM4/  

PAD[2]  

–

–

–

SERCOM5/  

PAD[1]  

TCC0/  

WO[1]  

SERCOM4/  

PAD[1]  

–

SCLK  

–

–

SERCOM4/  

PAD[3]  

–

DS70005356C-page 15  

Datasheet  

©

2019 Microchip

T

e

chnology Inc.  

SAM R34/R35  

I/O Multiplexing and Considerations  

………..continued  

Internal  

Signal  

I/O Pin

 

Supply  

Type  

A

B

C

D

E

F

G

H

I

EIC  

RSTC REF ADC  

AC PTC  

X-  

PTC  

SERCOM  

SERCOM-  

ALT  

TC/TCC TCC/  

SERCOM  

COM AC/GCLK/  

SUPC  

CCL  

Y-  

lines  

lines  

MISO  

PC19  

VDDIO  

I/O  

–

–

–

–

–

–

–

–

–

–

SERCOM4/  

PAD[0]  

–

–

–

5.3  

Other Functions  

5.3.1  

Oscillator Pinout  

The oscillators are not mapped to the normal PORT functions, and their multiplexing is controlled by  

registers in the Oscillator Controller (OSCCTROL) and in the 32kHz Oscillators Controller  

(OSC32KCTRL).  

Table 5-3.ꢀOscillator Pinout  

Oscillator  

Supply  

Signal  

XIN  

I/O Port  

PA14  

XOSC  

VDDIO  

XOUT  

XIN32  

XOUT32  

PA15  

XOSC32K  

VSWOUT  

PA00  

PA01  

5.3.2  

Serial Wire Debug Interface Pins  

Only the SWCLK pin is mapped to the normal PORT functions. A debugger cold-plugging or hot-plugging  

detection will automatically switch the SWDIO port to the SWDIO function.  

Table 5-4.ꢀSerial Wire Debug Interface Pinout  

Signal  

Supply  

VDDIN  

VDDIN  

I/O Pin  

PA30  

SWCLK  

SWDIO  

PA31  

5.3.3  

SERCOM I

2

C Pins  

Table 5-5.ꢀSERCOM Pins Supporting I

2

C  

Device  

Pins Supporting I

2

C HS Mode  

SAM R34/R35  

PA08, PA09, PA13, PA16, PA17, PA22, PA23  

DS70005356C-page 16  

Datasheet  

©

2019 Microchip

T

e

chnology Inc.  

SAM R34/R35  

I/O Multiplexing and Considerations  

5.3.4  

GPIO Cluster  

Table 5-6.ꢀGPIO Clusters  

Package Cluster GPIO  

Supply Pins Connected to  

the Cluster  

64 Pins  

1

2

PA31 PA30  

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

VDDIN C4/GND D4  

PA28 PA27 PB23 PB22  

VDDIN C4/GND D4 and  

VDDIO C6/GND C5  

3

PA25 PA24 PA23 PA22  

–

–

PA19 PA18 PA17 PA16 PA15 PA14 PA13 VDDIO

 

C6/GND C5 and  

VDDIO F3/GND F4  

4

5

6

–

–

PA09 PA08  

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

VDDIO F3/GND F4  

PA07 PA06 PA05 PA04  

VDDANA C1/GNDANA C3  

VDDANA C1/GNDANA C3  

–

–

PA01 PA00 PB03 PB02  

5.3.5  

TCC Configurations  

The SAML21 has three instances of the Timer/Counter for Control applications (TCC) peripheral,  

TCC<2:0>.  

Table 5-7.ꢀTCC Configuration Summary  

TCC Channels

 

Waveform Counter

 

Fault Dithering Output

 

Dead  

SWAP Pattern  

Generation  

No. (CC_NUM)

 

Output  

(WO_NUM)  

Size  

Matrix Time  

Insertion  

(DTI)  

Y

e

s  

—

0

1

2

4

2

2

8

24-bit  

24-bit  

16-bit  

Y

e

s

Y

e

s  

Y

e

s

Y

e

s  

Y

e

s  

Y

e

s  

—

Y

e

s  

—

Y

e

s  

4

2

Y

e

s  

—

—

—

—

Note:ꢀ

The number of CC register (CC_NUM)_ for each TCC corresponds to the number of compare/  

capture channels to ensure that a TCC can have more Waveform Outputs (WO_NUM) than CC registers.  

DS70005356C-page 17  

Datasheet  

©

2019 Microchip

T

e

chnology Inc.  

SAM R34/R35  

Signal Description  

6.  

Signal Description  

This section provides the required information to understand the origin and the function of each such  

signal. The nature of a SIP results in the situation where the package pins may be bonded to the  

microcontroller die or the transceiver die. There are also signals bonded in-between the two dies.  

6.1  

Signal Details  

This section provides the naming and functional description of the internal and external signals.

5. I/O  

Multiplexing and Considerations

describes the routing of these signals between the MCU core and  

transceiver subsystem and to the external package pins.  

Table 6-1.ꢀSignal Descriptions List  

Signal Name  

Function  

Type  

Analog Comparators (AC)  

AIN<3:0>  

AC analog inputs  

AC comparator outputs  

Analog  

Digital  

CMP<1:0>  

Analog Digital Converter (ADC)  

AIN<19:0>  

VREFB  

ADC analog inputs  

Analog  

Analog  

ADC voltage external reference B  

External Interrupt Controller (EIC)  

EXTINT<15:0>  

NMI  

External interrupts inputs  

External non-maskable interrupt input  

Digital  

Digital  

Reset Controller (RSTC)  

EXTWAKE<7:0> External

 

wake-up inputs  

Generic Clock Generator (GCLK)  

Digital  

GCLK_IO<7:0> Generic

 

clock (source clock inputs or generic clock generator output)

 

Digital  

Custom Control Logic (CCL)  

IN<8:0>  

Logic inputs  

Digital  

Digital  

OUT<2:0>  

Logic outputs  

Supply Controller (SUPC)  

VBAT  

External battery supply inputs  

Analog  

Digital  

Digital  

PSOK  

Main power supply OK input  

Logic outputs  

OUT<1:0>  

Power Manager (PM)  

RESETN  

Active low Reset input  

Digital  

Serial Communication Interface (SERCOMx)  

DS70005356C-page 18  

Datasheet  

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chnology Inc.  

SAM R34/R35  

Signal Description  

………..continued  

Signal Name  

Function  

Type  

PAD<3:0>  

SERCOM Input/Output pads  

Digital  

Oscillators Control (OSCCTRL)  

XIN  

Crystal or external clock input  

Crystal output  

Analog/Digital  

Analog  

XOUT  

32KHz Oscillators Control (OSC32KCTRL)  

XIN32  

32KHz crystal or external clock input  

32KHz crystal output  

Analog/Digital  

Analog  

XOUT32  

Timer Counter (TCx)  

WO<1:0>  

Waveform outputs  

Digital  

Digital  

Timer Counter (TCCx)  

WO<7:0>  

Waveform outputs  

General Purpose I/O (PORT)  

PA01-PA00  

PA09-PA04  

PA25-PA22  

PA28-PA27  

PA03-PB02  

PA23-PB22  

Parallel I/O controller I/O Port A  

Digital  

Digital  

Digital  

Digital  

Digital  

Digital  

Parallel I/O controller I/O Port A  

Parallel I/O controller I/O Port A  

Parallel I/O controller I/O Port A  

Parallel I/O controller I/O Port B  

Parallel I/O controller I/O Port B  

Universal Serial Bus (USB)  

DP  

DP for USB (SAM R34 only)  

DM for USB (SAM R34 only)  

Digital  

Digital  

DM  

External RF Signals  

RF_XTB  

RF_XTA  

VR_DIG  

VBAT_ANA  

VR_ANA  

RFI_LF  

XTAL connection  

OSC  

XTAL connection or TCXO input  

OSC  

Regulated supply voltage for digital blocks  

Supply voltage for analog circuitry  

Regulated supply voltage for analog circuitry  

RF input for bands 2 and 3  

Reg Output  

Analog Power  

Reg Output  

RF Input  

RFO_LF  

PA_BOOST  

VR_PA  

RF output for bands 2 and 3  

RF Output  

RF Output  

Reg Output  

Optional high-power PA output, all frequency bands  

Regulated supply voltage for the PA  

DS70005356C-page 19  

Datasheet  

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chnology Inc.  

SAM R34/R35  

Signal Description  

………..continued  

Signal Name  

Function  

Type  

VBAT_RF  

RFO_HF  

VBAT_DIG  

RXTX  

Supply voltage for RF blocks  

RF output for band 1  

RF Power  

RF Output  

Digital Power  

Digital I/O  

RF Input  

Supply voltage for digital blocks  

RX/TX switch control: High in TX  

RF input for band 1  

RFI_HF  

Internal Interconnect Signals  

DIO0  

Digital I/O, software configured  

I/O  

DIO1/DCLK  

DIO2/DATA  

DIO3  

Digital I/O, software configured  

Digital I/O, software configured  

Digital I/O, software configured  

Digital I/O, software configured  

Digital I/O, software configured  

SPI clock input  

I/O  

I/O  

I/O  

DIO4  

I/O  

DIO5  

I/O  

SCLK  

Input  

Output  

Input  

Input  

I/O  

MISO  

SPI data output  

MOSI  

SPI data input  

SEL  

SPI chip select input  

RF_RST  

Reset trigger input  

DS70005356C-page 20  

Datasheet  

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chnology Inc.  

SAM R34/R35  

Processor and Architecture  

7.  

Processor and Architecture  

7.1  

Cortex M0+ Processor  

The SAM R34/R35 contains an ATSAML21 Die Revision C ARM Cortex-M0+ processor. The processor is  

®

based on the ARMv6 Architecture and Thumb

 

-2 ISA. The Cortex-M0+ is 100% instruction set  

compatible with its predecessor, the Cortex-M0 core, and upward compatible to Cortex-M3 and M4 cores.  

The implemented ARM Cortex-M0+ is revision r0p1. For more information, refer to

.  

7.1.1  

Cortex M0+ Configuration  

Table 7-1.ꢀCortex M0+ Configuration in SAM R34/R35  

Features  

Cortex M0+ options  

External interrupts 0-32  

Little-endian or big-endian  

Present or absent  

0, 1, 2  

SAM R34/R35 configuration  

Interrupts  

29  

Data endianness  

SysTick timer  

Little-endian  

Present  

2

Number of watchpoint  

comparators  

Number of breakpoint  

comparators  

0, 1, 2, 3, 4  

4

Halting debug support  

Multiplier  

Present or absent  

Fast or small  

Present  

Fast (single cycle)  

Present  

Single-cycle I/O port  

Present or absent  

Supported or not supported  

Present or absent  

Present or absent  

Wake-up interrupt controller  

Vector

T

a

ble Offset Register  

Unprivileged/Privileged support  

Not supported  

Present  

Absent – All software run in  

privileged mode only  

Memory Protection Unit  

Reset all registers  

Not present or 8-region  

Present or absent  

Not present  

Absent  

Instruction fetch width  

16-bit only or mostly 32-bit  

32-bit  

The ARM Cortex-M0+ core has two bus interfaces:  

• Single

 

32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all  

system memory including Flash memory and RAM  

• Single

 

32-bit I/O port bus interfacing to the PORT with 1-cycle loads and stores  

7.1.1.1 Cortex

 

M0+ Peripherals  

• System

 

Control Space (SCS)  

– The

 

processor provides debug through registers in the SCS. Refer to the Cortex-M0+

T

e

chnical  

Reference Manual for details (

)  

• Nested

 

Vectored Interrupt Controller (NVIC)  

DS70005356C-page 21  

Datasheet  

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SAM R34/R35  

Processor and Architecture  

– External

 

interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software  

can set the priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely  

coupled, providing low latency interrupt processing and efficient processing of late arriving  

interrupts. Refer to the Cortex-M0+

T

e

chnical Reference Manual for details (

).  

Note:ꢀ

When the CPU frequency is much higher than the APB frequency it is recommended to  

insert a memory read barrier after each CPU write to registers mapped on the APB. Failing to do  

so in such conditions may lead to unexpected behavior such as re-entering a peripheral interrupt  

handler just after leaving it.  

• System

 

Timer (SysTick)  

– The

 

System Timer is a 24-bit timer clocked by CLK_CPU that extends the functionality of both  

the processor and the NVIC. Refer to the Cortex-M0+

T

e

chnical Reference Manual for details  

(

).  

• System

 

Control Block (SCB)  

– The

 

System Control Block provides system implementation information, and system control. This  

includes configuration, control, and reporting of the system exceptions. Refer to the Cortex-M0+  

Devices Generic User Guide for details (

)  

• Micro

 

Trace Buffer (MTB)  

– The

 

CoreSight MTB-M0+ (MTB) provides a simple execution trace capability to the Cortex-M0+  

processor. Refer to section

MTB-Micro Trace Buffer

and the CoreSight MTB-M0+

T

e

chnical  

Reference Manual for details (

).  

Related Links  

7.2 Nested

 

Vector Interrupt Controller  

7.1.1.2 Cortex

 

M0+ Address Map  

Table 7-2.ꢀCortex-M0+ Address Map  

Address  

Peripheral  

0xE000E000  

System Control Space (SCS)  

System Timer (SysTick)  

0xE000E010  

0xE000E100  

Nested Vectored Interrupt Controller (NVIC)  

System Control Block (SCB)  

Micro Trace Buffer (MTB)  

0xE000ED00  

0x41006000  

7.1.1.3 I/O

 

Interface  

™

®

The device allows direct access to PORT registers. Accesses to the AMBA

 

AHB-Lite and

 

the single  

cycle I/O interface can be made concurrently, so the Cortex M0+ processor can fetch the next instructions  

while accessing the I/Os. This enables single cycle I/O access to be sustained for as long as necessary.  

7.2  

Nested Vector Interrupt Controller  

7.2.1  

Overview  

The Nested Vectored Interrupt Controller (NVIC) in the SAM R34/R35 supports 32 interrupt lines with four  

different priority levels. For more details, refer to the Cortex-M0+

T

e

chnical Reference Manual (

).  

DS70005356C-page 22  

Datasheet  

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chnology Inc.  

SAM R34/R35  

Processor and Architecture  

7.2.2  

Interrupt Line Mapping  

Each of the 23 interrupt lines is connected to one peripheral instance, as shown in the table below. Each  

peripheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear  

(INTFLAG) register.  

An interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be  

individually enabled by writing a 1 to the corresponding bit in the peripheral’s Interrupt Enable Set  

(INTENSET) register, and disabled by writing 1 to the corresponding bit in the peripheral’s Interrupt  

Enable Clear (INTENCLR) register.  

An interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding  

interrupt is enabled.  

The interrupt requests for one peripheral are ORed together on system level, generating one interrupt  

request for each peripheral. An interrupt request will set the corresponding interrupt pending bit in the  

NVIC interrupt pending registers (SETPEND/CLRPEND bits in ISPR/ICPR).  

For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/  

CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for  

each interrupt.  

Table 7-3.ꢀInterrupt Line Mapping  

Peripheral Source  

NVIC Line  

EIC NMI – External Interrupt Controller  

PM – Power Manager  

NMI  

0

MCLK – Main Clock  

OSCCTRL – Oscillators Controller  

OSC32KCTRL – 32KHz Oscillators Controller  

SUPC – Supply Controller  

PAC – Protecion Access Controller  

WDT – Watchdog Timer  

1

RTC – Real Time Counter  

2

EIC – External Interrupt Controller  

3

NVMCTRL – Non-Volatile Memory Controller  

DMAC – Direct Memory Access Controller  

USB – Universal Serial Bus  

4

5

6

EVSYS – Event System  

7

SERCOM0 – Serial Communication Interface 0  

SERCOM1 – Serial Communication Interface 1  

SERCOM2 – Serial Communication Interface 2  

SERCOM3 – Serial Communication Interface 3  

SERCOM4 – Serial Communication Interface 4  

8

9

10  

11  

12  

DS70005356C-page 23  

Datasheet  

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SAM R34/R35  

Processor and Architecture  

………..continued  

Peripheral Source  

NVIC Line  

SERCOM5 – Serial Communication Interface 5  

TCC0 – Timer Counter for Control 0  

TCC1 – Timer Counter for Control 1  

TCC2 – Timer Counter for Control 2  

TC0 – Timer Counter 0  

13  

14  

15  

16  

17  

18  

19  

20  

21  

TC1 – Timer Counter 1  

TC4 – Timer Counter 4  

ADC – Analog-to-Digital Converter  

AC – Analog Comparator  

7.3  

Micro Trace Buffer  

7.3.1  

Features  

• Program

 

flow tracing for the Cortex-M0+ processor  

• MTB

 

SRAM can be used for both trace and general purpose storage by the processor  

• The

 

position and size of the trace buffer in SRAM is configurable by software  

• CoreSight

 

compliant  

7.3.2  

Overview  

When enabled, the MTB records the changes in program flow that are reported by the Cortex-M0+  

processor over the execution trace interface. This interface is shared between the Cortex-M0+ processor  

and the CoreSight MTB-M0+. The information is stored by the MTB in the SRAM as trace packets. An off-  

chip debugger can extract the trace information using the Debug Access Port to read the trace  

information from the SRAM. The debugger can then reconstruct the program flow from this information.  

The MTB stores trace information into the SRAM and gives the processor access to the SRAM  

simultaneously. The MTB ensures that trace write accesses have priority over processor accesses.  

An execution trace packet consists of a pair of 32-bit words that the MTB generates when it detects a  

non-sequential change of the program pounter (PC) value. A non-sequential PC change can occur during  

branch instructions or during exception entry. See the CoreSight MTB-M0+

T

e

chnical Reference Manual  

for more details on the MTB execution trace packet format.  

Tracing is enabled when the MASTER.EN bit in the Master Trace Control Register is 1. There are various  

ways to set the bit to 1 to start tracing, or to 0 to stop tracing. See the CoreSight Cortex-M0+

T

e

chnical  

Reference Manual for more details on the Trace start and stop and for a detailed description of the MTB’s  

MASTER register. The MTB can be programmed to stop tracing automatically when the memory fills to a  

specified watermark level or to start or stop tracing by writing directly to the MASTER.EN bit. If the  

watermark mechanism is not being used and the trace buffer overflows, then the buffer wraps around  

overwriting previous trace packets.  

The base address of the MTB registers is 0x41006000; this address is also written in the CoreSight ROM  

T

a

ble. The offset of each register from the base address is fixed and as defined by the CoreSight MTB-  

DS70005356C-page 24  

Datasheet  

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chnology Inc.  

SAM R34/R35  

Processor and Architecture  

M0+

T

e

chnical Reference Manual. The MTB has four programmable registers to control the behavior of  

the trace features:  

• POSITION:

 

Contains the trace write pointer and the wrap bit  

• MASTER:

 

Contains the main trace enable bit and other trace control fields  

• FLOW:

 

Contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits  

• BASE:

 

Indicates where the SRAM is located in the processor memory map. This register is provided  

to enable auto discovery of the MTB SRAM location by a debug agent  

See the CoreSight MTB-M0+

T

e

chnical Reference Manual for a detailed description of these registers.  

7.4  

High-Speed Bus System  

7.4.1  

Features  

High-Speed Bus Matrix has the following features:  

• Symmetric

 

crossbar bus switch implementation  

• Allows

 

concurrent accesses from different masters to different slaves  

• 32-bit

 

data bus  

• Operation

 

at a one-to-one clock frequency with the bus masters  

H2LBRIDGE has the following features:  

• LP

 

clock division support  

• Write:

 

Posted-write FIFO of 3 words, no bus stall until it is full  

• Write:

 

1 cycle bus stall when full when LP clock is not divided  

• 2

 

stall cycles on read when LP clock is not divided  

• Ultra-Low

 

Latency mode:  

– Suitable

 

when the HS clock frequency is not above half the maximum device clock frequency  

– Removes

 

all intrinsic bridge stall cycles (except those needed for LP clock ratio adaptation)  

– Enabled

 

by writing a ‘1’ in 0x41008120 using a 32-bit write access  

L2HBRIDGE has the following features:  

• LP

 

clock division support  

• Write:

 

Posted-write FIFO of 1 word, no bus stall until it is full  

• Write:

 

1 cycle bus stall when full when LP clock is not divided  

• 2

 

stall cycles on read when LP clock is not divided  

• Ultra-Low

 

Latency mode:  

– Suitable

 

when the HS clock frequency is not above half the maximum device clock frequency  

– Removes

 

all intrinsic bridge stall cycles (except those needed for LP clock ratio adaptation)  

– Enabled

 

by writing a ‘1’ in 0x41008120 using a 32-bit write access  

Figure 7-1.ꢀHigh-Speed Bus System Components  

M

M

S

M

M

M

S

H2LBRIDGEM  

L2HBRIDGES  

H2LBRIDGES  

L2HBRIDGES  

S

H2LBRIDGE  

L2HBRIDGE  

HMATRIXLP  

HMATRIXHS  

M

S

S

S

S S  

S

S S S S S S  

DS70005356C-page 25  

Datasheet  

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SAM R34/R35  

Processor and Architecture  

7.4.2  

Configuration  

Figure 7-2.ꢀMaster-Slave Relations High-Speed Bus Matrix  

High-Speed Bus SLAVES  

0

1

2

3

4

CM0+  

DSU  

0

1

2

L2HBRIDGEM  

Figure 7-3.ꢀMaster-Slave Relations Low-Power Bus Matrix  

Low-Power Bus SLAVES  

0

1

2

3

5

7

8

9

H2LBRIDGEM 0  

DMAC  

2

Table 7-4.ꢀHigh-Speed Bus Matrix Masters  

High-Speed Bus Matrix Masters  

CM0+ – Cortex M0+ Processor  

Master ID  

0

1

DSU – Device Service Unit  

DS70005356C-page 26  

Datasheet  

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SAM R34/R35  

Processor and Architecture  

………..continued  

High-Speed Bus Matrix Masters  

Master ID  

L2HBRIDGEM – Low-Power to High-Speed bus  

matrix AHB to AHB bridge  

2

Table 7-5.ꢀHigh-Speed Bus Matrix Slaves  

High-Speed Bus Matrix Slaves  

Internal Flash Memory  

Slave ID  

0

1

2

3

4

HS SRAM Port 0 – CM0+ Access  

HS SRAM Port 1 – DSU Access  

AHB-APB Bridge B  

H2LBRIDGES – High-Speed to Low-Power bus  

matrix AHB to AHB bridge  

Table 7-6.ꢀLow-Power Bus Matrix Masters  

Low-Power Bus Matrix Masters  

Master ID  

H2LBRIDGEM – High-Speed to Low-Power bus  

matrix AHB to AHB bridge  

0

DMAC – Direct Memory Access Controller – Data  

Access  

2

Table 7-7.ꢀLow-Power Bus Matrix Slaves  

Low-Power Bus Matrix Slaves  

AHB-APB Bridge A  

Slave ID  

0

1

2

3

5

7

8

AHB-APB Bridge C  

AHB-APB Bridge D  

AHB-APB Bridge E  

LP SRAM Port 2- H2LBRIDGEM access  

LP SRAM Port 1- DMAC access  

L2HBRIDGES – Low-Power to High-Speed bus  

matrix AHB to AHB bridge  

HS SRAM Port 2- HMATRIXLP access  

9

7.4.3  

SRAM Quality of Service  

To

e

nsure that masters with latency requirements get sufficient priority when accessing RAM, priority  

levels can be assigned to the masters for different types of access.  

The Quality of Service (QoS) level is independently selected for each master accessing the RAM. For any  

access to the RAM, the RAM also receives the QoS level. The QoS levels and their corresponding bit  

values for the QoS level configuration are shown in the following table.  

DS70005356C-page 27  

Datasheet  

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SAM R34/R35  

Processor and Architecture  

Table 7-8.ꢀQuality of Service  

Value  

Name  

Description  

0x0  

DISABLE  

Background (no sensitive  

operation)  

0x1  

0x2  

0x3  

LOW  

Sensitive Bandwidth  

Sensitive Latency  

Critical Latency  

MEDIUM  

HIGH  

If a master is configured with QoS level DISABLE (0x0) or LOW (0x1) there will be a minimum latency of  

one cycle for the RAM access.  

The priority order for concurrent accesses are decided by two factors. First, the QoS level for the master  

and second, a static priority given by the port ID. The lowest port ID has the highest static priority. See the  

tables below for details.  

The MTB has a fixed QoS level HIGH (0x3).  

The CPU QoS level can be written/read, using 32-bit access only, at address 0x41008114 bits [1:0]. Its  

reset value is 0x3.  

Refer to different master QOSCTRL registers for configuring QoS for the other masters (USB, DMAC).  

Table 7-9.ꢀHS SRAM Port Connections QoS  

HS SRAM Port Connection

 

Port ID

 

Connection Type

 

QoS  

default QoS  

MTB – Micro Trace Buffer  

USB – Universal Serial Bus  

4

3

2

Direct  

STATIC-3  

0x3  

0x3  

0x2  

Direct  

IP-QOSCTRL  

HMATRIXLP – Low-Power  

Bus Matrix  

Bus Matrix  

0x44000934

(1)

, bits[1:0]  

DSU – Device Service Unit  

1

0

Bus Matrix  

Bus Matrix  

0x4100201C

(1)  

0x2  

0x3  

CM0+ – Cortex M0+  

Processor  

0x41008114

(1)

, bits[1:0]  

Note:ꢀ  

1. Using

 

32-bit access only.  

Table 7-10.ꢀLP SRAM Port Connections QoS  

LP SRAM Port Connection

 

Port ID

 

Connection Type

 

QoS  

default QoS  

DMAC – Direct Memory  

Access Controller – Write-  

Back Access  

5, 6  

Direct  

IP-QOSCTRL.WRBQOS  

0x2  

DMAC – Direct Memory  

Access Controller – Fetch  

Access  

3, 4  

Direct  

IP-QOSCTRL.FQOS  

0x2  

DS70005356C-page 28  

Datasheet  

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SAM R34/R35  

Processor and Architecture  

………..continued  

LP SRAM Port Connection

 

Port ID

 

Connection Type

 

QoS  

default QoS  

H2LBRIDGEM – HS to LP  

bus matrix AHB to AHB  

bridge  

2

Bus Matrix  

0x44000924

(1)

, bits[1:0]  

0x2  

DMAC – Direct Memory  

Access Controller – Data  

Access  

1

Bus Matrix  

IP-QOSCTRL.DQOS  

0x2  

Note:ꢀ  

1. Using

 

32-bit access only.  

DS70005356C-page 29  

Datasheet  

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chnology Inc.  

SAM R34/R35  

Application Schematic Introduction  

8.  

Application Schematic Introduction  

The SAM R34/R35 application schematic has to provide the environment for both integrated circuits  

inside the package. The microcontroller as well as the radio have integrated LDOs to provide the required  

core voltages.

T

o

a

chieve the full radio performance, the application layout has to take the noise  

decoupling in-between the analog radio part and the digital processor and signal processing power  

domains into account.  

8.1  

SAM R34/R35 Basic Application Schematic  

The following application schematic shows the minimum circuit elements required for the SAM R34/R35  

system. In this schematic, both the high-power PA_BOOST and high-efficiency RFO_HF transmitter  

configurations are populated. Some applications may require only one transmitter configuration.  

For unused pins, the default state of the pins will give the lowest current leakage. Thus, there is no need  

to perform any configuration of the unused pins in order to lower the power consumption.  

DS70005356C-page 30  

Datasheet  

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Figure 8-1.ꢀSAM R34/R35 Basic Application Schematic

rotatethispage90  

VDD  

U300  

VDD  

G4  

A8  

A7  

C2  

H8  

H3  

C1  

VDDIO1  

VDDIO2  

VDDIN  

VBAT_DIG  

VBAT_ANA  

VBAT_RF  

VDDANA  

32 MHz TCXO  

VDDANA  

DNP  

VDDANA  

A6  

A5  

H4  

H2  

D1  

L301  

LQH3NPN100MJ0  

C303  

100nF  

C304  

100nF  

C307  

100nF  

C308  

100nF  

VSW  

VR_DIG  

VR_ANA  

VR_PA  

XTA  

VDDCORE  

C330  

33pF  

C311  

100nF  

C312  

100nF  

C313  

100nF  

C314  

100nF  

C340  

4.7pF  

C315  

100nF  

GND  

GND  

GND  

GND  

C316  

100nF  

B3  

E2  

B5  

B7  

D4  

D6  

A2  

B2  

E1  

F2  

G2  

G3  

G5  

G6  

G7  

H5  

C321  

DNF  

C300  

DNF  

GNDANA  

GNDANA  

GND  

GND  

GND  

GND_RF  

GND_RF  

GND_RF  

GND_RF  

GND_RF  

GND_RF  

GND_RF  

GND_RF  

GND_RF  

GND_RF  

VDD  

DNP  

GND  

DNP  

GND  

XC1  

TYETBCSANF-32.000000  

GND  

GND  

GND  

GND  

GND  

GND  

GND  

GND  

GND  

VR_PA  

B6  

RESET  

RESET  

GND  

A3  

A4  

D3  

C4  

E3  

F3  

F4  

F5  

F6  

F8  

G8  

F7  

E6  

E7  

E8  

D8  

D7  

B8  

C8  

E4  

C6  

C5  

D5  

B4  

C3  

E5  

C7  

PA00_XIN32  

PA01_XOUT32  

PA00  

PA01  

PA04  

PA05  

PA06  

PA07  

PA08  

PA09  

PA13  

PA14  

PA15  

PA16  

PA17  

PA18  

PA19  

PA22  

PA23  

PA24  

PA25  

PA27  

PA28  

PA30  

PA31  

PB02  

PB03  

PB22  

PB23  

PA04_S0_UART_TX  

PA05_S0_UART_RX  

50Ohm  

i

VDD  

L300  

BLM15AG121SN1D  

B1  

A1  

F1  

G1  

H1  

D2  

RFO_HF  

RFI_HF  

VDDANA  

RFSW_PWR  

RFO_HF  

RFI_HF  

PA_BOOST  

RFO_LF  

RFI_LF  

RXTX  

GND  

50Ohm  

i

C306  

10uF  

RFSW_PWR  

BAND_SEL  

C320  

100nF  

50Ohm  

i

PA_BOOST  

GND  

GND  

TXRX  

XTA  

32 kHz Crystal  

PA30_SWDCLK  

PA31_SWDIO  

Y301  

H6  

H7  

PA01_XOUT32  

PA00_XIN32  

XTA  

XTB  

ABS05-32.768KHZ-9-T  

C309  

C310  

10pF  

10pF  

SAMR34J18B  

ANTENNA  

SMA Antenna connector  

GND  

GND  

GND  

C904  

50Ohm  

DNP  

i

1

J901  

DNF  

50Ohm  

i

50Ohm  

i

50Ohm  

50Ohm  

i

50Ohm  

i

SM

A

E

dg

e

M

ount  

C900  

i

L900  

2.2nH  

L902  

L901  

10nH  

PA_BOOST  

Cortex Debug Connector  

10nH  

GND  

1

8

p

F  

C901  

3.9pF  

C917  

3.3pF  

C902  

5.6pF  

C903  

3.3pF  

L903  

33nH  

GND  

GND  

VDD  

J303  

1

3

5

7

9

2

4

6

8

GND  

VREF  

PA31_SWDIO  

PA30_SWDCLK  

GND  

GND  

GND  

U900  

SKY13373-460LF  

VR_PA  

50Ohm  

i

50Ohm  

i

50Ohm  

i

10  

C905  

RESET  

L904  

1

9

RFI_HF  

J1  

J2  

C906  

DNF  

C907  

4.7nF  

DNP  

HEADER 2×5  

1310-1205SNS073R1  

10nH  

GND  

2

8

L905  

33nH  

47pF  

GND  

GND  

GND  

C908  

2.7pF  

3

7

C909  

DNP  

DNF  

C915  

DNP  

DNF  

J3  

GND  

GND  

GND  

GND  

50Ohm  

i

50Ohm  

i

50Ohm  

C910  

50Ohm  

50Ohm  

50Ohm  

i

GND  

i

i

i

L906  

L907  

L909  

10nH  

RFO_HF  

V1 V2  

RF Switch State  

11nH  

10nH  

RFSW_PWR  

22pF  

0

1

0

1

0

0

1

1

Shutdown  

C911  

3.9pF  

C912  

8.2pF  

C913  

5.6pF  

C916  

3.3pF  

RFC to J2 (RFI_HF)  

RFC to J1 (PA_BOOST)  

RFC to J3 (RFO_HF)  

C914  

1 nF  

GND  

GND  

GND  

GND  

GND  

BAND_SEL  

TXRX  

SAM R34/R35  

Application Schematic Introduction  

8.2  

SAM R34/R35 Bill of Materials  

Table 8-1.ꢀBill of Materials for SAM R34/R35  

Sl. No.

 

Designator  

Quantity Value  

Manufacturer  

MPN  

C0201C104K9PACTU  

Description  

1

C303, C304, C307,

 

11  

100nF  

KEMET  

CAP CER 0.1UF 6.3V 10% X5R 0201  

C308, C311, C312,  

C313, C314, C315,  

C316, C320  

2

3

4

C306  

1

2

1

10uF  

10pF  

33pF  

Murata  

GRM155R60J106ME15  

C0603C0G1E100C  

250R05L330GV4T  

Ceramic capacitor, SMD 0402, X5R, 6.3V, 20%  

CAP CER 10PF 25V C0G 0201  

C309, C310  

C330  

TDK Corporation  

Johanson

T

e

chnology  

Inc.  

Ceramic capacitor, SMD 0201, C0G/NP0, 25V,  

+/-2%  

5

C340  

1

4.7pF  

Johanson

T

e

chnology  

Inc.  

250R05L4R7BV4T  

Ceramic capacitor, SMD 0201, C0G/NP0, 25V,  

+/-0.1pF  

6

7

8

9

C900  

1

2

2

3

18pF  

3.9pF  

5.6pF  

3.3pF  

Murata  

Murata  

Murata  

GRM0335C1H180GA01D CAP

 

CER 18PF 50V C0G/NP0 0201 +/- 2%  

GRM0335C1H3R9BA01D CAP

 

CER 3.9PF 50V C0G/NP0 0201, +/-0.1pF  

GRM0335C1E5R6BA01D CAP

 

CER 5.6PF 25V 0201  

C901, C911  

C902, C913  

C903, C916, C917  

Johanson

T

e

chnology  

Inc.  

250R05L3R3BV4T  

Ceramic capacitor, SMD 0201, C0G/NP0, 25V,  

+/-0.1pF  

10  

11  

12  

13  

14  

C905  

C907  

C908  

C910  

C912  

1

1

1

1

1

47pF  

4.7nF  

2.7pF  

22pF  

8.2pF  

1nF  

Johanson

T

e

chnology  

Inc.  

250R05L470GV4T  

Ceramic capacitor, SMD 0201, C0G/NP0, 25V,  

+/-2%  

Murata  

GRM033R71A472KA01D Ceramic

 

capacitor, SMD 0201, X7R, 10V,  

+/-10%  

Murata  

GJM0335C1E2R7BB01E Ceramic

 

capacitor, SMD 0201, C0G/NP0, 25V,  

+/-0.1pF  

Johanson

T

e

chnology  

Inc.  

250R05L220GV4T  

Ceramic capacitor, SMD 0201, C0G/NP0, 25V,  

+/-2%  

Johanson

T

e

chnology  

Inc.  

250R05L8R2CV4T  

CAP CER 8.2PF 25V NP0 0201 ±0.25pF  

15  

16  

C914  

J303  

1

1

Murata  

GRM033R71C102KA01D Ceramic

 

capacitor, SMD 0201, X7R, 16V, 0.1  

1310-1205SNS073R1 WCON

 

Hardware  

Electronics Co., Ltd  

1310-1205SNS073R1  

2×5 pin header, 1.27mm pitch, THM  

17  

18  

19  

20  

21  

22  

23  

J901  

L300  

L900  

1

1

1

4

2

1

1

SMA Edge Mount  

Cinch Connectivity  

Solutions Johnson  

142-0771-831  

Cinch Connectivity Solutions Johnson 50 Ohms,  

SMA Edge Mount Jack Receptacle  

BLM15AG121SN1D  

Murata  

Murata  

Murata  

BLM15AG121SN1D  

LQW15AN2N2C10D  

LQP03TN10NH02D  

L-05B33NJV6T  

Chip Bead, 120ohm@100Mhz, 0.55A, 0402,  

Rdc 0.19ohm  

2.2nH  

10nH  

33nH  

10nH  

11nH  

FIXED IND 2.2NH 1A 27 MOHM SMD, +-0.2nH,  

0201  

L901, L902, L907,  

L909  

FIXED IND 10NH 250MA 700 MOHM, +-3%,  

0201  

L903, L905  

Johanson

T

e

chnology  

Inc.  

RF Inductor, 33nH, +/-5%, Irms=0.2A,  

Q=5@100Mhz, DCR=2.3(Max), SMD, 0201  

L904  

TDK Corporation  

MLK0603L10NJT000  

LQP03HQ11NH02  

RF Inductor, 10nH, +/-5%, Irms=0.2A,  

Q=6@300Mhz, DCR=0.8(Max), SMD, 0201  

L906  

Murata  

FIXED IND 11NH 300MA 500 MOHM 0201  

+/-3%  

24  

25  

R300  

U300  

1

1

100k  

ASJ  

CR10-1003-FK  

Thick film resistor, SMD 0402, 1/16W, 1%  

SAMR34 BGA-64  

SAMR34J18B  

Microchip

T

e

chnology  

Inc.  

ATSAMR34J18BT-I/7JX  

DS70005356C-page 32  

Datasheet  

©

2019 Microchip

T

e

chnology Inc.  

SAM R34/R35  

Application Schematic Introduction  

………..continued  

Sl. No.

 

Designator  

Quantity Value  

Manufacturer  

Skyworks Solutions  

T

a

itien  

MPN  

SKY13373-460LF  

Description  

26  

27  

U900  

XC1  

1

1

SKY13373-460LF  

0.1-6.0GHZ SPT3 SWITCH  

32MHz TCXO  

TYETBCSANF-32.000000 32MHz

 

TCXO, 2.8 ~ 3.3

V

,

C

lipped sine wave  

10kOhm/10p

F

, 2 x

1

.6 mm SMD  

28  

Y301  

1

ABS05-32.768KHZ-9-T  

—

—

CRYSTAL 32.768KHz 9pF SMD ABS05  

DS70005356C-page 33  

Datasheet  

©

2019 Microchip

T

e

chnology Inc.  

SAM R34/R35  

Transceiver Circuit Description  

9.  

Transceiver Circuit Description  

Note:ꢀ

The SAM R34/R35 incorporates a LoRa transceiver.  

The integrated Sub-GHz transceiver supports LoRa technology spread spectrum modulation, combining  

ultra-long range communications and high interference immunity with extremely low current consumption.  

Receive sensitivities of over -148 dBm can be achieved in narrowband modes, and -136 dBm in  

LoRaWAN protocol compliant modes, using a low cost crystal and bill of materials.  

The transmit section offers two integrated power amplifiers. The highly efficient RFO port delivers up to  

+13 dBm for European regions and battery conservation. The high powered PA_BOOST port delivers a  

regulated output of +17 dBm with low EMI across the entire working voltage range or, up to +20 dBm of  

raw RF power with high-voltage supplies. This combination of high power and high RX sensitivity yields  

industry leading link budget, making it ideal for any application requiring long range low-data-rate  

communications. LoRa technology also provides significant advantages in both blocking and selectivity  

over conventional modulation techniques, solving the traditional design compromise between range,  

interference robustness and energy consumption. For maximum flexibility, the user may decide on the  

spread spectrum modulation bandwidth (BW), spreading factor (SF), and forward error correction rate  

(CR). Another benefit of the spread spectrum modulation is that each spreading factor is orthogonal, thus  

multiple transmitted signals can occupy the same channel without interfering.  

The SAM R34/R35 also supports high performance (G)FSK, (G)MSK, and OOK modes for systems  

including WMBus and IEEE802.15.4g.  

This transceiver offers bandwidth options ranging from 7.8 kHz to 500 kHz with spreading factors ranging  

from 6 to 12, and covering all available frequency bands from 137 to 1020 MHz.  

9.1  

Transceiver Pin Description  

Table 9-1.ꢀDescription of Transceiver Signals Available Outside the Package  

Name  

Type  

I

Description  

RFI_LF  

RFO_LF  

VR_ANA  

VBAT_ANA  

VR_DIG  

VBAT_DIG  

XTA  

RF Input for Bands 2 and 3  

RF Output for Bands 2 and 3  

Regulated Supply Voltage for Analog Circuitry  

Supply Voltage for Analog Circuitry  

Regulated Supply Voltage for Digital Blocks