Microchip-Tech-TN0106N3-G
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Supertex inc.
TN0106
N-Channel Enhancement-Mode
Vertical DMOS FET
General Description
Features
This low threshold, enhancement-mode (normally-off) transistor
utilizes a vertical DMOS structure and Supertex’s well-proven,
silicon-gate manufacturing process. This combination produces
a device with the power handling capabilities of bipolar transistors
and the high input impedance and positive temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
this device is free from thermal runaway and thermally-induced
secondary breakdown.
►
Low threshold – 2.0V max.
►
High input impedance
►
Low input capacitance – 50pF typical
►
Fast switching speeds
►
Low on-resistance
►
Free from secondary breakdown
►
Low input and output leakage
Applications
►
Logic level interfaces – ideal for TTL and CMOS
►
Solid state relays
Supertex’s vertical DMOS FE
T
s
a
re ideally suited to a wide range
of switching and amplifying applications where very low threshold
voltage, high breakdown voltage, high input impedance, low
input capacitance, and fast switching speeds are desired.
►
Battery operated systems
►
Photo voltaic drives
►
Analog switches
►
General purpose line drivers
►
T
e
lecom switches
Ordering Information
Package
Wafer / Die Options
Device
NW
NJ
ND
TO-92
(Die in wafer form)
(Die on adhesive tape)
(Die in waffle pack)
TN0106
TN0106N3-G
TN1506NW
TN1506NJ
TN1506ND
For packaged products, -G indicates package is RoHS compliant (‘Green’). Devices in Wafer / Die form are RoHS compliant (‘Green’).
Refer to Die Specification VF15 for layout and dimensions.
Product Summary
Pin Configurations
R
DS(ON)
I
D(ON)
V
GS(th)
BV
DSS
/BV
DGS
Device
(max)
(Ω)
(min)
(A)
(max)
(V)
(V)
TN0106N3-G
60
3.0
2.0
2.0
DRAIN
SOURCE
Absolute Maximum Ratings
GATE
Parameter
Value
BV
DSS
BV
DGS
±20V
TO-92 (N3)
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
Operating and storage temperature
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
Product Marking
SiTN
0 1 0 6
YYWW
-55
O
C to +150
O
C
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-92 (N3)
TN0106
Thermal Characteristics
I
D
I
D
Power Dissipation
†
θ
jc
(
O
C/W)
θ
ja
(
O
C/W)
I
DR
I
DRM
(A)
(continuous)
†
(mA)
(pulsed)
(A)
@T
C
= 25
O
C
(W)
Package
(mA)
TO-92
350
2.0
1.0
125
170
350
2.0
Notes:
I
D
(continuous) is limited by max rated T
j
.
†
Electrical Characteristic
s
(T
A
= 25
O
C unless otherwise specified)
Sym
BV
DSS
V
GS(th)
Parameter
Min
60
0.6
–
Typ
Max Units
Conditions
Drain-to-source breakdown voltage
Gate threshold voltage
–
–
V
V
V
GS
= 0
V
,
I
D
= 1.0mA
V
GS
= V
DS
, I
D
= 0.5mA
–
2.0
ΔV
GS(th)
Change in V
GS(th)
with temperature
-3.2
-5.0 mV/
O
C V
GS
= V
DS
, I
D
= 1.0mA
I
GSS
Gate body leakage
–
–
–
100
10
nA
V
GS
= ± 20
V
,
V
DS
= 0V
–
V
GS
= 0
V
,
V
DS
= Max Rating
I
DSS
Zero Gate voltage drain current
µA
V
DS
= 0.8 Max Rating,
–
–
500
V
GS
= 0
V
,
T
A
= 125°C
V
GS
= 5.0
V
,
V
DS
= 25V
V
GS
= 10
V
,
V
DS
= 25V
V
GS
= 4.5
V
,
I
D
= 250mA
V
GS
= 10
V
,
I
D
= 500mA
0.75
1.4
3.4
2.0
1.6
0.6
400
50
–
I
D(ON)
On-state drain current
A
2.0
–
–
4.5
3.0
1.1
–
R
DS(ON)
Static drain-to-source on-state resistance
Ω
–
ΔR
DS(ON)
Change in R
DS(ON)
with temperature
–
%/
O
C V
GS
= 10
V
,
I
D
= 500mA
G
FS
C
ISS
C
OSS
C
RSS
t
d(ON)
t
r
Forward transductance
Input capacitance
225
mmho V
DS
= 25
V
,
I
D
= 500mA
–
–
–
–
–
–
–
60
35
8.0
5.0
5.0
7.0
6.0
1.5
–
V
GS
= 0
V
,
V
DS
= 25
V
,
f = 1.0MHz
Common source output capacitance
Reverse transfer capacitance
Turn-on delay time
25
pF
ns
4.0
2.0
3.0
6.0
3.0
1.0
400
V
DD
= 25
V
,
Rise time
I
D
= 1.0A,
t
d(OFF)
t
f
Turn-off delay time
R
GEN
= 25Ω
Fall time
V
SD
Diode forward voltage drop
Reverse recovery time
V
V
GS
= 0
V
,
I
SD
= 500mA
V
GS
= 0
V
,
I
SD
= 500mA
t
rr
–
ns
Notes:
1. All
D.C. parameters 100% tested at 25
O
C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All
A.C. parameters sample tested.
Switching Waveforms and Test Circuit
V
DD
R
L
10V
90%
INPUT
Pulse
Generator
10%
0V
OUTPUT
t
(ON)
t
d(ON)
t
(OFF)
t
d(OFF)
R
GEN
t
f
t
r
VDD
0V
INPUT
D.U.
T
.
10%
10%
OUTPUT
90%
90%
2
TN0106
Typical Performance Curves
Output Characteristics
Saturation Characteristics
5.0
5.0
4.0
3.0
2.0
1.0
0
4.0
V
GS
= 10V
V
GS
= 10V
3.0
2.0
1.0
0
8V
6V
8V
6V
4V
2V
4V
2V
0
10
20
30
40
50
0
2.0
4.0
6.0
8.0
10
V
DS
(volts)
V
DS
(volts)
2.0
Power Dissipation vs. Case Temperature
Transconductance vs. Drain Current
0.5
0.4
0.3
0.2
0.1
0
T
A
= -55
O
C
T
A
= 25
O
C
T
A
= 150
O
C
TO-92
1.0
V
DS
= 25V
0
0
0.6
1.2
1.8
2.4
3.0
0
25
50
75
100
125
150
T
C
(
O
C)
I
D
(amperes)
Maximum Rated Safe Operating Area
T
C
= 25
O
C
Thermal Response Characteristics
10
1.0
1.0
0.8
0.6
0.4
0.2
0
TO-92 (pulsed)
TO-92 (DC)
0.1
TO-92
T
C
= 25
O
C
P
D
= 1W
0.01
1.0
10
100
1000
0.001
0.01
0.1
1.0
10
t
p
(seconds)
V
DS
(volts)
3
TN0106
Typical Performance Curves
(cont.)
BV
DSS
Variation with Temperature
On-Resistance vs. Drain Current
1.3
5.0
4.0
3.0
2.0
1.0
0
V
GS
= 10V
V
GS
= 5.0V
1.2
1.1
1.0
0.9
0.8
-50
0
50
100
150
0
1.0
2.0
3.0
4.0
5.0
T
j
(
O
C)
I
D
(amperes)
V
(th)
and R
DS
Variation with Temperature
Transfer Characteristics
V
DS
= 25V
1.4
1.2
1.0
0.8
0.6
0.4
3.0
1.4
1.2
1.0
0.8
0.6
0.4
T
A
= -55
O
C
V
(th)
@ 0.5mA
2.4
1.8
1.2
0.6
0
25
O
C
R
DS(ON)
@ 10V, 0.5A
150
O
C
0
2.0
4.0
6.0
8.0
10
-50
0
50
100
150
T
j
(
O
C)
V
GS
(volts)
Capacitance vs. Drain-to-Source Voltage
Gate Drive Dynamic Characteristics
10
8.0
6.0
4.0
2.0
0
100
75
50
25
0
f = 1.0MHz
V
DS
= 10V
V
DS
= 40V
55pF
C
ISS
C
OSS
C
RSS
50pF
0
1.0
2.0
3.0
4.0
5.0
0
10
20
30
40
Q
G
(nanocoulombs)
V
DS
(volts)
4
TN0106
3-Lead TO-92 Package Outline (N3)
D
A
Seating
Plane
1
2
3
L
b
c
e1
e
Side View
Front View
E
E1
3
1
2
Bottom View
Symbol
A
.170
–
b
.014
†
–
c
D
.175
–
E
.125
–
E1
.080
–
e
e1
.045
–
L
.500
–
MIN
NOM
MAX
.014
†
–
.095
–
Dimensions
(inches)
.210
.022
†
.022
†
.205
.165
.105
.105
.055
.610*
JEDEC Registration TO-92.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc.#:
DSPD-3TO92N3, Version E041009.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
Supertex inc.
does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.”
Supertex inc.
does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the
Supertex inc.
(website: http//www.supertex.com)
©2011
Supertex inc
.
All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
T
e
l: 408-222-8888
Doc.# DSFP-TN0106
B080811
5
Mouser Electronics
Authorized Distributor
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