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UXN40M7K
Datasheet
40 GHz Divide-by-1-to-127 Programmable
Integer Divider
40 GHz Divide-by-1-to-127 Programmable Integer Divider
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UXN40M7K Datasheet Revision 2.0
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40 GHz Divide-by-1-to-127 Programmable Integer Divider
1
Revision History
The revision history describes the changes that were implemented in the document. The changes
are listed by revision, starting with the most current publication.
1.1
1.2
Revision 1.0
Revision 1.0 was published in February 2017. It was the first publication of this document.
Revision 2.0
Revision 2.0 was published in April 2020. The Electrical Characteristics table was updated.
UXN40M7K Datasheet Revision 2.0
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40 GHz Divide-by-1-to-127 Programmable Integer Divider
Contents
UXN40M7K Datasheet Revision 2.0
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40 GHz Divide-by-1-to-127 Programmable Integer Divider
Figures
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40 GHz Divide-by-1-to-127 Programmable Integer Divider
Tables
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40 GHz Divide-by-1-to-127 Programmable Integer Divider
2
Product Overview
The UXN40M7K is a highly programmable integer divider covering all integer divide ratios between 1
and 127. The device features single-ended or differential inputs and outputs. Parallel control inputs
are CMOS and LVTTL compatible for ease of system integration. The UXN40M7K is packaged in a 24-
pin, 4 mm × 4 mm leadless ceramic surface mount package, shown in the following figure
(dimensions are in millimeters).
Figure 1
UXN40M7K Package Outline
2.1
2.2
Applications
The UXN40M7K can be used as a general purpose, highly configurable divider in a variety of high-
frequency synthesizer applications. Fast switching combined with a wide range of divide ratios make
the UXN40M7K an excellent choice for fractional-N and integer-N phase-locked loops. Fractional
division may be achieved by applying a sequence to the divider control lines, such as a delta-sigma
modulated sequence.
Key Features
The following are the key features of the UXN40M7K device:
•
•
•
•
•
•
•
Wide operating range: 0.5 GHz–40 GHz
Contiguous divide ratios: 1 to 127
Large output swings: >600 mVpp/side
Single-ended and/or differential drive
Small size: 4 mm × 4 mm
Parallel control lines
Low SSB phase noise: –153 dBc at 10 kHz offset
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40 GHz Divide-by-1-to-127 Programmable Integer Divider
3
Electrical Specifications
This section details the electrical specifications of the UXN40M7K device.
3.1
Electrical Characteristics
The following table shows the electrical characteristics of the UXN40M7K device at 25 °C, where
V
CC
= 3.3 V, I
CC
= 230 mA, and Z
O
= 50
Ω
.
Table 1
Electrical Characteristics
Parameter
F
IN
(GHz)
P
IN
(dBm)
P
OUT
(dBm)
P
DC
(W)
Description
Min
Typ
Max
50
Input frequency
0.5
Input power
0
10
Output power
2.00
0.75
26
DC power dissipation
Junction-case thermal resistance
θ
JC
(°C/W)
3.2
Functional Block Diagram
The following drawing shows the functional blocks of the UXN40M7K device.
Figure 2
Functional Block Diagram
3.3
Pin Descriptions
The following table shows the pin descriptions of the UXN40M7K device.
Table 2
Pin Descriptions
Pin Name
Description
Notes
1
IN
P
Divider input, positive terminal
Divider input, negative terminal
Divider output, positive terminal
Divider output, positive terminal
CML signal levels
CML signal levels
CML signal levels
CML signal levels
1
IN
N
OUT
P
OUT
N
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40 GHz Divide-by-1-to-127 Programmable Integer Divider
Pin Name
R0–R6
V
CC
Description
Notes
Divider modulus control (R6 = MSB)
3.3 V at 230 mA
CMOS levels default to logic 0
Positive supply voltage
The paddle is floating
V
EE
RC and DC ground
1
V
CM
Common mode input
1. IN
P
, IN
N
, and V
CM
require coupling capacitors at the inputs, with V
CM
’s capacitor going to ground.
Use the following equation to find the divider modulus, where setting all bits to 0 results in N = 1.
Divider Modulus = N = P
0
∙ 2
0
+ P
1
∙ 2
1
+ P
2
∙ 2
2
+ … + P
6
∙ 2
6
for 1
≤ N ≤
127
3.4
CMOS Levels
The following table shows the CMOS levels for control lines R0-R8 of the UXN40M7K device.
Table 3
CMOS Levels for Control Lines R0-R8
Logic Level
Minimum
3.6
Typical
V
Supply voltage (V
CC
-V
EE
)
RF input power (IN
P
, IN
N
)
Operating temperature
Storage temperature
Junction temperature
10
dBm
°C
–40 to 85
–85 to 125
125
°C
°C
The following table shows the CMOS levels for control lines R0-R8 of the UXN40M7K device.
Table 4
CMOS Levels for Control Lines R0-R8
Logic State (P
i
)
1 (high)
Minimum
V
CC
– 1.3 V
V
EE
Typical
V
CC
Maximum
V
CC
0 (low)
V
EE
V
EE
+ 0.8 V
3.5
Simplified Control Logic Schematic
The following drawing shows the simplified control logic schematic of the UXN40M7K device.
Figure 3
Simplified Control Logic Schematic
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40 GHz Divide-by-1-to-127 Programmable Integer Divider
3.6
Typical Performance Plots
This section details the typical performance plots of the UXN40M7K device.
Figure 4
Min/Max Single-Ended Input Power
Input Sensitivity Window
Figure 5
Divide-by-8 Output Power,
3rd Harmonic, and Input Feed Through
Figure 7
Static Divide-by-127 Configuration
Figure 9
Fundamental Feed Through
Figure 6
Static Divide-by-80 Configuration
Figure 8
Output Amplitude vs. Frequency
UXN40M7K Datasheet Revision 2.0
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40 GHz Divide-by-1-to-127 Programmable Integer Divider
Figure 10
Sensitivity Window vs.
Supply Voltage
Figure 11
Sensitivity Window vs.
Temperature
Figure 12
S-Parameters S11
Figure 13
S-Parameters S12
Figure 14
S-Parameters S21
Figure 15
S-Parameters S22
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40 GHz Divide-by-1-to-127 Programmable Integer Divider
4
Pin Definition and Package Outline
The UXN40M7K is packaged in a 24-pin, 4 mm × 4 mm leadless ceramic surface mount package.
4.1
Pin Definition
The following table shows the pin definitions for the UXN40M7K device.
Table 5
Pin Definitions
Pin
Function
Notes
1 (R1)
2 (R0)
Divide modulus control
Divide modulus control (LSB)
RF and DC ground
Defaults to logic 0, connect to V
CC
for logic 1
Defaults to logic 0, connect to V
CC
for logic 1
0 V
3, 8, 9, 12,
17 (VEE)
4 (INP)
5 (INN)
6 (VCM)
Divider input
Positive terminal of differential input
Negative terminal of differential input
Refer to functional block diagram
Nominally +3.3 V
Divider input
Common mode input
7, 10, 11, 13,
Positive supply voltage
16, 19 (VCC)
14 (OUTP)
15 (OUTN)
18 (VADJ)
20 (R6)
Divider output
Positive terminal of differential output
Negative terminal of differential output
Tie to VCC for maximum swing
Divider output
Output amplitude control
Divide modulus control (MSB)
Divide modulus control
Divide modulus control
Divide modulus control
Divide modulus control
Package paddle
Defaults to logic 0, connect to V
CC
for logic 1
Defaults to logic 0, connect to V
CC
for logic 1
Defaults to logic 0, connect to V
CC
for logic 1
Defaults to logic 0, connect to V
CC
for logic 1
Defaults to logic 0, connect to V
CC
for logic 1
Tie to heat sink
21 (R5)
22 (R4)
23 (R3)
24 (R2)
Paddle
UXN40M7K Datasheet Revision 2.0
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40 GHz Divide-by-1-to-127 Programmable Integer Divider
4.2
Package Outline
The following drawing shows the physical characteristics of the UXN40M7K device.
Figure 16
Package Outline
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40 GHz Divide-by-1-to-127 Programmable Integer Divider
5
Application Notes
5.1
Low-Frequency Operation
Low-frequency operation is limited by external coupling capacitors and the slew rate of the input
clock. The next paragraph shows the calculations for the capacitors. Sine-wave inputs are limited to
roughly 500 MHz.
The values of the coupling capacitors for the high-speed inputs and outputs (I/Os) are determined by
the lowest IC operation frequency.
1
C
≫
2
∙ ꢀ ∙
50
ꢁ ∙
ꢂ
ꢃꢄꢅꢆꢇꢈ
For example, to use the device below 1 GHz, coupling capacitors should be larger than 3 pF.
5.2
5.3
IC Assembly
The device is designed to operate with either single-ended or differential inputs. The supply should
be capacitively bypassed to ground to provide a good AC ground over the frequency range of
interest. RF I/Os should be AC-coupled through the series capacitors. The backside of the chip
should be connected to a good thermal heat sink.
ESD Sensitivity
Although SiGe ICs have robust ESD sensitivities, preventative ESD measures should be taken while
storing, handling, and assembling.
Inputs are more ESD susceptible because they could expose the base of a BJT. All control inputs are
protected with ESD diodes. These inputs should withstand voltage spikes up to 400 V.
5.4
Differential vs. Single-Ended
The UXN40M7K is fully differential to maximize signal-to-noise ratios for high-speed operation. The
high-speed outputs are terminated to V
CC
with on-chip 75
Ω
resistors. The maximum DC voltage on
either of the output terminals must be limited to V
CC
± 1 V to prevent damaging the termination
resistors with excessive current.
The outputs require a DC return path capable of handling approximately 24 mA per side with V
ADJ
set
recommended for the fastest operation with maximum swing. The value of the capacitor should be
large enough to pass the lowest frequencies of interest. The discrete R/L/C elements should be
resonance free up to the maximum frequency of operation for broadband applications.
UXN40M7K Datasheet Revision 2.0
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40 GHz Divide-by-1-to-127 Programmable Integer Divider
Figure 17
Bias Tee Circuit
The high-speed inputs are terminated to an internal reference voltage (V
REF
) set by a resistive divider
between V
CC
and V
EE
. For V
CC
= 3.3. V and V
EE
tied to ground, the nominal value of V
REF
is 1.9 V, and
equivalent impedance from V
REF
is approximately 800
Ω
. It is recommended that DC voltage on any
of the input terminals be maintained between a minimum of V
EE
– 1 V and a maximum of V
CC
+ 1 V.
Note:
A potential oscillation mechanism exists if both inputs are static and have identical DC voltages—a small
DC offset on either input is sufficient to prevent possible oscillations. Connecting a 10k
Ω
resistor between
the unused input and V
EE
should provide sufficient offset to prevent oscillation.
The UXN40M7K device can also be used in single-ended applications. All unused ports should be
terminated with the same loading as the ports being used.
The following diagram shows AC coupling with a positive supply.
Figure 18
Positive Supply (AC Coupling)
UXN40M7K Datasheet Revision 2.0
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40 GHz Divide-by-1-to-127 Programmable Integer Divider
5.5
Duty Cycle
The UXN40M7K output duty cycle varies between 33% and 66% as a function of the divide ratio, N.
When N is a power of 2, the duty cycle is exactly 50%. As N deviates from a power of 2, so too does
the duty cycle deviate from 50%. For example, N = 64 has 50% duty cycle, N = 60 has 47% duty cycle,
and N = 56 has 43% duty cycle.
The following equations calculate pulse width and duty cycle as a function of N, for any integer N
from 2 to 127.
N
3
ꢖ
ꢗ
+1ꢘ
floor�log2
(
)
ꢉꢊꢋꢌꢍ ꢎꢏꢐꢑℎ
ꢏꢒꢓꢊꢑ ꢔꢕꢔꢋꢍꢌ
= N– 2
ꢉꢊꢋꢌꢍ ꢎꢏꢐꢑℎ
ꢙꢏꢚꢏꢐꢍ ꢛꢜꢑꢏꢝ
(
)
ꢙꢊꢑꢕ ꢔꢕꢔꢋꢍ
1% =
× 100%
The following illustration shows the period–pulse width relationship for the UXN40M7K device.
Figure 19
Period–Pulse Width Relationship
The following table shows the pulse width and duty cycle for N from 2 to 16 for the UXN40M7K
device.
Table 6
Duty Cycle Summary
Divide Ratio
Pulse Width (Input Cycles)
Duty Cycle (%)
2
1
1
2
3
2
3
4
5
6
7
4
5
6
7
8
50
33
50
60
33
43
50
55
60
63
33
38
43
47
50
3
4
5
6
7
8
9
10
11
12
13
14
15
16
UXN40M7K Datasheet Revision 2.0
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40 GHz Divide-by-1-to-127 Programmable Integer Divider
The following graph shows the duty cycle versus divide ratio for N = 1 to 127 for the UXN40M7K
device.
Figure 20
Duty Cycle vs. Divide Ratio
UXN40M7K Datasheet Revision 2.0
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40 GHz Divide-by-1-to-127 Programmable Integer Divider
6
Ordering Information
The following table shows the ordering information for the UXN40M7K device.
Table 7
Ordering Information
Part Number
Package
UXN40M7K
24-pin ceramic leadless surface mount package
UXN40M7K Datasheet Revision 2.0
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