Microchip-Tech-VN2450N3-G
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VN2450
N-Channel Enhancement-Mode
Vertical DMOS FETs
Features
General Description
►
Free from secondary breakdown
►
Low input and output leakage
This enhancement-mode (normally-off) transistor utilizes a
vertical DMOS structure
and Supertex’s well-proven silicon-gate
manufacturing process. This combination produces a device with
the power handling capabilities of bipolar transistors and with
the high input impedance and positive temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
this device is free from thermal runaway and thermally induced
secondary breakdown.
►
Low C
ISS
and fast switching speeds
►
High input impedance and high gain
Applications
►
Motor controls
►
Converters
Supertex’s vertical DMOS FE
T
s
a
re ideally suited to a wide range
of switching and amplifying applications where high breakdown
voltage, high input impedance, low input capacitance, and fast
switching speeds are desired.
►
Amplifiers
►
Switches
►
Power supply circuits
►
Drivers (relays, hammers, solenoids, lamps,
memories, displays, bipolar transistors, etc.)
Ordering Information
Package Options
Device
R
DS(ON)
I
D(ON)
BV
DSS
/BV
DGS
(max)
(Ω)
(min)
(mA)
TO-243AA
(V)
TO-92
(SOT-89)
VN2450
VN2450N3-G
VN2450N8-G
500
13
500
-G indicates package is RoHS compliant (‘Green’)
Pin Configurations
DRAIN
DRAIN
SOURCE
SOURCE
DRAIN
Absolute Maximum Ratings
Parameter
GATE
GATE
Value
BV
DSS
TO-92 (N3)
TO-243AA (SOT-89) (N8)
Drain-to-source voltage
Drain-to-gate voltage
BV
DGS
Product Marking
Gate-to-source voltage
±20V
SiVN
2 4 5 0
YY WW
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
Operating and storage temperature
Soldering temperature*
-55°C to +150°C
+300°C
Package may or may not include the following marks: Si or
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
TO-92 (N3)
W = Code for week sealed
VN4EW
= “Green” Packaging
*
Distance of 1.6mm from case for 10 seconds.
Package may or may not include the following marks: Si or
TO-243AA (SOT-89) (N8)
VN2450
Thermal Characteristics
I
D
I
D
Power Dissipation
†
θ
jc
(
O
C/W)
θ
ja
(
O
C/W)
I
DR
I
DRM
(mA)
(continuous)
*
(mA)
(pulsed)
(mA)
@T
A
= 25
O
C
(W)
Package
(mA)
TO-92
200
250
650
750
0.74
1.6
‡
125
15
170
78
‡
200
250
650
750
TO-243AA
Notes:
†
‡
I
D
(continuous) is limited by max rated T
J
,
Mounted on FR5 board, 25mm x 25mm x 1.57mm.
(T =
25°C unless otherwise specified)
Electrical Characteristics
A
Sym
BV
DSS
V
GS(th)
Parameter
Min
Typ
Max
–
Units Conditions
Drain-to-source breakdown voltage
Gate threshold voltage
500
–
–
–
–
V
V
V
GS
= 0
V
,
I
D
= 2.0mA
V
GS
= V
DS
, I
D
= 1.0mA
1.5
4.0
-5.5
100
ΔV
GS(th)
Change in V
GS(th)
with temperature
–
–
mV/
O
C V
GS
= V
DS
, I
D
= 1.0mA
I
GSS
Gate body leakage current
nA
V
GS
= ±20
V
,
V
DS
= 0V
V
GS
= 0
V
,
V
DS
= Max Rating
–
–
–
–
10
µA
I
DSS
Zero gate voltage drain current
V
DS
= 0.8 Max Rating,
V
GS
= 0
V
, T
A
= 125
O
C
1.0
mA
A
I
D(ON)
On-state drain current
0.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
V
GS
= 10
V
,
V
DS
= 25V
V
GS
= 4.5
V
,
I
D
= 100mA
V
GS
= 10
V
,
I
D
= 400mA
–
–
20
13
1.7
–
R
DS(ON)
Static drain-to-source on-state resistance
Ω
ΔR
DS(ON)
Change in R
DS(ON)
with temperature
–
%/
O
C V
GS
= 10
V
,
I
D
= 400mA
G
FS
C
ISS
C
OSS
C
RSS
t
d(ON)
t
r
Forward transconductance
Input capacitance
50
–
mmho V
DS
= 25
V
,
I
D
= 200mA
150
50
25
10
10
25
20
1.5
V
GS
= 0
V
,
V
DS
= 25
V
,
f = 1.0MHz
Common source output capacitance
Reverse transfer capacitance
Turn-on delay time
–
pF
–
–
V
DD
= 25
V
,
I
D
= 250mA,
R
GEN
= 25Ω
Rise time
–
ns
V
t
d(OFF)
t
f
Turn-off delay time
–
Fall time
–
V
SD
Diode forward voltage drop
–
V
GS
= 0
V
,
I
SD
= 400mA
Notes:
1. All
D.C. parameters 100% tested at 25
O
C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All
A.C. parameters sample tested.
V
DD
R
L
Switching Waveforms and Test Circuit
10V
90%
INPUT
PULSE
GENERATOR
10%
0V
OUTPUT
t
(ON)
t
d(ON)
t
(OFF)
t
d(OFF)
R
GEN
t
r
t
F
V
DD
D.U.
T
.
10%
10%
INPUT
OUTPUT
0V
90%
90%
2
VN2450
Typical Performance Curves
Saturation Characteristics
Output Characteristics
VGS = 10V
8V
1.2
1.0
0.8
VGS = 10V
1.0
6V
8V
6V
0.8
0.6
0.4
0.6
0.4
0.2
0
5V
5V
4V
3V
4V
3V
0.2
0
0
10
20
30
40
50
0
2
4
6
8
10
V
DS
(volts)
V
DS
(volts)
Transconductance vs. Drain Current
Power Dissipation vs. Case
T
e
mperature
SO
T
–
89
0.5
0.4
0.3
0.2
0.1
0
2.0
1.6
1.2
V
= 25V
DS
T
= -55°C
A
T
= 25°C
A
0.8
0.4
0
TO-92
T
= 125°C
A
0
25
50
75
100
125
150
0
0.2
0.4
0.6
0.8
1.0
T
C
(
O
C)
I
D
(amperes)
Maximum Rated Safe Operating Area
Thermal Response Characteristics
SOT-89
SOT-89 (pulsed)
1.0
0.1
1.0
0.8
0.6
0.4
TO-92 (pulsed)
P
T
= 1.6W
= 25°C
D
C
SOT-89
TO-92
0.01
0.001
0.2
0
TO-92
P
T
= 1W
= 25°C
D
C
T
= 25°C
C
1
10
100
1000
0.001
0.01
0.1
1.0
10
V
DS
(volts)
t
p
(seconds)
3
VN2450
Typical Performance Curves
(cont.)
BV
DSS
Variation with
T
e
mperature
On-Resistance vs. Drain Current
1.2
30
25
VGS = 4.5V
1.1
1.0
0.9
0.8
20
15
10
VGS = 10V
5
0
0
0.3
0.6
0.9
1.2
1.5
-50
0
50
100
150
I
D
(amperes)
T
J
(
O
C)
Transfer Characteristics
V
(th)
and R
DS
Variation with
T
e
mperature
1.2
3.0
1.5
V
= 25V
R
@ 10
V
,
0
.4A
DS
T
= -55
O
C
A
DS(on)
1.0
0.8
0.6
0.4
0.2
0.0
1.35
2.5
2.0
1.5
1.0
0.5
0.0
V
@ 1mA
GS(th)
1.2
1.05
0.9
T
= 25
O
C
A
T
= 125
O
C
A
0.75
0.6
-50
-25
0
25
50
75
100 125 150
0
1
2
3
4
5
6
T
J
(
O
C)
V
GS (volts)
Gate Drive Dynamic Characteristics
Capacitance vs. Drain-to-Source Voltage
300
225
150
75
10
8
I
= 0.5A
f = 1MHz
D
V
=10V
DS
V
=40V
DS
6
C
ISS
4
2
C
OSS
C
RSS
0
0
0
10
20
30
40
0
1.0
2.0
3.0
4.0
Q
G
(nanocoulombs)
V
DS
(volts)
4
VN2450
3-Lead TO-92 Package Outline (N3)
D
A
1
2
3
Seating Plane
L
b
c
e1
e
Side View
Front View
E
E1
3
1
2
Bottom View
Symbol
A
b
c
D
.175
–
E
.125
–
E1
e
.095
–
e1
.045
–
L
.500
–
MIN
NOM
MAX
.170
–
.014
†
–
.014
†
–
.080
–
Dimensions
(inches)
.210
.022
†
.022
†
.205
.165
.105
.105
.055
.610*
JEDEC Registration TO-92.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc.#:
DSPD-3TO92N3, Version E041009.
5
VN2450
3-Lead TO-243AA (SOT-89) Package Outline (N8)
b
b1
Symbol
A
1.40
–
b
b1
0.36
–
C
0.35
–
D
4.40
–
D1
1.62
–
E
2.29
–
E1
2.00
†
–
e
e1
H
3.94
–
L
0.89
–
MIN
NOM
MAX
0.44
–
Dimensions
(mm)
1.50
BSC
3.00
BSC
1.60
0.56
0.48
0.44
4.60
1.83
2.60
2.29
4.25
1.20
JEDEC Registration TO-243, Variation AA, Issue C, July 1986.
†
This dimension differs from the JEDEC drawing
Drawings not to scale
.
Supertex Doc. #:
DSPD-3TO243AAN8, Version E051509.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
Supertex inc.
does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an
adequate “product liability indemnification insurance agreement.”
Supertex inc.
does not assume responsibility for use of devices described, and limits its liability to the
replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications refer to the
Supertex inc.
website: http//www.supertex.com.
©2009
All rights reserved. Unauthorized use or reproduction is prohibited.
1235 Bordeaux Drive, Sunnyvale, CA 94089
T
e
l: 408-222-8888
Doc.# DSFP-VN2450
A052209
6
