Nexperia-BUK9880-55A-CUX
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BUK9880-55A
N-channel TrenchMOS logic level FET
19 March 2014
Product data sheet
1. General
description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
2. Features
and benefits
Low conduction losses due to low on-state resistance
Q101 compliant
Suitable for logic level gate drive sources
•
•
•
3. Applications
12 V and 24 V loads
Automotive and general purpose power switching
Motors, lamps and solenoids
•
•
•
4. Quick
reference data
Table 1.
Symbol
Quick reference data
Parameter
Conditions
Min
Typ
Max
55
7
Unit
V
V
DS
I
D
drain-source voltage
drain current
T
j
≥ 25 °C; T
j
≤ 150 °C
–
–
–
–
–
–
A
P
tot
8
W
Static characteristics
R
DSon
drain-source on-state
resistance
V
GS
= 10 V; I
D
= 8 A; T
j
= 25 °C
V
GS
= 4.5 V; I
D
= 8 A; T
j
= 25 °C
–
–
–
62
–
73
89
80
mΩ
mΩ
mΩ
68
Avalanche ruggedness
E
DS(AL)S
non-repetitive drain-
I
D
= 6 A; V
sup
≤ 55 V; R
GS
= 50 Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped
–
–
36
mJ
source avalanche
energy
Nexperia
BUK9880-55A
N-channel TrenchMOS logic level FET
5. Pinning
information
Table 2.
Pin
Pinning information
Symbol Description
Simplified outline
Graphic symbol
4
D
1
2
3
4
G
D
S
D
gate
drain
source
drain
G
1
2
3
mbb076
S
SC-73 (SOT223)
6. Ordering
information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
BUK9880-55A
SC-73
plastic surface-mounted package with increased heatsink; 4
leads
SOT223
BUK9880-55A/CU
SC-73
plastic surface-mounted package with increased heatsink; 4
leads
SOT223
7. Marking
Table 4.
Marking codes
Type number
Marking code
988055A
BUK9880-55A
BUK9880-55A/CU
988055
8. Limiting
values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
Parameter
Conditions
Min
Max
55
55
15
8
Unit
drain-source voltage
drain-gate voltage
gate-source voltage
total power dissipation
drain current
T
j
≥ 25 °C; T
j
≤ 150 °C
R
GS
= 20 kΩ
–
V
V
V
W
A
A
A
V
DGR
V
GS
–
-15
P
tot
–
–
–
–
I
D
4
7
I
DM
peak drain current
30
©
BUK9880-55A
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Nexperia B.V. 2017. All rights reserved
Product data sheet
19 March 2014
2 / 13
Nexperia
BUK9880-55A
N-channel TrenchMOS logic level FET
Symbol
T
stg
Parameter
Conditions
Min
-55
-55
-15
Max
150
150
15
Unit
°C
°C
V
storage temperature
junction temperature
peak gate-source voltage
T
j
V
GSM
pulsed; t
p
≤ 50 µs
Source-drain diode
I
S
source current
peak source current
T
sp
= 25 °C
–
–
7
A
A
I
SM
pulsed; t
p
≤ 10 µs; T
sp
= 25 °C
30
Avalanche ruggedness
E
DS(AL)S
non-repetitive drain-source
I
D
= 6 A; V
sup
≤ 55 V; R
GS
= 50 Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped
–
36
–
mJ
J
avalanche energy
E
DS(AL)R
repetitive drain-source
avalanche energy
[1] Maximum
value not quoted. Repetitive rating defined in avalanche rating figure.
[2] Single-pulse
avalanche rating limited by maximum junction temperature of 150 °C.
[3] Repetitive
avalanche rating limited by an average junction temperature of 145 °C.
[4] Refer
to application note AN10273 for further information.
03aa17
003aab787
120
8
I
D
P
(A)
der
(%)
6
4
2
0
80
40
0
0
50
100
150
200
T
sp
(°C)
0
50
100
150
200
T
sp
(°C)
Fig. 1.
Normalized total power dissipation as a
function of solder point temperature
Fig. 2.
Continuous drain current as a function of solder
point temperature
©
BUK9880-55A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
19 March 2014
3 / 13
Nexperia
BUK9880-55A
N-channel TrenchMOS logic level FET
03nc54
10
3
I
D
(A)
10
2
R
D
S
on
= V
DS
/ I
D
t
p
= 10 µs
100 µs
1 ms
10
1
t
p
T
DC
P
10 ms
δ =
100 ms
10
-1
t
t
p
T
10
-2
10
-1
1
10
10
2
V
DS
(V)
Fig. 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
003aab771
10
I
AL
(A)
(1)
1
(2)
(3)
10
-1
10
-2
10
-3
10
-2
10
-1
1
10
t
AL
(ms)
Fig. 4.
Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time.
9. Thermal
characteristics
Table 6.
Symbol
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
R
th(j-sp)
thermal resistance
from junction to solder
point
–
–
15
K/W
©
BUK9880-55A
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Nexperia B.V. 2017. All rights reserved
Product data sheet
19 March 2014
4 / 13
Nexperia
BUK9880-55A
N-channel TrenchMOS logic level FET
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
R
th(j-a)
thermal resistance
from junction to
ambient
–
120
–
K/W
03nc55
10
2
Z
th(j-sp)
(K/W)
δ = 0.5
10
1
0.2
0.1
0.05
t
p
P
δ=
0.02
T
10
-1
Single Shot
t
t
p
T
10
-2
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
1
10
10
2
t
p
(s)
Fig. 5.
Transient thermal impedance from junction to solder point as a function of pulse duration
10. Characteristics
Table 7.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V
(BR)DSS
drain-source
breakdown voltage
I
D
= 0.25 mA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 0.25 mA; V
GS
= 0 V; T
j
= 25 °C
50
55
1
–
–
V
V
V
–
–
V
GS(th)
gate-source threshold
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
1.5
2
voltage
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 150 °C;
0.6
–
–
–
–
V
V
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
2.3
I
DSS
drain leakage current
gate leakage current
V
DS
= 55 V; V
GS
= 0 V; T
j
= 150 °C
V
DS
= 55 V; V
GS
= 0 V; T
j
= 25 °C
V
GS
= 10 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -10 V; V
DS
= 0 V; T
j
= 25 °C
–
–
–
–
–
–
500
10
µA
µA
nA
nA
mΩ
0.05
I
GSS
2
2
–
100
100
147
R
DSon
drain-source on-state
resistance
V
GS
= 5 V; I
D
= 8 A; T
j
= 150 °C;
V
GS
= 10 V; I
D
= 8 A; T
j
= 25 °C
–
–
62
73
89
mΩ
mΩ
V
GS
= 4.5 V; I
D
= 8 A; T
j
= 25 °C
All information provided in this document is subject to legal disclaimers.
19 March 2014
–
©
BUK9880-55A
Nexperia B.V. 2017. All rights reserved
Product data sheet
5 / 13
Nexperia
BUK9880-55A
N-channel TrenchMOS logic level FET
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
–
68
80
mΩ
Dynamic characteristics
Q
G(tot)
total gate charge
Q
GS
I
D
= 10 A; V
DS
= 44 V; V
GS
= 5 V;
–
–
–
11
–
–
–
nC
nC
nC
gate-source charge
gate-drain charge
1.6
4.6
Q
GD
I
D
= 10 A; V
DS
= 44 V; V
GS
= 5 V;
C
iss
C
oss
C
rss
input capacitance
output capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
–
–
–
438
87
584
104
85
pF
pF
pF
reverse transfer
capacitance
62
t
d(on)
t
r
t
d(off)
t
f
turn-on delay time
rise time
V
DS
= 30 V; R
L
= 1.2 Ω; V
GS
= 5 V;
R
G(ext)
= 10 Ω; T
j
= 25 °C
–
–
–
–
8
–
–
–
–
ns
ns
ns
ns
118
20
32
turn-off delay time
fall time
Source-drain diode
V
SD
source-drain voltage
t
rr
–
–
–
0.85
33
1.2
V
reverse recovery time
I
S
= 20 A; dI
S
/dt = -100 A/µs;
–
–
ns
nC
V
GS
= -10 V; V
DS
= 30 V; T
j
= 25 °C
Q
r
recovered charge
60
03nc51
03nc50
60
80
I
D
(A)
V
GS
(V) = 10
R
DSon
(mΩ)
7
6
40
5
60
4
3.4
3
20
2.4
2.2
40
0
2
4
6
8
10
0
2
4
6
8
10
V
DS
(V)
V
GS
(V)
Fig. 7.
Drain-source on-state resistance as a function
of gate-source voltage; typical values
Fig. 6.
Output characteristics: drain current as a
function of drain-source voltage; typical values
©
BUK9880-55A
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Nexperia B.V. 2017. All rights reserved
Product data sheet
19 March 2014
6 / 13
Nexperia
BUK9880-55A
N-channel TrenchMOS logic level FET
03aa36
03nc48
10
-1
I
D
12
10
8
g
fs
(A)
(S)
10
-2
10
-3
10
-4
10
-5
min
typ
max
6
4
2
10
-6
0
0
0
5
10
15
20
1
2
3
V
GS
(V)
I
D
(A)
T
j
= 25 °C; V
DS
= 5 V
Fig. 9.
Forward transconductance as a function of
drain current; typical values
Fig. 8.
Sub-threshold drain current as a function of
gate-source voltage
03nc49
03nc47
15
5
V
GS
(V)
I
D
(A)
4
10
V
DS
= 14 V
3
V
DS
= 44 V
2
1
0
5
°
T
j
= 150
C
2
T
j
= 25 °C
3
0
0
1
4
0
5
10
15
V
GS
(V)
Q
G
(nC)
Fig. 10.
Transfer characteristics: drain current as a
function of gate-source voltage; typical values
Fig. 11.
Gate-source voltage as a function of turn-on
gate charge; typical values
©
BUK9880-55A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
19 March 2014
7 / 13
Nexperia
BUK9880-55A
N-channel TrenchMOS logic level FET
03aa33
03nc52
2.5
V
GS(th)
(V)
180
R
D
S
on
(mΩ)
150
V
GS
(V) = 5
3
3.2
3.6 3.8
4
3.4
2
1.5
1
max
120
90
60
30
0
typ
min
0.5
0
-60
0
10
20
30
40
0
60
120
180
I
D
(A)
T ( C)
°
j
Fig. 13.
Drain-source on-state resistance as a function
of drain current; typical values
Fig. 12.
Gate-source threshold voltage as a function of
junction temperature
03nc37
03nc24
2
5
a
V
GS
(V)
1.8
V
= 14 V
DD
1.6
1.4
1.2
1
4
3
2
1
0
V
= 44 V
DD
0.8
0.6
0.4
0.2
0
0
10
20
30
-60
-20
20
60
100
140
180
Q
(nC)
G
°
T
j
( C)
Fig. 14.
Normalized drain source on-state resistance
factor as a function of junction temperature
Fig. 15.
Gate-source voltage as a function of turn-on
gate charge; typical values
©
BUK9880-55A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
19 March 2014
8 / 13
Nexperia
BUK9880-55A
N-channel TrenchMOS logic level FET
03nc53
03nc46
1200
C
60
(pF)
I
S
(A)
1000
800
600
400
200
40
C
iss
20
C
o
s
s
°
T
j
= 150
C
°
T
j
= 25
C
C
r
s
s
0
0
0.0
10
-2
10
-1
1
10
10
2
0.5
1.0
1.5
2.0
V
SD
(V)
V
DS
(V)
Fig. 16.
Input, output and reverse transfer capacitances
Fig. 17.
Reverse diode current as a function of reverse
as a function of drain-source voltage; typical
values
diode voltage; typical value
©
BUK9880-55A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
19 March 2014
9 / 13
Nexperia
BUK9880-55A
N-channel TrenchMOS logic level FET
11. Package
outline
Plastic surface-mounted package with increased heatsink; 4 leads
SOT223
D
E
B
A
X
c
y
H
v
M
A
E
b
1
4
Q
A
A
1
L
1
2
3
p
e
b
p
w
M
B
detail X
1
e
0
2
4 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
b
p
b
c
D
E
e
e
H
L
p
Q
v
w
y
1
1
1
E
1.8
1.5
0.10 0.80
0.01 0.60
3.1
2.9
0.32
0.22
6.7
6.3
3.7
3.3
7.3
6.7
1.1
0.7
0.95
0.85
mm
4.6
2.3
0.2
0.1
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-10
06-03-16
SOT223
SC-73
Fig. 18.
Package outline SC-73 (SOT223)
©
BUK9880-55A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
19 March 2014
10 / 13
Nexperia
BUK9880-55A
N-channel TrenchMOS logic level FET
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including – without limitation –
lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
12. Legal information
12.1 Data
sheet status
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the
Terms and conditions of commercial sale
of Nexperia.
Document
Product
Definition
Objective
[short] data
sheet
Development This
document contains data from
the objective specification for product
development.
Right to make changes
— Nexperia reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Preliminary
[short] data
sheet
Qualification This
document contains data from the
preliminary specification.
Suitability for use in automotive applications
— This Nexperia
product has been qualified for use in automotive
Product
[short] data
sheet
Production
This document contains the product
specification.
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
[1] Please
consult the most recently issued document before initiating or
completing a design.
[2] The
term ‘short data sheet’ is explained in section “Definitions”.
[3] The
product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
Quick reference data
— The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
12.2 Definitions
Applications
— Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Preview
— The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
Nexperia does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
no liability for the consequences of use of such information.
Customers are responsible for the design and operation of their
applications and products using Nexperia products, and Nexperia
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the Nexperia product is suitable and fit for the
Draft
— The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
Short data sheet
— A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local Nexperia
sales office. In case of any inconsistency or conflict with the
Nexperia does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
customer’s third party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications
short data sheet, the full data sheet shall prevail.
and the products or of the application or use by customer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Product specification
— The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
Limiting values
— Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
12.3 Disclaimers
Terms and conditions of commercial sale
— Nexperia
Limited warranty and liability
— Information in this document is believed
to be accurate and reliable. However, Nexperia does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an information
source outside of Nexperia.
products are sold subject to the general terms and conditions of commercial
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
©
BUK9880-55A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
19 March 2014
11 / 13
Nexperia
BUK9880-55A
N-channel TrenchMOS logic level FET
No offer to sell or license
— Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control
— This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations
— A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
12.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
©
BUK9880-55A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
19 March 2014
12 / 13
Nexperia
BUK9880-55A
N-channel TrenchMOS logic level FET
13. Contents
1
2
3
4
5
6
7
8
9
10
11
12
12.1
12.2
12.3
12.4
©
Nexperia B.V. 2017. All rights reserved
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release:
19 March 2014
©
BUK9880-55A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
19 March 2014
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