Nexperia-BUK9K89-100E-115
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BUK9K89-100E
Dual N-channel TrenchMOS logic level FET
23 April 2013
Product data sheet
1. General
description
Dual logic level N-channel MOSFET in a LFPAK56D package using TrenchMOS
technology. This product has been designed and qualified to AEC Q101 standard for use
in high performance automotive applications.
2. Features
and benefits
Q101 compliant
Repetitive avalanche rated
Suitable for thermally demanding environments due to 175 °C rating
True logic level gate with V
GS(th)
> 0.5 V @ 175 °C
•
•
•
•
3. Applications
12 V Automotive systems
•
•
•
•
•
Motors, lamps and solenoid control
Start-stop micro-hybrid applications
Transmission control
Ultra high performance power switching
4. Quick
reference data
Table 1.
Symbol
Quick reference data
Parameter
Conditions
Min
Typ
Max
100
12.5
38
Unit
V
V
DS
I
D
drain-source voltage
drain current
T
j
≥ 25 °C; T
j
≤ 175 °C
–
–
–
–
–
–
A
P
tot
W
Static characteristics FET1 and FET2
R
DSon
drain-source on-state
resistance
–
–
75.8
4.2
89
–
mΩ
nC
Dynamic characteristics FET1 and FET2
Q
GD
gate-drain charge
I
D
= 5 A; V
DS
= 80 V; V
GS
= 10 V;
Nexperia
BUK9K89-100E
Dual N-channel TrenchMOS logic level FET
5. Pinning
information
Table 2.
Pin
Pinning information
Symbol Description
Simplified outline
Graphic symbol
8
7
6
5
D1
D2
D2
1
2
3
4
5
6
7
8
S1
G1
S2
G2
D2
D2
D1
D1
source1
gate1
D1
source2
gate2
drain2
drain2
drain1
drain1
S1
G1
S2
G2
mbk725
1
2
3
4
LFPAK56D (SOT1205)
6. Ordering
information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
BUK9K89-100E
LFPAK56D
Plastic single ended surface mounted package (LFPAK56D); 8
leads
SOT1205
7. Marking
Table 4.
Marking codes
Type number
Marking code
BUK9K89-100E
98910E
8. Limiting
values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
Parameter
Conditions
Min
Max
100
100
10
Unit
drain-source voltage
drain-gate voltage
gate-source voltage
T
j
≥ 25 °C; T
j
≤ 175 °C
R
GS
= 20 kΩ; T
j
≥ 25 °C; T
j
≤ 175 °C
T
j
≤ 175 °C; DC
–
V
V
V
V
A
A
A
V
DGR
V
GS
–
-10
-15
–
T
j
≤ 175 °C; Pulsed
15
I
D
drain current
12.5
8.9
50
–
I
DM
peak drain current
All information provided in this document is subject to legal disclaimers.
23 April 2013
–
©
BUK9K89-100E
Nexperia B.V. 2017. All rights reserved
Product data sheet
2 / 13
Nexperia
BUK9K89-100E
Dual N-channel TrenchMOS logic level FET
Symbol
P
tot
Parameter
Conditions
Min
–
Max
38
Unit
W
total power dissipation
storage temperature
junction temperature
peak soldering temperature
T
stg
-55
-55
–
175
175
260
°C
T
j
°C
T
sld(M)
°C
Source-drain diode FET1 and FET2
I
S
source current
T
mb
= 25 °C
–
–
12.5
50
A
A
I
SM
peak source current
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C
Avalanche Ruggedness FET1 and FET2
E
DS(AL)S
non-repetitive drain-source
avalanche energy
I
D
= 12.5 A; V
sup
≤ 100 V; V
GS
= 5 V;
–
21
mJ
[1] Accumulated
Pulse duration up to 50 hours delivers zero defect ppm
[2] Significantly
longer life times are achieved by lowering T
j
and or V
GS
.
[3] Refer
to application note AN10273 for further information
[4] Single-pulse
avalanche rating limited by maximum junction temperature of 175 °C
003aaj685
03aa16
20
16
12
8
120
I
D
(A)
P
der
(%)
80
40
4
0
0
0
30
60
90
120
150
T (°C)
180
0
50
100
150
200
j
T
(°C)
mb
Fig. 1.
Continuous drain current as a function of
mounting base temperature
Fig. 2.
Normalized total power dissipation as a
function of mounting base temperature
©
BUK9K89-100E
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Nexperia B.V. 2017. All rights reserved
Product data sheet
23 April 2013
3 / 13
Nexperia
BUK9K89-100E
Dual N-channel TrenchMOS logic level FET
003aaj666
2
10
I
AL
(A)
10
(1)
1
(2)
(3)
-1
10
-2
10
-3
-2
-1
10
10
10
1
AL
10
t
(ms)
Fig. 3.
Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time, FET1 and
FET2
003aaj684
10
4
I
D
(A)
10
3
10
2
Limit R
= V
/ I
DS D
DSon
t =10
s
µ
s
p
10
1
100
µ
DC
1 ms
10 ms
100 ms
10
-1
10
-2
1
10
10
2
10
3
V
(V)
DS
Fig. 4.
Safe operating area; continuous and peak drain current as a function of drain-source voltage
9. Thermal
characteristics
Table 6.
Symbol
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
3.96
Unit
R
th(j-mb)
thermal resistance
from junction to
mounting base
–
–
K/W
©
BUK9K89-100E
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Nexperia B.V. 2017. All rights reserved
Product data sheet
23 April 2013
4 / 13
Nexperia
BUK9K89-100E
Dual N-channel TrenchMOS logic level FET
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
R
th(j-a)
thermal resistance
from junction to
ambient
Minimum footprint; mounted on a
printed circuit board
–
95
–
K/W
003aaj683
10
Z
th(j-mb)
= 0.5
δ
(K/W)
0.2
1
0.1
0.05
0.02
t
p
δ =
T
P
10
-1
single shot
t
t
p
T
10
-2
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
1
t (s)
p
Fig. 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration
10. Characteristics
Table 7.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics FET1 and FET2
V
(BR)DSS
drain-source
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
90
–
–
V
V
V
breakdown voltage
100
1.4
–
–
V
GS(th)
gate-source threshold
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
1.7
2.1
voltage
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 175 °C;
0.5
–
–
–
–
V
V
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
2.45
I
DSS
drain leakage current
gate leakage current
V
DS
= 100 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 100 V; V
GS
= 0 V; T
j
= 175 °C
V
GS
= -10 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 10 V; V
DS
= 0 V; T
j
= 25 °C
–
–
–
–
–
–
0.02
1
µA
µA
nA
–
500
100
100
89
I
GSS
2
2
nA
R
DSon
drain-source on-state
resistance
75.8
mΩ
mΩ
V
GS
= 5 V; I
D
= 5 A; T
j
= 175 °C;
205.4 245
All information provided in this document is subject to legal disclaimers.
23 April 2013
–
74.9
85
mΩ
©
BUK9K89-100E
Nexperia B.V. 2017. All rights reserved
Product data sheet
5 / 13
Nexperia
BUK9K89-100E
Dual N-channel TrenchMOS logic level FET
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Dynamic characteristics FET1 and FET2
Q
G(tot)
Q
GS
Q
GD
C
iss
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
I
D
= 5 A; V
DS
= 80 V; V
GS
= 10 V;
–
–
–
–
–
–
16.8
1.7
4.2
831
81
–
nC
nC
nC
pF
pF
pF
–
–
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
1108
97
81
C
oss
C
rss
reverse transfer
capacitance
59
t
d(on)
t
r
t
d(off)
t
f
turn-on delay time
rise time
V
DS
= 80 V; R
L
= 16 Ω; V
GS
= 10 V;
R
G(ext)
= 10 Ω; T
j
= 25 °C; I
D
= 5 A
–
–
–
–
3.6
–
–
–
–
ns
ns
ns
ns
5.8
turn-off delay time
fall time
22.1
12.1
Source-drain diode FET1 and FET2
V
SD
source-drain voltage
t
rr
–
–
–
0.78
29.9
39.9
1.2
V
reverse recovery time
I
S
= 5 A; dI
S
/dt = -100 A/µs; V
GS
= 0 V;
–
–
ns
nC
V
DS
= 50 V; T
j
= 25 °C
recovered charge
Q
r
003aaj676
003aaj674
250
50
R
g
DSon
fs
(m
)
(S)
Ω
40
200
30
20
10
0
150
100
50
0
0
5
10
15
20
0
4
8
12
16
I
(A)
V
(V)
GS
D
Fig. 7.
Drain-source on-state resistance as a function
of gate-source voltage; typical values
Fig. 6.
Forward transconductance as a function of
drain current; typical values
©
BUK9K89-100E
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Nexperia B.V. 2017. All rights reserved
Product data sheet
23 April 2013
6 / 13
Nexperia
BUK9K89-100E
Dual N-channel TrenchMOS logic level FET
003aaj677
003aaj675
20
60
I
4.5
3.5
D
I
D
(A)
(A)
10
15
45
V
(V) =
3
GS
10
5
30
15
0
2.8
2.6
T = 175
C
°
T = 25
C
°
j
j
2.4
2.2
0
0
2.5
5
7.5
10
0
1
2
3
4
5
6
V
(V)
V
(V)
GS
DS
Fig. 8.
Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig. 9.
Transfer characteristics: drain current as a
function of gate-source voltage; typical values
003aah026
003aah025
3
10
-1
V
GS(th)
(V)
I
D
(A)
2.5
10
-2
max
2
min
typ
max
10
-3
10
-4
10
-5
10
-6
typ
1.5
min
1
0.5
0
-60
0
60
120
180
0
1
2
3
T ( C)
V
GS
(V)
°
j
Fig. 10.
Gate-source threshold voltage as a function of
Fig. 11.
Sub-threshold drain current as a function of
junction temperature
gate-source voltage
©
BUK9K89-100E
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Nexperia B.V. 2017. All rights reserved
Product data sheet
23 April 2013
7 / 13
Nexperia
BUK9K89-100E
Dual N-channel TrenchMOS logic level FET
003aaj682
003aaj820
300
3
2.4
1.8
1.2
0.6
0
R
DSon
a
(m
)
Ω
2.6
2.8
3
250
200
150
100
50
V
(V) = 3.5
10
GS
4.5
0
0
5
10
15
20
-60
0
60
120
180
I (A)
T
j
°C)
D
(
Fig. 13.
Normalized drain-source on-state resistance
factor as a function of junction temperature
Fig. 12.
Drain-source on-state resistance as a function
of drain current; typical values
003aaj679
10
V
DS
V
GS
(V)
8
I
D
V
=
80 V
DS
V
GS(pl)
6
4
2
0
14 V
V
GS(th)
GS
V
Q
Q
GS1
GS2
Q
Q
GD
GS
Q
G(tot)
003aaa508
Fig. 14.
Gate charge waveform definitions
0
5
10
15
20
Q
(nC)
G
Fig. 15.
Gate-source voltage as a function of gate
charge; typical values
©
BUK9K89-100E
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Nexperia B.V. 2017. All rights reserved
Product data sheet
23 April 2013
8 / 13
Nexperia
BUK9K89-100E
Dual N-channel TrenchMOS logic level FET
003aaj680
003aaj681
10
4
30
C
(pF)
I
S
(A)
C
iss
10
3
20
C
10
2
10
oss
T =
175 C
°
T =
25 C
°
j
j
C
rss
10
0
10
-1
1
10
10
2
0
0.3
0.6
0.9
V
1.2
(V)
V
(V)
SD
DS
Fig. 16.
Input, output and reverse transfer capacitances
Fig. 17.
Source current as a function of source-drain
as a function of drain-source voltage; typical
values
voltage; typical values
©
BUK9K89-100E
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
23 April 2013
9 / 13
Nexperia
BUK9K89-100E
Dual N-channel TrenchMOS logic level FET
11. Package
outline
Plastic single ended surface mounted package (LFPAK56D); 8 leads
SOT1205
E
A
A
b
c
1
1
L
1
mounting
base
D
1
D
D
2
H
L
1
2
3
4
X
b
(8x)
e
c
E
1
w
A
E
2
C
A
1
θ
L
p
y
C
detail X
0
2.5
5 mm
scale
Dimensions
Unit
D
(ref)
2
(1)
(1)
(1)
E
(1)
A
A
b
b
c
c
D
D
1
E
E
e
H
L
L
L
p
w
y
θ
1
1
1
1
2
1
°
8
0
max 1.05
0.1 0.50 4.4 0.25
0.30 4.70
4.8
nom
5.30 1.8 0.85
4.95 1.6
6.2 1.3
0.55 0.85
5.9 0.8
0.30 0.40
mm
3.5
1.27
0.25 0.1
°
min
0.0 0.35 4.1 0.19
0.24 4.45
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
sot1205_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
13-02-19
13-02-21
SOT1205
Fig. 18.
Package outline LFPAK56D (SOT1205)
©
BUK9K89-100E
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
23 April 2013
10 / 13
Nexperia
BUK9K89-100E
Dual N-channel TrenchMOS logic level FET
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including – without limitation –
lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
12. Legal information
12.1 Data
sheet status
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the
Terms and conditions of commercial sale
of Nexperia.
Document
Product
Definition
Objective
[short] data
sheet
Development This
document contains data from
the objective specification for product
development.
Right to make changes
— Nexperia reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Preliminary
[short] data
sheet
Qualification This
document contains data from the
preliminary specification.
Suitability for use in automotive applications
— This Nexperia
product has been qualified for use in automotive
Product
[short] data
sheet
Production
This document contains the product
specification.
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
[1] Please
consult the most recently issued document before initiating or
completing a design.
[2] The
term ‘short data sheet’ is explained in section “Definitions”.
[3] The
product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
Quick reference data
— The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
12.2 Definitions
Applications
— Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Preview
— The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
Nexperia does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
no liability for the consequences of use of such information.
Customers are responsible for the design and operation of their
applications and products using Nexperia products, and Nexperia
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the Nexperia product is suitable and fit for the
Draft
— The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
Short data sheet
— A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local Nexperia
sales office. In case of any inconsistency or conflict with the
Nexperia does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
customer’s third party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications
short data sheet, the full data sheet shall prevail.
and the products or of the application or use by customer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Product specification
— The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
Limiting values
— Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
12.3 Disclaimers
Terms and conditions of commercial sale
— Nexperia
Limited warranty and liability
— Information in this document is believed
to be accurate and reliable. However, Nexperia does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an information
source outside of Nexperia.
products are sold subject to the general terms and conditions of commercial
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
©
BUK9K89-100E
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
23 April 2013
11 / 13
Nexperia
BUK9K89-100E
Dual N-channel TrenchMOS logic level FET
No offer to sell or license
— Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control
— This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations
— A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
12.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
©
BUK9K89-100E
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
23 April 2013
12 / 13
Nexperia
BUK9K89-100E
Dual N-channel TrenchMOS logic level FET
13. Contents
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©
Nexperia B.V. 2017. All rights reserved
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release:
23 April 2013
©
BUK9K89-100E
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
23 April 2013
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